Re: [PATCH 14/17] drm/msm/dpu: modify encoder programming for CDM over DP

2024-02-01 Thread Abhinav Kumar 




On 1/31/2024 7:17 PM, Dmitry Baryshkov wrote:

On Thu, 1 Feb 2024 at 03:30, Abhinav Kumar  wrote:




On 1/29/2024 3:44 PM, Dmitry Baryshkov wrote:

On Mon, 29 Jan 2024 at 09:08, Abhinav Kumar  wrote:


On 1/28/2024 10:12 PM, Dmitry Baryshkov wrote:

On Mon, 29 Jan 2024 at 07:03, Abhinav Kumar  wrote:




On 1/28/2024 7:42 PM, Dmitry Baryshkov wrote:

On Mon, 29 Jan 2024 at 04:58, Abhinav Kumar  wrote:




On 1/27/2024 9:55 PM, Dmitry Baryshkov wrote:

On Sun, 28 Jan 2024 at 07:48, Paloma Arellano  wrote:



On 1/25/2024 1:57 PM, Dmitry Baryshkov wrote:

On 25/01/2024 21:38, Paloma Arellano wrote:

Adjust the encoder format programming in the case of video mode for DP
to accommodate CDM related changes.

Signed-off-by: Paloma Arellano 
---
   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   | 16 +
   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |  8 +
   .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  | 35 ---
   drivers/gpu/drm/msm/dp/dp_display.c   | 12 +++
   drivers/gpu/drm/msm/msm_drv.h |  9 -
   5 files changed, 75 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index b0896814c1562..99ec53446ad21 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -222,6 +222,22 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
   15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
   };
   +u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
const struct drm_display_mode *mode)
+{
+const struct dpu_encoder_virt *dpu_enc;
+const struct msm_display_info *disp_info;
+struct msm_drm_private *priv;
+
+dpu_enc = to_dpu_encoder_virt(drm_enc);
+disp_info = _enc->disp_info;
+priv = drm_enc->dev->dev_private;
+
+if (disp_info->intf_type == INTF_DP &&
+ msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]],
mode))


This should not require interacting with DP. If we got here, we must
be sure that 4:2:0 is supported and can be configured.

Ack. Will drop this function and only check for if the mode is YUV420.



+return DRM_FORMAT_YUV420;
+
+return DRM_FORMAT_RGB888;
+}
 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
*drm_enc)
   {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 7b4afa71f1f96..62255d0aa4487 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -162,6 +162,14 @@ int dpu_encoder_get_vsync_count(struct
drm_encoder *drm_enc);
*/
   bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
*drm_enc);
   +/**
+ * dpu_encoder_get_drm_fmt - return DRM fourcc format
+ * @drm_enc:Pointer to previously created drm encoder structure
+ * @mode:Corresponding drm_display_mode for dpu encoder
+ */
+u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
+const struct drm_display_mode *mode);
+
   /**
* dpu_encoder_get_crc_values_cnt - get number of physical encoders
contained
*in virtual encoder that can collect CRC values
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index e284bf448bdda..a1dde0ff35dc8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -234,6 +234,7 @@ static void
dpu_encoder_phys_vid_setup_timing_engine(
   {
   struct drm_display_mode mode;
   struct dpu_hw_intf_timing_params timing_params = { 0 };
+struct dpu_hw_cdm *hw_cdm;
   const struct dpu_format *fmt = NULL;
   u32 fmt_fourcc = DRM_FORMAT_RGB888;
   unsigned long lock_flags;
@@ -254,17 +255,26 @@ static void
dpu_encoder_phys_vid_setup_timing_engine(
   DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
   drm_mode_debug_printmodeline();
   -if (phys_enc->split_role != ENC_ROLE_SOLO) {
+hw_cdm = phys_enc->hw_cdm;
+if (hw_cdm) {
+intf_cfg.cdm = hw_cdm->idx;
+fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc->parent, );
+}
+
+if (phys_enc->split_role != ENC_ROLE_SOLO ||
+dpu_encoder_get_drm_fmt(phys_enc->parent, ) ==
DRM_FORMAT_YUV420) {
   mode.hdisplay >>= 1;
   mode.htotal >>= 1;
   mode.hsync_start >>= 1;
   mode.hsync_end >>= 1;
+mode.hskew >>= 1;


Separate patch.

Ack.



 DPU_DEBUG_VIDENC(phys_enc,
-"split_role %d, halve horizontal %d %d %d %d\n",
+"split_role %d, halve horizontal %d %d %d %d %d\n",
   phys_enc->split_role,
   mode.hdisplay, mode.htotal,
-mode.hsync_start, mode.hsync_end);
+mode.hsync_start, mode.hsync_end,
+

Re: [PATCH 14/17] drm/msm/dpu: modify encoder programming for CDM over DP

2024-01-31 Thread Dmitry Baryshkov 
On Thu, 1 Feb 2024 at 03:30, Abhinav Kumar  wrote:
>
>
>
> On 1/29/2024 3:44 PM, Dmitry Baryshkov wrote:
> > On Mon, 29 Jan 2024 at 09:08, Abhinav Kumar  
> > wrote:
> >>
> >> On 1/28/2024 10:12 PM, Dmitry Baryshkov wrote:
> >>> On Mon, 29 Jan 2024 at 07:03, Abhinav Kumar  
> >>> wrote:
> 
> 
> 
>  On 1/28/2024 7:42 PM, Dmitry Baryshkov wrote:
> > On Mon, 29 Jan 2024 at 04:58, Abhinav Kumar  
> > wrote:
> >>
> >>
> >>
> >> On 1/27/2024 9:55 PM, Dmitry Baryshkov wrote:
> >>> On Sun, 28 Jan 2024 at 07:48, Paloma Arellano 
> >>>  wrote:
> 
> 
>  On 1/25/2024 1:57 PM, Dmitry Baryshkov wrote:
> > On 25/01/2024 21:38, Paloma Arellano wrote:
> >> Adjust the encoder format programming in the case of video mode 
> >> for DP
> >> to accommodate CDM related changes.
> >>
> >> Signed-off-by: Paloma Arellano 
> >> ---
> >>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   | 16 +
> >>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |  8 +
> >>   .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  | 35 
> >> ---
> >>   drivers/gpu/drm/msm/dp/dp_display.c   | 12 +++
> >>   drivers/gpu/drm/msm/msm_drv.h |  9 -
> >>   5 files changed, 75 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >> index b0896814c1562..99ec53446ad21 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >> @@ -222,6 +222,22 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
> >>   15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
> >>   };
> >>   +u32 dpu_encoder_get_drm_fmt(const struct drm_encoder 
> >> *drm_enc,
> >> const struct drm_display_mode *mode)
> >> +{
> >> +const struct dpu_encoder_virt *dpu_enc;
> >> +const struct msm_display_info *disp_info;
> >> +struct msm_drm_private *priv;
> >> +
> >> +dpu_enc = to_dpu_encoder_virt(drm_enc);
> >> +disp_info = _enc->disp_info;
> >> +priv = drm_enc->dev->dev_private;
> >> +
> >> +if (disp_info->intf_type == INTF_DP &&
> >> + 
> >> msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]],
> >> mode))
> >
> > This should not require interacting with DP. If we got here, we must
> > be sure that 4:2:0 is supported and can be configured.
>  Ack. Will drop this function and only check for if the mode is 
>  YUV420.
> >
> >> +return DRM_FORMAT_YUV420;
> >> +
> >> +return DRM_FORMAT_RGB888;
> >> +}
> >> bool dpu_encoder_is_widebus_enabled(const struct 
> >> drm_encoder
> >> *drm_enc)
> >>   {
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> >> index 7b4afa71f1f96..62255d0aa4487 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> >> @@ -162,6 +162,14 @@ int dpu_encoder_get_vsync_count(struct
> >> drm_encoder *drm_enc);
> >>*/
> >>   bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
> >> *drm_enc);
> >>   +/**
> >> + * dpu_encoder_get_drm_fmt - return DRM fourcc format
> >> + * @drm_enc:Pointer to previously created drm encoder 
> >> structure
> >> + * @mode:Corresponding drm_display_mode for dpu encoder
> >> + */
> >> +u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
> >> +const struct drm_display_mode *mode);
> >> +
> >>   /**
> >>* dpu_encoder_get_crc_values_cnt - get number of physical 
> >> encoders
> >> contained
> >>*in virtual encoder that can collect CRC values
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> >> index e284bf448bdda..a1dde0ff35dc8 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> >> @@ -234,6 +234,7 @@ static void
> >> dpu_encoder_phys_vid_setup_timing_engine(
> >>   {
> >>   struct drm_display_mode mode;
> >>   struct dpu_hw_intf_timing_params timing_params = { 0 };
> >> +struct dpu_hw_cdm *hw_cdm;
>

Re: [PATCH 14/17] drm/msm/dpu: modify encoder programming for CDM over DP

2024-01-31 Thread Abhinav Kumar 




On 1/29/2024 3:44 PM, Dmitry Baryshkov wrote:

On Mon, 29 Jan 2024 at 09:08, Abhinav Kumar  wrote:


On 1/28/2024 10:12 PM, Dmitry Baryshkov wrote:

On Mon, 29 Jan 2024 at 07:03, Abhinav Kumar  wrote:




On 1/28/2024 7:42 PM, Dmitry Baryshkov wrote:

On Mon, 29 Jan 2024 at 04:58, Abhinav Kumar  wrote:




On 1/27/2024 9:55 PM, Dmitry Baryshkov wrote:

On Sun, 28 Jan 2024 at 07:48, Paloma Arellano  wrote:



On 1/25/2024 1:57 PM, Dmitry Baryshkov wrote:

On 25/01/2024 21:38, Paloma Arellano wrote:

Adjust the encoder format programming in the case of video mode for DP
to accommodate CDM related changes.

Signed-off-by: Paloma Arellano 
---
  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   | 16 +
  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |  8 +
  .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  | 35 ---
  drivers/gpu/drm/msm/dp/dp_display.c   | 12 +++
  drivers/gpu/drm/msm/msm_drv.h |  9 -
  5 files changed, 75 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index b0896814c1562..99ec53446ad21 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -222,6 +222,22 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
  15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
  };
  +u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
const struct drm_display_mode *mode)
+{
+const struct dpu_encoder_virt *dpu_enc;
+const struct msm_display_info *disp_info;
+struct msm_drm_private *priv;
+
+dpu_enc = to_dpu_encoder_virt(drm_enc);
+disp_info = _enc->disp_info;
+priv = drm_enc->dev->dev_private;
+
+if (disp_info->intf_type == INTF_DP &&
+ msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]],
mode))


This should not require interacting with DP. If we got here, we must
be sure that 4:2:0 is supported and can be configured.

Ack. Will drop this function and only check for if the mode is YUV420.



+return DRM_FORMAT_YUV420;
+
+return DRM_FORMAT_RGB888;
+}
bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
*drm_enc)
  {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 7b4afa71f1f96..62255d0aa4487 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -162,6 +162,14 @@ int dpu_encoder_get_vsync_count(struct
drm_encoder *drm_enc);
   */
  bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
*drm_enc);
  +/**
+ * dpu_encoder_get_drm_fmt - return DRM fourcc format
+ * @drm_enc:Pointer to previously created drm encoder structure
+ * @mode:Corresponding drm_display_mode for dpu encoder
+ */
+u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
+const struct drm_display_mode *mode);
+
  /**
   * dpu_encoder_get_crc_values_cnt - get number of physical encoders
contained
   *in virtual encoder that can collect CRC values
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index e284bf448bdda..a1dde0ff35dc8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -234,6 +234,7 @@ static void
dpu_encoder_phys_vid_setup_timing_engine(
  {
  struct drm_display_mode mode;
  struct dpu_hw_intf_timing_params timing_params = { 0 };
+struct dpu_hw_cdm *hw_cdm;
  const struct dpu_format *fmt = NULL;
  u32 fmt_fourcc = DRM_FORMAT_RGB888;
  unsigned long lock_flags;
@@ -254,17 +255,26 @@ static void
dpu_encoder_phys_vid_setup_timing_engine(
  DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
  drm_mode_debug_printmodeline();
  -if (phys_enc->split_role != ENC_ROLE_SOLO) {
+hw_cdm = phys_enc->hw_cdm;
+if (hw_cdm) {
+intf_cfg.cdm = hw_cdm->idx;
+fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc->parent, );
+}
+
+if (phys_enc->split_role != ENC_ROLE_SOLO ||
+dpu_encoder_get_drm_fmt(phys_enc->parent, ) ==
DRM_FORMAT_YUV420) {
  mode.hdisplay >>= 1;
  mode.htotal >>= 1;
  mode.hsync_start >>= 1;
  mode.hsync_end >>= 1;
+mode.hskew >>= 1;


Separate patch.

Ack.



DPU_DEBUG_VIDENC(phys_enc,
-"split_role %d, halve horizontal %d %d %d %d\n",
+"split_role %d, halve horizontal %d %d %d %d %d\n",
  phys_enc->split_role,
  mode.hdisplay, mode.htotal,
-mode.hsync_start, mode.hsync_end);
+mode.hsync_start, mode.hsync_end,
+mode.hskew);
  }
drm_mode_to_intf_timing_params(phys_enc, , _params);
@@ -412,8 +422,15 @@ static int

Re: [PATCH 14/17] drm/msm/dpu: modify encoder programming for CDM over DP

2024-01-29 Thread Dmitry Baryshkov 
On Mon, 29 Jan 2024 at 09:08, Abhinav Kumar  wrote:
>
> On 1/28/2024 10:12 PM, Dmitry Baryshkov wrote:
> > On Mon, 29 Jan 2024 at 07:03, Abhinav Kumar  
> > wrote:
> >>
> >>
> >>
> >> On 1/28/2024 7:42 PM, Dmitry Baryshkov wrote:
> >>> On Mon, 29 Jan 2024 at 04:58, Abhinav Kumar  
> >>> wrote:
> 
> 
> 
>  On 1/27/2024 9:55 PM, Dmitry Baryshkov wrote:
> > On Sun, 28 Jan 2024 at 07:48, Paloma Arellano 
> >  wrote:
> >>
> >>
> >> On 1/25/2024 1:57 PM, Dmitry Baryshkov wrote:
> >>> On 25/01/2024 21:38, Paloma Arellano wrote:
>  Adjust the encoder format programming in the case of video mode for 
>  DP
>  to accommodate CDM related changes.
> 
>  Signed-off-by: Paloma Arellano 
>  ---
>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   | 16 +
>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |  8 +
>   .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  | 35 
>  ---
>   drivers/gpu/drm/msm/dp/dp_display.c   | 12 +++
>   drivers/gpu/drm/msm/msm_drv.h |  9 -
>   5 files changed, 75 insertions(+), 5 deletions(-)
> 
>  diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>  b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>  index b0896814c1562..99ec53446ad21 100644
>  --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>  +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>  @@ -222,6 +222,22 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
>   15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
>   };
>   +u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
>  const struct drm_display_mode *mode)
>  +{
>  +const struct dpu_encoder_virt *dpu_enc;
>  +const struct msm_display_info *disp_info;
>  +struct msm_drm_private *priv;
>  +
>  +dpu_enc = to_dpu_encoder_virt(drm_enc);
>  +disp_info = _enc->disp_info;
>  +priv = drm_enc->dev->dev_private;
>  +
>  +if (disp_info->intf_type == INTF_DP &&
>  + msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]],
>  mode))
> >>>
> >>> This should not require interacting with DP. If we got here, we must
> >>> be sure that 4:2:0 is supported and can be configured.
> >> Ack. Will drop this function and only check for if the mode is YUV420.
> >>>
>  +return DRM_FORMAT_YUV420;
>  +
>  +return DRM_FORMAT_RGB888;
>  +}
> bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
>  *drm_enc)
>   {
>  diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>  b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>  index 7b4afa71f1f96..62255d0aa4487 100644
>  --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>  +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>  @@ -162,6 +162,14 @@ int dpu_encoder_get_vsync_count(struct
>  drm_encoder *drm_enc);
>    */
>   bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
>  *drm_enc);
>   +/**
>  + * dpu_encoder_get_drm_fmt - return DRM fourcc format
>  + * @drm_enc:Pointer to previously created drm encoder structure
>  + * @mode:Corresponding drm_display_mode for dpu encoder
>  + */
>  +u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
>  +const struct drm_display_mode *mode);
>  +
>   /**
>    * dpu_encoder_get_crc_values_cnt - get number of physical 
>  encoders
>  contained
>    *in virtual encoder that can collect CRC values
>  diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>  b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>  index e284bf448bdda..a1dde0ff35dc8 100644
>  --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>  +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>  @@ -234,6 +234,7 @@ static void
>  dpu_encoder_phys_vid_setup_timing_engine(
>   {
>   struct drm_display_mode mode;
>   struct dpu_hw_intf_timing_params timing_params = { 0 };
>  +struct dpu_hw_cdm *hw_cdm;
>   const struct dpu_format *fmt = NULL;
>   u32 fmt_fourcc = DRM_FORMAT_RGB888;
>   unsigned long lock_flags;
>  @@ -254,17 +255,26 @@ static void
>  dpu_encoder_phys_vid_setup_timing_engine(
>   DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
>   drm_mode_debug_printmodeline();
>   -if

Re: [PATCH 14/17] drm/msm/dpu: modify encoder programming for CDM over DP

2024-01-28 Thread Abhinav Kumar 




On 1/28/2024 10:12 PM, Dmitry Baryshkov wrote:

On Mon, 29 Jan 2024 at 07:03, Abhinav Kumar  wrote:




On 1/28/2024 7:42 PM, Dmitry Baryshkov wrote:

On Mon, 29 Jan 2024 at 04:58, Abhinav Kumar  wrote:




On 1/27/2024 9:55 PM, Dmitry Baryshkov wrote:

On Sun, 28 Jan 2024 at 07:48, Paloma Arellano  wrote:



On 1/25/2024 1:57 PM, Dmitry Baryshkov wrote:

On 25/01/2024 21:38, Paloma Arellano wrote:

Adjust the encoder format programming in the case of video mode for DP
to accommodate CDM related changes.

Signed-off-by: Paloma Arellano 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   | 16 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |  8 +
 .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  | 35 ---
 drivers/gpu/drm/msm/dp/dp_display.c   | 12 +++
 drivers/gpu/drm/msm/msm_drv.h |  9 -
 5 files changed, 75 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index b0896814c1562..99ec53446ad21 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -222,6 +222,22 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
 };
 +u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
const struct drm_display_mode *mode)
+{
+const struct dpu_encoder_virt *dpu_enc;
+const struct msm_display_info *disp_info;
+struct msm_drm_private *priv;
+
+dpu_enc = to_dpu_encoder_virt(drm_enc);
+disp_info = _enc->disp_info;
+priv = drm_enc->dev->dev_private;
+
+if (disp_info->intf_type == INTF_DP &&
+ msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]],
mode))


This should not require interacting with DP. If we got here, we must
be sure that 4:2:0 is supported and can be configured.

Ack. Will drop this function and only check for if the mode is YUV420.



+return DRM_FORMAT_YUV420;
+
+return DRM_FORMAT_RGB888;
+}
   bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
*drm_enc)
 {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 7b4afa71f1f96..62255d0aa4487 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -162,6 +162,14 @@ int dpu_encoder_get_vsync_count(struct
drm_encoder *drm_enc);
  */
 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
*drm_enc);
 +/**
+ * dpu_encoder_get_drm_fmt - return DRM fourcc format
+ * @drm_enc:Pointer to previously created drm encoder structure
+ * @mode:Corresponding drm_display_mode for dpu encoder
+ */
+u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
+const struct drm_display_mode *mode);
+
 /**
  * dpu_encoder_get_crc_values_cnt - get number of physical encoders
contained
  *in virtual encoder that can collect CRC values
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index e284bf448bdda..a1dde0ff35dc8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -234,6 +234,7 @@ static void
dpu_encoder_phys_vid_setup_timing_engine(
 {
 struct drm_display_mode mode;
 struct dpu_hw_intf_timing_params timing_params = { 0 };
+struct dpu_hw_cdm *hw_cdm;
 const struct dpu_format *fmt = NULL;
 u32 fmt_fourcc = DRM_FORMAT_RGB888;
 unsigned long lock_flags;
@@ -254,17 +255,26 @@ static void
dpu_encoder_phys_vid_setup_timing_engine(
 DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
 drm_mode_debug_printmodeline();
 -if (phys_enc->split_role != ENC_ROLE_SOLO) {
+hw_cdm = phys_enc->hw_cdm;
+if (hw_cdm) {
+intf_cfg.cdm = hw_cdm->idx;
+fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc->parent, );
+}
+
+if (phys_enc->split_role != ENC_ROLE_SOLO ||
+dpu_encoder_get_drm_fmt(phys_enc->parent, ) ==
DRM_FORMAT_YUV420) {
 mode.hdisplay >>= 1;
 mode.htotal >>= 1;
 mode.hsync_start >>= 1;
 mode.hsync_end >>= 1;
+mode.hskew >>= 1;


Separate patch.

Ack.



   DPU_DEBUG_VIDENC(phys_enc,
-"split_role %d, halve horizontal %d %d %d %d\n",
+"split_role %d, halve horizontal %d %d %d %d %d\n",
 phys_enc->split_role,
 mode.hdisplay, mode.htotal,
-mode.hsync_start, mode.hsync_end);
+mode.hsync_start, mode.hsync_end,
+mode.hskew);
 }
   drm_mode_to_intf_timing_params(phys_enc, , _params);
@@ -412,8 +422,15 @@ static int dpu_encoder_phys_vid_control_vblank_irq(
 static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys
*phys_enc)
 {

Re: [PATCH 14/17] drm/msm/dpu: modify encoder programming for CDM over DP

2024-01-28 Thread Dmitry Baryshkov 
On Mon, 29 Jan 2024 at 07:03, Abhinav Kumar  wrote:
>
>
>
> On 1/28/2024 7:42 PM, Dmitry Baryshkov wrote:
> > On Mon, 29 Jan 2024 at 04:58, Abhinav Kumar  
> > wrote:
> >>
> >>
> >>
> >> On 1/27/2024 9:55 PM, Dmitry Baryshkov wrote:
> >>> On Sun, 28 Jan 2024 at 07:48, Paloma Arellano  
> >>> wrote:
> 
> 
>  On 1/25/2024 1:57 PM, Dmitry Baryshkov wrote:
> > On 25/01/2024 21:38, Paloma Arellano wrote:
> >> Adjust the encoder format programming in the case of video mode for DP
> >> to accommodate CDM related changes.
> >>
> >> Signed-off-by: Paloma Arellano 
> >> ---
> >> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   | 16 +
> >> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |  8 +
> >> .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  | 35 
> >> ---
> >> drivers/gpu/drm/msm/dp/dp_display.c   | 12 +++
> >> drivers/gpu/drm/msm/msm_drv.h |  9 -
> >> 5 files changed, 75 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >> index b0896814c1562..99ec53446ad21 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >> @@ -222,6 +222,22 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
> >> 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
> >> };
> >> +u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
> >> const struct drm_display_mode *mode)
> >> +{
> >> +const struct dpu_encoder_virt *dpu_enc;
> >> +const struct msm_display_info *disp_info;
> >> +struct msm_drm_private *priv;
> >> +
> >> +dpu_enc = to_dpu_encoder_virt(drm_enc);
> >> +disp_info = _enc->disp_info;
> >> +priv = drm_enc->dev->dev_private;
> >> +
> >> +if (disp_info->intf_type == INTF_DP &&
> >> + msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]],
> >> mode))
> >
> > This should not require interacting with DP. If we got here, we must
> > be sure that 4:2:0 is supported and can be configured.
>  Ack. Will drop this function and only check for if the mode is YUV420.
> >
> >> +return DRM_FORMAT_YUV420;
> >> +
> >> +return DRM_FORMAT_RGB888;
> >> +}
> >>   bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
> >> *drm_enc)
> >> {
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> >> index 7b4afa71f1f96..62255d0aa4487 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> >> @@ -162,6 +162,14 @@ int dpu_encoder_get_vsync_count(struct
> >> drm_encoder *drm_enc);
> >>  */
> >> bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
> >> *drm_enc);
> >> +/**
> >> + * dpu_encoder_get_drm_fmt - return DRM fourcc format
> >> + * @drm_enc:Pointer to previously created drm encoder structure
> >> + * @mode:Corresponding drm_display_mode for dpu encoder
> >> + */
> >> +u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
> >> +const struct drm_display_mode *mode);
> >> +
> >> /**
> >>  * dpu_encoder_get_crc_values_cnt - get number of physical encoders
> >> contained
> >>  *in virtual encoder that can collect CRC values
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> >> index e284bf448bdda..a1dde0ff35dc8 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> >> @@ -234,6 +234,7 @@ static void
> >> dpu_encoder_phys_vid_setup_timing_engine(
> >> {
> >> struct drm_display_mode mode;
> >> struct dpu_hw_intf_timing_params timing_params = { 0 };
> >> +struct dpu_hw_cdm *hw_cdm;
> >> const struct dpu_format *fmt = NULL;
> >> u32 fmt_fourcc = DRM_FORMAT_RGB888;
> >> unsigned long lock_flags;
> >> @@ -254,17 +255,26 @@ static void
> >> dpu_encoder_phys_vid_setup_timing_engine(
> >> DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
> >> drm_mode_debug_printmodeline();
> >> -if (phys_enc->split_role != ENC_ROLE_SOLO) {
> >> +hw_cdm = phys_enc->hw_cdm;
> >> +if (hw_cdm) {
> >> +intf_cfg.cdm = hw_cdm->idx;
> >> +fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc->parent, );
> >> +}
> >> +
> >> +if (phys_enc->split_role != ENC_ROLE_SOLO ||
> >> +dpu_encoder_get_drm_fmt(phys_enc->parent, )

Re: [PATCH 14/17] drm/msm/dpu: modify encoder programming for CDM over DP

2024-01-28 Thread Abhinav Kumar 




On 1/28/2024 7:42 PM, Dmitry Baryshkov wrote:

On Mon, 29 Jan 2024 at 04:58, Abhinav Kumar  wrote:




On 1/27/2024 9:55 PM, Dmitry Baryshkov wrote:

On Sun, 28 Jan 2024 at 07:48, Paloma Arellano  wrote:



On 1/25/2024 1:57 PM, Dmitry Baryshkov wrote:

On 25/01/2024 21:38, Paloma Arellano wrote:

Adjust the encoder format programming in the case of video mode for DP
to accommodate CDM related changes.

Signed-off-by: Paloma Arellano 
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   | 16 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |  8 +
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  | 35 ---
drivers/gpu/drm/msm/dp/dp_display.c   | 12 +++
drivers/gpu/drm/msm/msm_drv.h |  9 -
5 files changed, 75 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index b0896814c1562..99ec53446ad21 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -222,6 +222,22 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
};
+u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
const struct drm_display_mode *mode)
+{
+const struct dpu_encoder_virt *dpu_enc;
+const struct msm_display_info *disp_info;
+struct msm_drm_private *priv;
+
+dpu_enc = to_dpu_encoder_virt(drm_enc);
+disp_info = _enc->disp_info;
+priv = drm_enc->dev->dev_private;
+
+if (disp_info->intf_type == INTF_DP &&
+ msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]],
mode))


This should not require interacting with DP. If we got here, we must
be sure that 4:2:0 is supported and can be configured.

Ack. Will drop this function and only check for if the mode is YUV420.



+return DRM_FORMAT_YUV420;
+
+return DRM_FORMAT_RGB888;
+}
  bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
*drm_enc)
{
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 7b4afa71f1f96..62255d0aa4487 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -162,6 +162,14 @@ int dpu_encoder_get_vsync_count(struct
drm_encoder *drm_enc);
 */
bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
*drm_enc);
+/**
+ * dpu_encoder_get_drm_fmt - return DRM fourcc format
+ * @drm_enc:Pointer to previously created drm encoder structure
+ * @mode:Corresponding drm_display_mode for dpu encoder
+ */
+u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
+const struct drm_display_mode *mode);
+
/**
 * dpu_encoder_get_crc_values_cnt - get number of physical encoders
contained
 *in virtual encoder that can collect CRC values
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index e284bf448bdda..a1dde0ff35dc8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -234,6 +234,7 @@ static void
dpu_encoder_phys_vid_setup_timing_engine(
{
struct drm_display_mode mode;
struct dpu_hw_intf_timing_params timing_params = { 0 };
+struct dpu_hw_cdm *hw_cdm;
const struct dpu_format *fmt = NULL;
u32 fmt_fourcc = DRM_FORMAT_RGB888;
unsigned long lock_flags;
@@ -254,17 +255,26 @@ static void
dpu_encoder_phys_vid_setup_timing_engine(
DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
drm_mode_debug_printmodeline();
-if (phys_enc->split_role != ENC_ROLE_SOLO) {
+hw_cdm = phys_enc->hw_cdm;
+if (hw_cdm) {
+intf_cfg.cdm = hw_cdm->idx;
+fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc->parent, );
+}
+
+if (phys_enc->split_role != ENC_ROLE_SOLO ||
+dpu_encoder_get_drm_fmt(phys_enc->parent, ) ==
DRM_FORMAT_YUV420) {
mode.hdisplay >>= 1;
mode.htotal >>= 1;
mode.hsync_start >>= 1;
mode.hsync_end >>= 1;
+mode.hskew >>= 1;


Separate patch.

Ack.



  DPU_DEBUG_VIDENC(phys_enc,
-"split_role %d, halve horizontal %d %d %d %d\n",
+"split_role %d, halve horizontal %d %d %d %d %d\n",
phys_enc->split_role,
mode.hdisplay, mode.htotal,
-mode.hsync_start, mode.hsync_end);
+mode.hsync_start, mode.hsync_end,
+mode.hskew);
}
  drm_mode_to_intf_timing_params(phys_enc, , _params);
@@ -412,8 +422,15 @@ static int dpu_encoder_phys_vid_control_vblank_irq(
static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys
*phys_enc)
{
struct dpu_hw_ctl *ctl;
+struct dpu_hw_cdm *hw_cdm;
+const struct dpu_format *fmt = NULL;
+u32 fmt_fourcc = DRM_FORMAT_RGB888;

Re: [PATCH 14/17] drm/msm/dpu: modify encoder programming for CDM over DP

2024-01-28 Thread Dmitry Baryshkov 
On Mon, 29 Jan 2024 at 04:58, Abhinav Kumar  wrote:
>
>
>
> On 1/27/2024 9:55 PM, Dmitry Baryshkov wrote:
> > On Sun, 28 Jan 2024 at 07:48, Paloma Arellano  
> > wrote:
> >>
> >>
> >> On 1/25/2024 1:57 PM, Dmitry Baryshkov wrote:
> >>> On 25/01/2024 21:38, Paloma Arellano wrote:
>  Adjust the encoder format programming in the case of video mode for DP
>  to accommodate CDM related changes.
> 
>  Signed-off-by: Paloma Arellano 
>  ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   | 16 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |  8 +
> .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  | 35 ---
> drivers/gpu/drm/msm/dp/dp_display.c   | 12 +++
> drivers/gpu/drm/msm/msm_drv.h |  9 -
> 5 files changed, 75 insertions(+), 5 deletions(-)
> 
>  diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>  b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>  index b0896814c1562..99ec53446ad21 100644
>  --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>  +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>  @@ -222,6 +222,22 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
> 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
> };
> +u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
>  const struct drm_display_mode *mode)
>  +{
>  +const struct dpu_encoder_virt *dpu_enc;
>  +const struct msm_display_info *disp_info;
>  +struct msm_drm_private *priv;
>  +
>  +dpu_enc = to_dpu_encoder_virt(drm_enc);
>  +disp_info = _enc->disp_info;
>  +priv = drm_enc->dev->dev_private;
>  +
>  +if (disp_info->intf_type == INTF_DP &&
>  + msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]],
>  mode))
> >>>
> >>> This should not require interacting with DP. If we got here, we must
> >>> be sure that 4:2:0 is supported and can be configured.
> >> Ack. Will drop this function and only check for if the mode is YUV420.
> >>>
>  +return DRM_FORMAT_YUV420;
>  +
>  +return DRM_FORMAT_RGB888;
>  +}
>   bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
>  *drm_enc)
> {
>  diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>  b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>  index 7b4afa71f1f96..62255d0aa4487 100644
>  --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>  +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>  @@ -162,6 +162,14 @@ int dpu_encoder_get_vsync_count(struct
>  drm_encoder *drm_enc);
>  */
> bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
>  *drm_enc);
> +/**
>  + * dpu_encoder_get_drm_fmt - return DRM fourcc format
>  + * @drm_enc:Pointer to previously created drm encoder structure
>  + * @mode:Corresponding drm_display_mode for dpu encoder
>  + */
>  +u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
>  +const struct drm_display_mode *mode);
>  +
> /**
>  * dpu_encoder_get_crc_values_cnt - get number of physical encoders
>  contained
>  *in virtual encoder that can collect CRC values
>  diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>  b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>  index e284bf448bdda..a1dde0ff35dc8 100644
>  --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>  +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>  @@ -234,6 +234,7 @@ static void
>  dpu_encoder_phys_vid_setup_timing_engine(
> {
> struct drm_display_mode mode;
> struct dpu_hw_intf_timing_params timing_params = { 0 };
>  +struct dpu_hw_cdm *hw_cdm;
> const struct dpu_format *fmt = NULL;
> u32 fmt_fourcc = DRM_FORMAT_RGB888;
> unsigned long lock_flags;
>  @@ -254,17 +255,26 @@ static void
>  dpu_encoder_phys_vid_setup_timing_engine(
> DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
> drm_mode_debug_printmodeline();
> -if (phys_enc->split_role != ENC_ROLE_SOLO) {
>  +hw_cdm = phys_enc->hw_cdm;
>  +if (hw_cdm) {
>  +intf_cfg.cdm = hw_cdm->idx;
>  +fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc->parent, );
>  +}
>  +
>  +if (phys_enc->split_role != ENC_ROLE_SOLO ||
>  +dpu_encoder_get_drm_fmt(phys_enc->parent, ) ==
>  DRM_FORMAT_YUV420) {
> mode.hdisplay >>= 1;
> mode.htotal >>= 1;
> mode.hsync_start >>= 1;
> mode.hsync_end >>= 1;
>  +mode.hskew >>= 1;
> >>>
> >>> Separate patch.
> >> Ack.
> >>>
>   DPU_DEBUG_VIDENC(phys_enc,
>  -"split_role %d, halve horizontal

Re: [PATCH 14/17] drm/msm/dpu: modify encoder programming for CDM over DP

2024-01-28 Thread Abhinav Kumar 




On 1/27/2024 9:55 PM, Dmitry Baryshkov wrote:

On Sun, 28 Jan 2024 at 07:48, Paloma Arellano  wrote:



On 1/25/2024 1:57 PM, Dmitry Baryshkov wrote:

On 25/01/2024 21:38, Paloma Arellano wrote:

Adjust the encoder format programming in the case of video mode for DP
to accommodate CDM related changes.

Signed-off-by: Paloma Arellano 
---
   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   | 16 +
   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |  8 +
   .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  | 35 ---
   drivers/gpu/drm/msm/dp/dp_display.c   | 12 +++
   drivers/gpu/drm/msm/msm_drv.h |  9 -
   5 files changed, 75 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index b0896814c1562..99ec53446ad21 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -222,6 +222,22 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
   15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
   };
   +u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
const struct drm_display_mode *mode)
+{
+const struct dpu_encoder_virt *dpu_enc;
+const struct msm_display_info *disp_info;
+struct msm_drm_private *priv;
+
+dpu_enc = to_dpu_encoder_virt(drm_enc);
+disp_info = _enc->disp_info;
+priv = drm_enc->dev->dev_private;
+
+if (disp_info->intf_type == INTF_DP &&
+ msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]],
mode))


This should not require interacting with DP. If we got here, we must
be sure that 4:2:0 is supported and can be configured.

Ack. Will drop this function and only check for if the mode is YUV420.



+return DRM_FORMAT_YUV420;
+
+return DRM_FORMAT_RGB888;
+}
 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
*drm_enc)
   {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 7b4afa71f1f96..62255d0aa4487 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -162,6 +162,14 @@ int dpu_encoder_get_vsync_count(struct
drm_encoder *drm_enc);
*/
   bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
*drm_enc);
   +/**
+ * dpu_encoder_get_drm_fmt - return DRM fourcc format
+ * @drm_enc:Pointer to previously created drm encoder structure
+ * @mode:Corresponding drm_display_mode for dpu encoder
+ */
+u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
+const struct drm_display_mode *mode);
+
   /**
* dpu_encoder_get_crc_values_cnt - get number of physical encoders
contained
*in virtual encoder that can collect CRC values
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index e284bf448bdda..a1dde0ff35dc8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -234,6 +234,7 @@ static void
dpu_encoder_phys_vid_setup_timing_engine(
   {
   struct drm_display_mode mode;
   struct dpu_hw_intf_timing_params timing_params = { 0 };
+struct dpu_hw_cdm *hw_cdm;
   const struct dpu_format *fmt = NULL;
   u32 fmt_fourcc = DRM_FORMAT_RGB888;
   unsigned long lock_flags;
@@ -254,17 +255,26 @@ static void
dpu_encoder_phys_vid_setup_timing_engine(
   DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
   drm_mode_debug_printmodeline();
   -if (phys_enc->split_role != ENC_ROLE_SOLO) {
+hw_cdm = phys_enc->hw_cdm;
+if (hw_cdm) {
+intf_cfg.cdm = hw_cdm->idx;
+fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc->parent, );
+}
+
+if (phys_enc->split_role != ENC_ROLE_SOLO ||
+dpu_encoder_get_drm_fmt(phys_enc->parent, ) ==
DRM_FORMAT_YUV420) {
   mode.hdisplay >>= 1;
   mode.htotal >>= 1;
   mode.hsync_start >>= 1;
   mode.hsync_end >>= 1;
+mode.hskew >>= 1;


Separate patch.

Ack.



 DPU_DEBUG_VIDENC(phys_enc,
-"split_role %d, halve horizontal %d %d %d %d\n",
+"split_role %d, halve horizontal %d %d %d %d %d\n",
   phys_enc->split_role,
   mode.hdisplay, mode.htotal,
-mode.hsync_start, mode.hsync_end);
+mode.hsync_start, mode.hsync_end,
+mode.hskew);
   }
 drm_mode_to_intf_timing_params(phys_enc, , _params);
@@ -412,8 +422,15 @@ static int dpu_encoder_phys_vid_control_vblank_irq(
   static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys
*phys_enc)
   {
   struct dpu_hw_ctl *ctl;
+struct dpu_hw_cdm *hw_cdm;
+const struct dpu_format *fmt = NULL;
+u32 fmt_fourcc = DRM_FORMAT_RGB888;
 ctl = phys_enc->hw_ctl;
+hw_cdm = phys_enc->hw_cdm;
+if (hw_cdm)
+fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc->parent,

Re: [PATCH 14/17] drm/msm/dpu: modify encoder programming for CDM over DP

2024-01-27 Thread Dmitry Baryshkov 
On Sun, 28 Jan 2024 at 07:48, Paloma Arellano  wrote:
>
>
> On 1/25/2024 1:57 PM, Dmitry Baryshkov wrote:
> > On 25/01/2024 21:38, Paloma Arellano wrote:
> >> Adjust the encoder format programming in the case of video mode for DP
> >> to accommodate CDM related changes.
> >>
> >> Signed-off-by: Paloma Arellano 
> >> ---
> >>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   | 16 +
> >>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |  8 +
> >>   .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  | 35 ---
> >>   drivers/gpu/drm/msm/dp/dp_display.c   | 12 +++
> >>   drivers/gpu/drm/msm/msm_drv.h |  9 -
> >>   5 files changed, 75 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >> index b0896814c1562..99ec53446ad21 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> >> @@ -222,6 +222,22 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
> >>   15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
> >>   };
> >>   +u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
> >> const struct drm_display_mode *mode)
> >> +{
> >> +const struct dpu_encoder_virt *dpu_enc;
> >> +const struct msm_display_info *disp_info;
> >> +struct msm_drm_private *priv;
> >> +
> >> +dpu_enc = to_dpu_encoder_virt(drm_enc);
> >> +disp_info = _enc->disp_info;
> >> +priv = drm_enc->dev->dev_private;
> >> +
> >> +if (disp_info->intf_type == INTF_DP &&
> >> + msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]],
> >> mode))
> >
> > This should not require interacting with DP. If we got here, we must
> > be sure that 4:2:0 is supported and can be configured.
> Ack. Will drop this function and only check for if the mode is YUV420.
> >
> >> +return DRM_FORMAT_YUV420;
> >> +
> >> +return DRM_FORMAT_RGB888;
> >> +}
> >> bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
> >> *drm_enc)
> >>   {
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> >> index 7b4afa71f1f96..62255d0aa4487 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> >> @@ -162,6 +162,14 @@ int dpu_encoder_get_vsync_count(struct
> >> drm_encoder *drm_enc);
> >>*/
> >>   bool dpu_encoder_is_widebus_enabled(const struct drm_encoder
> >> *drm_enc);
> >>   +/**
> >> + * dpu_encoder_get_drm_fmt - return DRM fourcc format
> >> + * @drm_enc:Pointer to previously created drm encoder structure
> >> + * @mode:Corresponding drm_display_mode for dpu encoder
> >> + */
> >> +u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
> >> +const struct drm_display_mode *mode);
> >> +
> >>   /**
> >>* dpu_encoder_get_crc_values_cnt - get number of physical encoders
> >> contained
> >>*in virtual encoder that can collect CRC values
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> >> index e284bf448bdda..a1dde0ff35dc8 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> >> @@ -234,6 +234,7 @@ static void
> >> dpu_encoder_phys_vid_setup_timing_engine(
> >>   {
> >>   struct drm_display_mode mode;
> >>   struct dpu_hw_intf_timing_params timing_params = { 0 };
> >> +struct dpu_hw_cdm *hw_cdm;
> >>   const struct dpu_format *fmt = NULL;
> >>   u32 fmt_fourcc = DRM_FORMAT_RGB888;
> >>   unsigned long lock_flags;
> >> @@ -254,17 +255,26 @@ static void
> >> dpu_encoder_phys_vid_setup_timing_engine(
> >>   DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
> >>   drm_mode_debug_printmodeline();
> >>   -if (phys_enc->split_role != ENC_ROLE_SOLO) {
> >> +hw_cdm = phys_enc->hw_cdm;
> >> +if (hw_cdm) {
> >> +intf_cfg.cdm = hw_cdm->idx;
> >> +fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc->parent, );
> >> +}
> >> +
> >> +if (phys_enc->split_role != ENC_ROLE_SOLO ||
> >> +dpu_encoder_get_drm_fmt(phys_enc->parent, ) ==
> >> DRM_FORMAT_YUV420) {
> >>   mode.hdisplay >>= 1;
> >>   mode.htotal >>= 1;
> >>   mode.hsync_start >>= 1;
> >>   mode.hsync_end >>= 1;
> >> +mode.hskew >>= 1;
> >
> > Separate patch.
> Ack.
> >
> >> DPU_DEBUG_VIDENC(phys_enc,
> >> -"split_role %d, halve horizontal %d %d %d %d\n",
> >> +"split_role %d, halve horizontal %d %d %d %d %d\n",
> >>   phys_enc->split_role,
> >>   mode.hdisplay, mode.htotal,
> >> -mode.hsync_start, mode.hsync_end);
> >> +mode.hsync_start, mode.hsync_end,
> >> +mode.hskew);
> >>   }
> >>

Re: [PATCH 14/17] drm/msm/dpu: modify encoder programming for CDM over DP

2024-01-27 Thread Paloma Arellano 



On 1/25/2024 1:57 PM, Dmitry Baryshkov wrote:

On 25/01/2024 21:38, Paloma Arellano wrote:

Adjust the encoder format programming in the case of video mode for DP
to accommodate CDM related changes.

Signed-off-by: Paloma Arellano 
---
  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   | 16 +
  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |  8 +
  .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  | 35 ---
  drivers/gpu/drm/msm/dp/dp_display.c   | 12 +++
  drivers/gpu/drm/msm/msm_drv.h |  9 -
  5 files changed, 75 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

index b0896814c1562..99ec53446ad21 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -222,6 +222,22 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
  15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
  };
  +u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc, 
const struct drm_display_mode *mode)

+{
+    const struct dpu_encoder_virt *dpu_enc;
+    const struct msm_display_info *disp_info;
+    struct msm_drm_private *priv;
+
+    dpu_enc = to_dpu_encoder_virt(drm_enc);
+    disp_info = _enc->disp_info;
+    priv = drm_enc->dev->dev_private;
+
+    if (disp_info->intf_type == INTF_DP &&
+ msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], 
mode))


This should not require interacting with DP. If we got here, we must 
be sure that 4:2:0 is supported and can be configured.

Ack. Will drop this function and only check for if the mode is YUV420.



+    return DRM_FORMAT_YUV420;
+
+    return DRM_FORMAT_RGB888;
+}
    bool dpu_encoder_is_widebus_enabled(const struct drm_encoder 
*drm_enc)

  {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h

index 7b4afa71f1f96..62255d0aa4487 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -162,6 +162,14 @@ int dpu_encoder_get_vsync_count(struct 
drm_encoder *drm_enc);

   */
  bool dpu_encoder_is_widebus_enabled(const struct drm_encoder 
*drm_enc);

  +/**
+ * dpu_encoder_get_drm_fmt - return DRM fourcc format
+ * @drm_enc:    Pointer to previously created drm encoder structure
+ * @mode:    Corresponding drm_display_mode for dpu encoder
+ */
+u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
+    const struct drm_display_mode *mode);
+
  /**
   * dpu_encoder_get_crc_values_cnt - get number of physical encoders 
contained

   *    in virtual encoder that can collect CRC values
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

index e284bf448bdda..a1dde0ff35dc8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -234,6 +234,7 @@ static void 
dpu_encoder_phys_vid_setup_timing_engine(

  {
  struct drm_display_mode mode;
  struct dpu_hw_intf_timing_params timing_params = { 0 };
+    struct dpu_hw_cdm *hw_cdm;
  const struct dpu_format *fmt = NULL;
  u32 fmt_fourcc = DRM_FORMAT_RGB888;
  unsigned long lock_flags;
@@ -254,17 +255,26 @@ static void 
dpu_encoder_phys_vid_setup_timing_engine(

  DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
  drm_mode_debug_printmodeline();
  -    if (phys_enc->split_role != ENC_ROLE_SOLO) {
+    hw_cdm = phys_enc->hw_cdm;
+    if (hw_cdm) {
+    intf_cfg.cdm = hw_cdm->idx;
+    fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc->parent, );
+    }
+
+    if (phys_enc->split_role != ENC_ROLE_SOLO ||
+    dpu_encoder_get_drm_fmt(phys_enc->parent, ) == 
DRM_FORMAT_YUV420) {

  mode.hdisplay >>= 1;
  mode.htotal >>= 1;
  mode.hsync_start >>= 1;
  mode.hsync_end >>= 1;
+    mode.hskew >>= 1;


Separate patch.

Ack.



    DPU_DEBUG_VIDENC(phys_enc,
-    "split_role %d, halve horizontal %d %d %d %d\n",
+    "split_role %d, halve horizontal %d %d %d %d %d\n",
  phys_enc->split_role,
  mode.hdisplay, mode.htotal,
-    mode.hsync_start, mode.hsync_end);
+    mode.hsync_start, mode.hsync_end,
+    mode.hskew);
  }
    drm_mode_to_intf_timing_params(phys_enc, , _params);
@@ -412,8 +422,15 @@ static int dpu_encoder_phys_vid_control_vblank_irq(
  static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys 
*phys_enc)

  {
  struct dpu_hw_ctl *ctl;
+    struct dpu_hw_cdm *hw_cdm;
+    const struct dpu_format *fmt = NULL;
+    u32 fmt_fourcc = DRM_FORMAT_RGB888;
    ctl = phys_enc->hw_ctl;
+    hw_cdm = phys_enc->hw_cdm;
+    if (hw_cdm)
+    fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc->parent, 
_enc->cached_mode);

+    fmt = dpu_get_dpu_format(fmt_fourcc);
    DPU_DEBUG_VIDENC(phys_enc, "\n");
  @@ -422,6

Re: [PATCH 14/17] drm/msm/dpu: modify encoder programming for CDM over DP

2024-01-25 Thread Dmitry Baryshkov 

On 25/01/2024 21:38, Paloma Arellano wrote:

Adjust the encoder format programming in the case of video mode for DP
to accommodate CDM related changes.

Signed-off-by: Paloma Arellano 
---
  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   | 16 +
  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |  8 +
  .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  | 35 ---
  drivers/gpu/drm/msm/dp/dp_display.c   | 12 +++
  drivers/gpu/drm/msm/msm_drv.h |  9 -
  5 files changed, 75 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index b0896814c1562..99ec53446ad21 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -222,6 +222,22 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
  };
  
+u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc, const struct drm_display_mode *mode)

+{
+   const struct dpu_encoder_virt *dpu_enc;
+   const struct msm_display_info *disp_info;
+   struct msm_drm_private *priv;
+
+   dpu_enc = to_dpu_encoder_virt(drm_enc);
+   disp_info = _enc->disp_info;
+   priv = drm_enc->dev->dev_private;
+
+   if (disp_info->intf_type == INTF_DP &&
+   msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], 
mode))


This should not require interacting with DP. If we got here, we must be 
sure that 4:2:0 is supported and can be configured.



+   return DRM_FORMAT_YUV420;
+
+   return DRM_FORMAT_RGB888;
+}
  
  bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)

  {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 7b4afa71f1f96..62255d0aa4487 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -162,6 +162,14 @@ int dpu_encoder_get_vsync_count(struct drm_encoder 
*drm_enc);
   */
  bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc);
  
+/**

+ * dpu_encoder_get_drm_fmt - return DRM fourcc format
+ * @drm_enc:Pointer to previously created drm encoder structure
+ * @mode:  Corresponding drm_display_mode for dpu encoder
+ */
+u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
+   const struct drm_display_mode *mode);
+
  /**
   * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained
   *in virtual encoder that can collect CRC values
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index e284bf448bdda..a1dde0ff35dc8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -234,6 +234,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
  {
struct drm_display_mode mode;
struct dpu_hw_intf_timing_params timing_params = { 0 };
+   struct dpu_hw_cdm *hw_cdm;
const struct dpu_format *fmt = NULL;
u32 fmt_fourcc = DRM_FORMAT_RGB888;
unsigned long lock_flags;
@@ -254,17 +255,26 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
drm_mode_debug_printmodeline();
  
-	if (phys_enc->split_role != ENC_ROLE_SOLO) {

+   hw_cdm = phys_enc->hw_cdm;
+   if (hw_cdm) {
+   intf_cfg.cdm = hw_cdm->idx;
+   fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc->parent, );
+   }
+
+   if (phys_enc->split_role != ENC_ROLE_SOLO ||
+   dpu_encoder_get_drm_fmt(phys_enc->parent, ) == 
DRM_FORMAT_YUV420) {
mode.hdisplay >>= 1;
mode.htotal >>= 1;
mode.hsync_start >>= 1;
mode.hsync_end >>= 1;
+   mode.hskew >>= 1;


Separate patch.

  
  		DPU_DEBUG_VIDENC(phys_enc,

-   "split_role %d, halve horizontal %d %d %d %d\n",
+   "split_role %d, halve horizontal %d %d %d %d %d\n",
phys_enc->split_role,
mode.hdisplay, mode.htotal,
-   mode.hsync_start, mode.hsync_end);
+   mode.hsync_start, mode.hsync_end,
+   mode.hskew);
}
  
  	drm_mode_to_intf_timing_params(phys_enc, , _params);

@@ -412,8 +422,15 @@ static int dpu_encoder_phys_vid_control_vblank_irq(
  static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
  {
struct dpu_hw_ctl *ctl;
+   struct dpu_hw_cdm *hw_cdm;
+   const struct dpu_format *fmt = NULL;
+   u32 fmt_fourcc = DRM_FORMAT_RGB888;
  
  	ctl = phys_enc->hw_ctl;

+   hw_cdm = phys_enc->hw_cdm;
+   if (hw_cdm)
+   fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc->parent, 
_enc->cached_mode);
+   fmt =

[PATCH 14/17] drm/msm/dpu: modify encoder programming for CDM over DP

2024-01-25 Thread Paloma Arellano 
Adjust the encoder format programming in the case of video mode for DP
to accommodate CDM related changes.

Signed-off-by: Paloma Arellano 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   | 16 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |  8 +
 .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  | 35 ---
 drivers/gpu/drm/msm/dp/dp_display.c   | 12 +++
 drivers/gpu/drm/msm/msm_drv.h |  9 -
 5 files changed, 75 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index b0896814c1562..99ec53446ad21 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -222,6 +222,22 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
 };
 
+u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc, const struct 
drm_display_mode *mode)
+{
+   const struct dpu_encoder_virt *dpu_enc;
+   const struct msm_display_info *disp_info;
+   struct msm_drm_private *priv;
+
+   dpu_enc = to_dpu_encoder_virt(drm_enc);
+   disp_info = _enc->disp_info;
+   priv = drm_enc->dev->dev_private;
+
+   if (disp_info->intf_type == INTF_DP &&
+   msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], 
mode))
+   return DRM_FORMAT_YUV420;
+
+   return DRM_FORMAT_RGB888;
+}
 
 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)
 {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 7b4afa71f1f96..62255d0aa4487 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -162,6 +162,14 @@ int dpu_encoder_get_vsync_count(struct drm_encoder 
*drm_enc);
  */
 bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc);
 
+/**
+ * dpu_encoder_get_drm_fmt - return DRM fourcc format
+ * @drm_enc:Pointer to previously created drm encoder structure
+ * @mode:  Corresponding drm_display_mode for dpu encoder
+ */
+u32 dpu_encoder_get_drm_fmt(const struct drm_encoder *drm_enc,
+   const struct drm_display_mode *mode);
+
 /**
  * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained
  * in virtual encoder that can collect CRC values
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index e284bf448bdda..a1dde0ff35dc8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -234,6 +234,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
 {
struct drm_display_mode mode;
struct dpu_hw_intf_timing_params timing_params = { 0 };
+   struct dpu_hw_cdm *hw_cdm;
const struct dpu_format *fmt = NULL;
u32 fmt_fourcc = DRM_FORMAT_RGB888;
unsigned long lock_flags;
@@ -254,17 +255,26 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n");
drm_mode_debug_printmodeline();
 
-   if (phys_enc->split_role != ENC_ROLE_SOLO) {
+   hw_cdm = phys_enc->hw_cdm;
+   if (hw_cdm) {
+   intf_cfg.cdm = hw_cdm->idx;
+   fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc->parent, );
+   }
+
+   if (phys_enc->split_role != ENC_ROLE_SOLO ||
+   dpu_encoder_get_drm_fmt(phys_enc->parent, ) == 
DRM_FORMAT_YUV420) {
mode.hdisplay >>= 1;
mode.htotal >>= 1;
mode.hsync_start >>= 1;
mode.hsync_end >>= 1;
+   mode.hskew >>= 1;
 
DPU_DEBUG_VIDENC(phys_enc,
-   "split_role %d, halve horizontal %d %d %d %d\n",
+   "split_role %d, halve horizontal %d %d %d %d %d\n",
phys_enc->split_role,
mode.hdisplay, mode.htotal,
-   mode.hsync_start, mode.hsync_end);
+   mode.hsync_start, mode.hsync_end,
+   mode.hskew);
}
 
drm_mode_to_intf_timing_params(phys_enc, , _params);
@@ -412,8 +422,15 @@ static int dpu_encoder_phys_vid_control_vblank_irq(
 static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
 {
struct dpu_hw_ctl *ctl;
+   struct dpu_hw_cdm *hw_cdm;
+   const struct dpu_format *fmt = NULL;
+   u32 fmt_fourcc = DRM_FORMAT_RGB888;
 
ctl = phys_enc->hw_ctl;
+   hw_cdm = phys_enc->hw_cdm;
+   if (hw_cdm)
+   fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc->parent, 
_enc->cached_mode);
+   fmt = dpu_get_dpu_format(fmt_fourcc);
 
DPU_DEBUG_VIDENC(phys_enc, "\n");
 
@@ -422,6 +439,8 @@ static void dpu_encoder_phys_vid_enable(struct 
dpu_encoder_phys *phys_enc)