subject:"\[PATCH 2\/2\] drm\/i915\/dp\: TPS4 PHY test pattern compliance support"

Re: [PATCH 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support

2020-07-20 Thread Almahallawy, Khaled

On Mon, 2020-07-20 at 17:11 -0700, Manasi Navare wrote:
> On Mon, Jul 20, 2020 at 04:41:26PM -0700, Khaled Almahallawy wrote:
> > Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source
> > tests.
> > 
> > Signed-off-by: Khaled Almahallawy 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 14 --
> >  drivers/gpu/drm/i915/i915_reg.h |  4 
> >  2 files changed, 16 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index d6295eb20b63..effadc096740 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -5371,7 +5371,7 @@ static void
> > intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
> > _dp->compliance.test_data.phytest;
> > struct intel_crtc *crtc = to_intel_crtc(dig_port-
> > >base.base.crtc);
> > enum pipe pipe = crtc->pipe;
> > -   u32 pattern_val;
> > +   u32 pattern_val, dp_tp_ctl;
> >  
> > switch (data->phy_pattern) {
> > case DP_PHY_TEST_PATTERN_NONE:
> > @@ -5411,7 +5411,7 @@ static void
> > intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
> >DDI_DP_COMP_CTL_ENABLE |
> >DDI_DP_COMP_CTL_CUSTOM80);
> > break;
> > -   case DP_PHY_TEST_PATTERN_CP2520:
> > +   case DP_PHY_TEST_PATTERN_CP2520_PAT1:
> > /*
> >  * FIXME: Ideally pattern should come from DPCD 0x24A.
> > As
> >  * current firmware of DPR-100 could not set it, so
> > hardcoding
> > @@ -5423,6 +5423,16 @@ static void
> > intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
> >DDI_DP_COMP_CTL_ENABLE |
> > DDI_DP_COMP_CTL_HBR2 |
> >pattern_val);
> > break;
> > +   case DP_PHY_TEST_PATTERN_CP2520_PAT3:
> > +   DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n");
> > +   intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
> > 0x0);
> > +   dp_tp_ctl = intel_de_read(dev_priv,
> > TGL_DP_TP_CTL(pipe));
> > +   dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK;
> > +   dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TS4a;
> > +   dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> > +   dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4;
> > +   intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe),
> > dp_tp_ctl);
> > +   break;
> > default:
> > WARN(1, "Invalid Phy Test Pattern\n");
> > }
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index a0d31f3bf634..a4607bd1ac26 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9982,6 +9982,10 @@ enum skl_power_gate {
> >  #define  DP_TP_CTL_MODE_SST(0 << 27)
> >  #define  DP_TP_CTL_MODE_MST(1 << 27)
> >  #define  DP_TP_CTL_FORCE_ACT   (1 << 25)
> > +#define  DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
> > +#define  DP_TP_CTL_TRAIN_PAT4_SEL_TS4a (0 << 19)
> > +#define  DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19)
> > +#define  DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19)
> 
> The bspec calls them Training Pattern 4a/b/c, why is it _TS4a. TP4b,
> TP4c?
> We shd make it uniform, all TP4a/b/c perhaps?

Apology,will fix to TP4a/b/c then

> 
> Manasi
> 
> >  #define  DP_TP_CTL_ENHANCED_FRAME_ENABLE   (1 << 18)
> >  #define  DP_TP_CTL_FDI_AUTOTRAIN   (1 << 15)
> >  #define  DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
> > -- 
> > 2.17.1
> > 
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Re: [PATCH 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support

2020-07-20 Thread Manasi Navare

On Mon, Jul 20, 2020 at 04:41:26PM -0700, Khaled Almahallawy wrote:
> Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests.
> 
> Signed-off-by: Khaled Almahallawy 
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 14 --
>  drivers/gpu/drm/i915/i915_reg.h |  4 
>  2 files changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index d6295eb20b63..effadc096740 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5371,7 +5371,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp 
> *intel_dp)
>   _dp->compliance.test_data.phytest;
>   struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
>   enum pipe pipe = crtc->pipe;
> - u32 pattern_val;
> + u32 pattern_val, dp_tp_ctl;
>  
>   switch (data->phy_pattern) {
>   case DP_PHY_TEST_PATTERN_NONE:
> @@ -5411,7 +5411,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp 
> *intel_dp)
>  DDI_DP_COMP_CTL_ENABLE |
>  DDI_DP_COMP_CTL_CUSTOM80);
>   break;
> - case DP_PHY_TEST_PATTERN_CP2520:
> + case DP_PHY_TEST_PATTERN_CP2520_PAT1:
>   /*
>* FIXME: Ideally pattern should come from DPCD 0x24A. As
>* current firmware of DPR-100 could not set it, so hardcoding
> @@ -5423,6 +5423,16 @@ static void intel_dp_phy_pattern_update(struct 
> intel_dp *intel_dp)
>  DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
>  pattern_val);
>   break;
> + case DP_PHY_TEST_PATTERN_CP2520_PAT3:
> + DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n");
> + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
> + dp_tp_ctl = intel_de_read(dev_priv, 
> TGL_DP_TP_CTL(pipe));
> + dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK;
> + dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TS4a;
> + dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4;
> + intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), 
> dp_tp_ctl);
> + break;
>   default:
>   WARN(1, "Invalid Phy Test Pattern\n");
>   }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a0d31f3bf634..a4607bd1ac26 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9982,6 +9982,10 @@ enum skl_power_gate {
>  #define  DP_TP_CTL_MODE_SST  (0 << 27)
>  #define  DP_TP_CTL_MODE_MST  (1 << 27)
>  #define  DP_TP_CTL_FORCE_ACT (1 << 25)
> +#define  DP_TP_CTL_TRAIN_PAT4_SEL_MASK   (3 << 19)
> +#define  DP_TP_CTL_TRAIN_PAT4_SEL_TS4a   (0 << 19)
> +#define  DP_TP_CTL_TRAIN_PAT4_SEL_TP4b   (1 << 19)
> +#define  DP_TP_CTL_TRAIN_PAT4_SEL_TP4c   (2 << 19)

The bspec calls them Training Pattern 4a/b/c, why is it _TS4a. TP4b, TP4c?
We shd make it uniform, all TP4a/b/c perhaps?

Manasi

>  #define  DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
>  #define  DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
>  #define  DP_TP_CTL_LINK_TRAIN_MASK   (7 << 8)
> -- 
> 2.17.1
> 
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[PATCH 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support

2020-07-20 Thread Khaled Almahallawy

Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests.

Signed-off-by: Khaled Almahallawy 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 14 --
 drivers/gpu/drm/i915/i915_reg.h |  4 
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index d6295eb20b63..effadc096740 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5371,7 +5371,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp 
*intel_dp)
_dp->compliance.test_data.phytest;
struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
enum pipe pipe = crtc->pipe;
-   u32 pattern_val;
+   u32 pattern_val, dp_tp_ctl;
 
switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_NONE:
@@ -5411,7 +5411,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp 
*intel_dp)
   DDI_DP_COMP_CTL_ENABLE |
   DDI_DP_COMP_CTL_CUSTOM80);
break;
-   case DP_PHY_TEST_PATTERN_CP2520:
+   case DP_PHY_TEST_PATTERN_CP2520_PAT1:
/*
 * FIXME: Ideally pattern should come from DPCD 0x24A. As
 * current firmware of DPR-100 could not set it, so hardcoding
@@ -5423,6 +5423,16 @@ static void intel_dp_phy_pattern_update(struct intel_dp 
*intel_dp)
   DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
   pattern_val);
break;
+   case DP_PHY_TEST_PATTERN_CP2520_PAT3:
+   DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n");
+   intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
+   dp_tp_ctl = intel_de_read(dev_priv, 
TGL_DP_TP_CTL(pipe));
+   dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK;
+   dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TS4a;
+   dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK;
+   dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4;
+   intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), 
dp_tp_ctl);
+   break;
default:
WARN(1, "Invalid Phy Test Pattern\n");
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a0d31f3bf634..a4607bd1ac26 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9982,6 +9982,10 @@ enum skl_power_gate {
 #define  DP_TP_CTL_MODE_SST(0 << 27)
 #define  DP_TP_CTL_MODE_MST(1 << 27)
 #define  DP_TP_CTL_FORCE_ACT   (1 << 25)
+#define  DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
+#define  DP_TP_CTL_TRAIN_PAT4_SEL_TS4a (0 << 19)
+#define  DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19)
+#define  DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19)
 #define  DP_TP_CTL_ENHANCED_FRAME_ENABLE   (1 << 18)
 #define  DP_TP_CTL_FDI_AUTOTRAIN   (1 << 15)
 #define  DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
-- 
2.17.1

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Re: [PATCH 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support

Re: [PATCH 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support

[PATCH 2/2] drm/i915/dp: TPS4 PHY test pattern compliance support

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