Re: [PATCH 2/2] drm/radeon/kms: add blit support for cayman
>@@ -582,11 +588,17 @@ int evergreen_blit_init(struct radeon_device *rdev) > obj_size = ALIGN(obj_size, 256); > > rdev->r600_blit.vs_offset = obj_size; >- obj_size += evergreen_vs_size * 4; >+ if (rdev->family < CHIP_CAYMAN) >+ obj_size += evergreen_vs_size * 4; >+ else >+ obj_size += cayman_vs_size * 4; > obj_size = ALIGN(obj_size, 256); > > rdev->r600_blit.ps_offset = obj_size; >- obj_size += evergreen_ps_size * 4; >+ if (rdev->family < CHIP_CAYMAN) >+ obj_size += evergreen_ps_size * 4; >+ else >+ obj_size += evergreen_ps_size * 4; > obj_size = ALIGN(obj_size, 256); > > r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, > RADEON_GEM_DOMAIN_VRAM, Hi, looks like a c&p error using evergreen_ps_size also for cayman ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 2/2] drm/radeon/kms: add blit support for cayman
>@@ -582,11 +588,17 @@ int evergreen_blit_init(struct radeon_device *rdev) > obj_size = ALIGN(obj_size, 256); > > rdev->r600_blit.vs_offset = obj_size; >- obj_size += evergreen_vs_size * 4; >+ if (rdev->family < CHIP_CAYMAN) >+ obj_size += evergreen_vs_size * 4; >+ else >+ obj_size += cayman_vs_size * 4; > obj_size = ALIGN(obj_size, 256); > > rdev->r600_blit.ps_offset = obj_size; >- obj_size += evergreen_ps_size * 4; >+ if (rdev->family < CHIP_CAYMAN) >+ obj_size += evergreen_ps_size * 4; >+ else >+ obj_size += evergreen_ps_size * 4; > obj_size = ALIGN(obj_size, 256); > > r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, > RADEON_GEM_DOMAIN_VRAM, Hi, looks like a c&p error using evergreen_ps_size also for cayman
[PATCH 2/2] drm/radeon/kms: add blit support for cayman
Allows us to use the 3D engine for memory management and allows us to use vram beyond the BAR aperture. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/cayman_blit_shaders.c | 326 - drivers/gpu/drm/radeon/cayman_blit_shaders.h |3 + drivers/gpu/drm/radeon/evergreen_blit_kms.c | 505 ++ drivers/gpu/drm/radeon/ni.c | 13 +- drivers/gpu/drm/radeon/radeon_asic.c |6 +- 5 files changed, 598 insertions(+), 255 deletions(-) diff --git a/drivers/gpu/drm/radeon/cayman_blit_shaders.c b/drivers/gpu/drm/radeon/cayman_blit_shaders.c index e148ab0..7b4eeb7 100644 --- a/drivers/gpu/drm/radeon/cayman_blit_shaders.c +++ b/drivers/gpu/drm/radeon/cayman_blit_shaders.c @@ -39,17 +39,335 @@ const u32 cayman_default_state[] = { - /* XXX fill in additional blit state */ + 0xc0066900, + 0x, + 0x0060, /* DB_RENDER_CONTROL */ + 0x, /* DB_COUNT_CONTROL */ + 0x, /* DB_DEPTH_VIEW */ + 0x002a, /* DB_RENDER_OVERRIDE */ + 0x, /* DB_RENDER_OVERRIDE2 */ + 0x, /* DB_HTILE_DATA_BASE */ 0xc0026900, - 0x0316, - 0x000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ - 0x0010, /* */ + 0x000a, + 0x, /* DB_STENCIL_CLEAR */ + 0x, /* DB_DEPTH_CLEAR */ + + 0xc0036900, + 0x000f, + 0x, /* DB_DEPTH_INFO */ + 0x, /* DB_Z_INFO */ + 0x, /* DB_STENCIL_INFO */ + + 0xc0016900, + 0x0080, + 0x, /* PA_SC_WINDOW_OFFSET */ + + 0xc00d6900, + 0x0083, + 0x, /* PA_SC_CLIPRECT_RULE */ + 0x, /* PA_SC_CLIPRECT_0_TL */ + 0x20002000, /* PA_SC_CLIPRECT_0_BR */ + 0x, + 0x20002000, + 0x, + 0x20002000, + 0x, + 0x20002000, + 0x, /* PA_SC_EDGERULE */ + 0x, /* PA_SU_HARDWARE_SCREEN_OFFSET */ + 0x000f, /* CB_TARGET_MASK */ + 0x000f, /* CB_SHADER_MASK */ + + 0xc0226900, + 0x0094, + 0x8000, /* PA_SC_VPORT_SCISSOR_0_TL */ + 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x, /* PA_SC_VPORT_ZMIN_0 */ + 0x3f80, /* PA_SC_VPORT_ZMAX_0 */ + + 0xc0016900, + 0x00d4, + 0x, /* SX_MISC */ 0xc0026900, 0x00d9, 0x, /* CP_RINGID */ 0x, /* CP_VMID */ + + 0xc0096900, + 0x0100, + 0x00ff, /* VGT_MAX_VTX_INDX */ + 0x, /* VGT_MIN_VTX_INDX */ + 0x, /* VGT_INDX_OFFSET */ + 0x, /* VGT_MULTI_PRIM_IB_RESET_INDX */ + 0x, /* SX_ALPHA_TEST_CONTROL */ + 0x, /* CB_BLEND_RED */ + 0x, /* CB_BLEND_GREEN */ + 0x, /* CB_BLEND_BLUE */ + 0x, /* CB_BLEND_ALPHA */ + + 0xc0016900, + 0x0187, + 0x0100, /* SPI_VS_OUT_ID_0 */ + + 0xc0026900, + 0x0191, + 0x0100, /* SPI_PS_INPUT_CNTL_0 */ + 0x0101, /* SPI_PS_INPUT_CNTL_1 */ + + 0xc0016900, + 0x01b1, + 0x, /* SPI_VS_OUT_CONFIG */ + + 0xc0106900, + 0x01b3, + 0x2001, /* SPI_PS_IN_CONTROL_0 */ + 0x, /* SPI_PS_IN_CONTROL_1 */ + 0x, /* SPI_INTERP_CONTROL_0 */ + 0x, /* SPI_INPUT_Z */ + 0x, /* SPI_FOG_CNTL */ + 0x0010, /* SPI_BARYC_CNTL */ + 0x, /* SPI_PS_IN_CONTROL_2 */ + 0x, /* SPI_COMPUTE_INPUT_CNTL */ + 0x, /* SPI_COMPUTE_NUM_THREAD_X */ + 0x, /* SPI_COMPUTE_NUM_THREAD_Y */ + 0x, /* SPI_COMPUTE_NUM_THREAD_Z */ + 0x, /* SPI_GPR_MGMT */ + 0x, /* SPI_LDS_MGMT */ + 0x, /* SPI_STACK_MGMT */ + 0x, /* SPI_WAVE_MGMT_1 */ + 0x, /* SPI_WAVE_MGMT_2 */ + + 0xc0016900, + 0x01e0, + 0x, /* CB_BLEND0_CONTROL */ + + 0xc00e6900, + 0x0200, + 0x, /* DB_DEPTH_CONTROL */ + 0x, /* DB_EQAA */ + 0x00cc0010, /* CB_COLOR_CONTROL */ + 0x0210, /* DB_SHADER_CONTROL */ + 0x0001, /* PA_CL_CLIP_CNTL */ + 0x0004, /* PA_SU_SC_MODE_CNTL *
[PATCH 2/2] drm/radeon/kms: add blit support for cayman
Allows us to use the 3D engine for memory management and allows us to use vram beyond the BAR aperture. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/cayman_blit_shaders.c | 326 - drivers/gpu/drm/radeon/cayman_blit_shaders.h |3 + drivers/gpu/drm/radeon/evergreen_blit_kms.c | 505 ++ drivers/gpu/drm/radeon/ni.c | 13 +- drivers/gpu/drm/radeon/radeon_asic.c |6 +- 5 files changed, 598 insertions(+), 255 deletions(-) diff --git a/drivers/gpu/drm/radeon/cayman_blit_shaders.c b/drivers/gpu/drm/radeon/cayman_blit_shaders.c index e148ab0..7b4eeb7 100644 --- a/drivers/gpu/drm/radeon/cayman_blit_shaders.c +++ b/drivers/gpu/drm/radeon/cayman_blit_shaders.c @@ -39,17 +39,335 @@ const u32 cayman_default_state[] = { - /* XXX fill in additional blit state */ + 0xc0066900, + 0x, + 0x0060, /* DB_RENDER_CONTROL */ + 0x, /* DB_COUNT_CONTROL */ + 0x, /* DB_DEPTH_VIEW */ + 0x002a, /* DB_RENDER_OVERRIDE */ + 0x, /* DB_RENDER_OVERRIDE2 */ + 0x, /* DB_HTILE_DATA_BASE */ 0xc0026900, - 0x0316, - 0x000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ - 0x0010, /* */ + 0x000a, + 0x, /* DB_STENCIL_CLEAR */ + 0x, /* DB_DEPTH_CLEAR */ + + 0xc0036900, + 0x000f, + 0x, /* DB_DEPTH_INFO */ + 0x, /* DB_Z_INFO */ + 0x, /* DB_STENCIL_INFO */ + + 0xc0016900, + 0x0080, + 0x, /* PA_SC_WINDOW_OFFSET */ + + 0xc00d6900, + 0x0083, + 0x, /* PA_SC_CLIPRECT_RULE */ + 0x, /* PA_SC_CLIPRECT_0_TL */ + 0x20002000, /* PA_SC_CLIPRECT_0_BR */ + 0x, + 0x20002000, + 0x, + 0x20002000, + 0x, + 0x20002000, + 0x, /* PA_SC_EDGERULE */ + 0x, /* PA_SU_HARDWARE_SCREEN_OFFSET */ + 0x000f, /* CB_TARGET_MASK */ + 0x000f, /* CB_SHADER_MASK */ + + 0xc0226900, + 0x0094, + 0x8000, /* PA_SC_VPORT_SCISSOR_0_TL */ + 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x8000, + 0x20002000, + 0x, /* PA_SC_VPORT_ZMIN_0 */ + 0x3f80, /* PA_SC_VPORT_ZMAX_0 */ + + 0xc0016900, + 0x00d4, + 0x, /* SX_MISC */ 0xc0026900, 0x00d9, 0x, /* CP_RINGID */ 0x, /* CP_VMID */ + + 0xc0096900, + 0x0100, + 0x00ff, /* VGT_MAX_VTX_INDX */ + 0x, /* VGT_MIN_VTX_INDX */ + 0x, /* VGT_INDX_OFFSET */ + 0x, /* VGT_MULTI_PRIM_IB_RESET_INDX */ + 0x, /* SX_ALPHA_TEST_CONTROL */ + 0x, /* CB_BLEND_RED */ + 0x, /* CB_BLEND_GREEN */ + 0x, /* CB_BLEND_BLUE */ + 0x, /* CB_BLEND_ALPHA */ + + 0xc0016900, + 0x0187, + 0x0100, /* SPI_VS_OUT_ID_0 */ + + 0xc0026900, + 0x0191, + 0x0100, /* SPI_PS_INPUT_CNTL_0 */ + 0x0101, /* SPI_PS_INPUT_CNTL_1 */ + + 0xc0016900, + 0x01b1, + 0x, /* SPI_VS_OUT_CONFIG */ + + 0xc0106900, + 0x01b3, + 0x2001, /* SPI_PS_IN_CONTROL_0 */ + 0x, /* SPI_PS_IN_CONTROL_1 */ + 0x, /* SPI_INTERP_CONTROL_0 */ + 0x, /* SPI_INPUT_Z */ + 0x, /* SPI_FOG_CNTL */ + 0x0010, /* SPI_BARYC_CNTL */ + 0x, /* SPI_PS_IN_CONTROL_2 */ + 0x, /* SPI_COMPUTE_INPUT_CNTL */ + 0x, /* SPI_COMPUTE_NUM_THREAD_X */ + 0x, /* SPI_COMPUTE_NUM_THREAD_Y */ + 0x, /* SPI_COMPUTE_NUM_THREAD_Z */ + 0x, /* SPI_GPR_MGMT */ + 0x, /* SPI_LDS_MGMT */ + 0x, /* SPI_STACK_MGMT */ + 0x, /* SPI_WAVE_MGMT_1 */ + 0x, /* SPI_WAVE_MGMT_2 */ + + 0xc0016900, + 0x01e0, + 0x, /* CB_BLEND0_CONTROL */ + + 0xc00e6900, + 0x0200, + 0x, /* DB_DEPTH_CONTROL */ + 0x, /* DB_EQAA */ + 0x00cc0010, /* CB_COLOR_CONTROL */ + 0x0210, /* DB_SHADER_CONTROL */ + 0x0001, /* PA_CL_CLIP_CNTL */ + 0x0004, /* PA_SU_SC_MODE_CNT