Re: [PATCH 2/2] phy: mtk-mipi-csi: add driver for CSI phy
On Mon, 2023-04-03 at 09:19 +0200, Julien Stephan wrote: > External email : Please do not click links or open attachments until > you have verified the sender or the content. > > > From: Phi-bang Nguyen > > This is a new driver that supports the MIPI CSI CD-PHY for mediatek > mt8365 soc > > Signed-off-by: Louis Kuo > Signed-off-by: Phi-bang Nguyen > [Julien Stephan: use regmap] > [Julien Stephan: use GENMASK] > Co-developed-by: Julien Stephan > Signed-off-by: Julien Stephan > --- > .../bindings/phy/mediatek,csi-phy.yaml| 9 +- > MAINTAINERS | 1 + > drivers/phy/mediatek/Kconfig | 8 + > drivers/phy/mediatek/Makefile | 2 + > .../phy/mediatek/phy-mtk-mipi-csi-rx-reg.h| 435 > ++ > drivers/phy/mediatek/phy-mtk-mipi-csi.c | 392 > 6 files changed, 845 insertions(+), 2 deletions(-) > create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h > create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi.c Please cc linux-media...@lists.infradead.org > > ... > diff --git a/MAINTAINERS b/MAINTAINERS > index 9308b4bb88bf..b3077eddd0bf 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -13103,6 +13103,7 @@ M: Julien Stephan > > M: Andy Hsieh > S: Supported > F: Documentation/devicetree/bindings/phy/mediatek,csi-phy.yaml > +F: drivers/phy/mediatek/phy-mtk-mipi-csi* > > MEDIATEK MMC/SD/SDIO DRIVER > M: Chaotian Jing separate a new patch for MAINTAINERS change? > diff --git a/drivers/phy/mediatek/Kconfig > b/drivers/phy/mediatek/Kconfig > index 3125ecb5d119..63fb0fa77573 100644 > --- a/drivers/phy/mediatek/Kconfig > +++ b/drivers/phy/mediatek/Kconfig > @@ -74,3 +74,11 @@ config PHY_MTK_DP > select GENERIC_PHY > help > Support DisplayPort PHY for MediaTek SoCs. > + > +config PHY_MTK_MIPI_CSI > + tristate "MediaTek CSI CD-PHY Driver" > + depends on ARCH_MEDIATEK && OF > + select GENERIC_PHY > + help > + Enable this to support the MIPI CSI CD-PHY receiver. > + The driver supports multiple CSI cdphy ports > simultaneously. > diff --git a/drivers/phy/mediatek/Makefile > b/drivers/phy/mediatek/Makefile > index fb1f8edaffa7..9a178c1c2628 100644 > --- a/drivers/phy/mediatek/Makefile > +++ b/drivers/phy/mediatek/Makefile > @@ -18,3 +18,5 @@ phy-mtk-mipi-dsi-drv-y:= > phy-mtk-mipi-dsi.o > phy-mtk-mipi-dsi-drv-y += phy-mtk-mipi-dsi-mt8173.o > phy-mtk-mipi-dsi-drv-y += phy-mtk-mipi-dsi-mt8183.o > obj-$(CONFIG_PHY_MTK_MIPI_DSI) += phy-mtk-mipi-dsi-drv.o > + > +obj-$(CONFIG_PHY_MTK_MIPI_CSI) += phy-mtk-mipi-csi.o > diff --git a/drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h > b/drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h > new file mode 100644 > index ..f360e807e3d1 > --- /dev/null > +++ b/drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h > @@ -0,0 +1,435 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > + > +#ifndef __MIPI_CDPHY_RX_REG_H__ > +#define __MIPI_CDPHY_RX_REG_H__ > + > +/* > + * CSI1 and CSI2 are identical, and similar to CSI0. All CSIx macros > are > + * applicable to the three PHYs. Where differences exist, they are > denoted by > + * macro names using CSI0 and CSI1, the latter being applicable to > CSI1 and > + * CSI2 alike. > + */ > + > +/* > + * Due to lanes supporting C-PHY mode on CSI0, register fields that > control the > + * behaviour of lanes are named differently between CSI0 and > CSI1/CSI2, even > + * when they control parameters that are agnostic to the PHY mode. > In those > + * cases, the macros below use the CSI0 field names (e.g. > + * MIPI_RX_ANA08_CSIxA_RG_CSIxA_L0P_T0A_HSRT_CODE_SHIFT). > + */ > + > > > +#define > MIPI_RX_ANA24_CSIxA_RG_CSIxA_RESERVE_SHIFT > 24 > +#define > MIPI_RX_ANA24_CSIxA_RG_CSIxA_RESERVE_MASK > (0xff << 24) Use GENMASK() > + > +/* CSI0-specific register. */ > +#define > MIPI_RX_ANA28_CSI0A > 0x0028 > +#define > MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_DIRECT_EN_SHIFT > 0 > > > +#define > MIPI_RX_ANA48_CSIxA_RGS_CSI1A_DPHY_L2_OS_CAL_CPLT_SHIFT > 5 > +#define > MIPI_RX_ANA48_CSIxA_RGS_CSI1A_DPHY_L2_OS_CAL_CPLT_MASK > BIT(5) > +/* Common fields. */ > +#define > MIPI_RX_ANA48_CSIxA_RGS_CSIxA_OS_CAL_CODE_SHIFT > 8 > +#define > MIPI_RX_ANA48_CSIxA_RGS_CSIxA_OS_CAL_CODE_MASK > GENMASK(15, 8) > + > +#define > MIPI_RX_WRAPPER80_CSIxA > 0x0080 > +#define > MIPI_RX_WRAPPER80_CSIxA_CSR_CSI_CLK_MON_SHIFT > 0 > +#define > MIPI_RX_WRAPPER80_CSIxA_CSR_CSI_CLK_MON_MASK > BIT(0) > +#define >
Re: [PATCH 2/2] phy: mtk-mipi-csi: add driver for CSI phy
On Mon, 2023-04-03 at 09:19 +0200, Julien Stephan wrote: > External email : Please do not click links or open attachments until > you have verified the sender or the content. > > > From: Phi-bang Nguyen > > This is a new driver that supports the MIPI CSI CD-PHY for mediatek > mt8365 soc > > Signed-off-by: Louis Kuo > Signed-off-by: Phi-bang Nguyen > [Julien Stephan: use regmap] > [Julien Stephan: use GENMASK] > Co-developed-by: Julien Stephan > Signed-off-by: Julien Stephan > --- > .../bindings/phy/mediatek,csi-phy.yaml| 9 +- > MAINTAINERS | 1 + > drivers/phy/mediatek/Kconfig | 8 + > drivers/phy/mediatek/Makefile | 2 + > .../phy/mediatek/phy-mtk-mipi-csi-rx-reg.h| 435 > ++ > drivers/phy/mediatek/phy-mtk-mipi-csi.c | 392 > 6 files changed, 845 insertions(+), 2 deletions(-) > create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h > create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi.c Please cc linux-media...@lists.infradead.org > > ... > diff --git a/MAINTAINERS b/MAINTAINERS > index 9308b4bb88bf..b3077eddd0bf 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -13103,6 +13103,7 @@ M: Julien Stephan > > > M: Andy Hsieh > S: Supported > F: Documentation/devicetree/bindings/phy/mediatek,csi-phy.yaml > +F: drivers/phy/mediatek/phy-mtk-mipi-csi* > > MEDIATEK MMC/SD/SDIO DRIVER > M: Chaotian Jing separate a new patch for MAINTAINERS change? > diff --git a/drivers/phy/mediatek/Kconfig > b/drivers/phy/mediatek/Kconfig > index 3125ecb5d119..63fb0fa77573 100644 > --- a/drivers/phy/mediatek/Kconfig > +++ b/drivers/phy/mediatek/Kconfig > @@ -74,3 +74,11 @@ config PHY_MTK_DP > select GENERIC_PHY > help > Support DisplayPort PHY for MediaTek SoCs. > + > +config PHY_MTK_MIPI_CSI > + tristate "MediaTek CSI CD-PHY Driver" > + depends on ARCH_MEDIATEK && OF > + select GENERIC_PHY > + help > + Enable this to support the MIPI CSI CD-PHY receiver. > + The driver supports multiple CSI cdphy ports > simultaneously. > diff --git a/drivers/phy/mediatek/Makefile > b/drivers/phy/mediatek/Makefile > index fb1f8edaffa7..9a178c1c2628 100644 > --- a/drivers/phy/mediatek/Makefile > +++ b/drivers/phy/mediatek/Makefile > @@ -18,3 +18,5 @@ phy-mtk-mipi-dsi-drv-y:= > phy-mtk-mipi-dsi.o > phy-mtk-mipi-dsi-drv-y += phy-mtk-mipi-dsi-mt8173.o > phy-mtk-mipi-dsi-drv-y += phy-mtk-mipi-dsi-mt8183.o > obj-$(CONFIG_PHY_MTK_MIPI_DSI) += phy-mtk-mipi-dsi-drv.o > + > +obj-$(CONFIG_PHY_MTK_MIPI_CSI) += phy-mtk-mipi-csi.o > diff --git a/drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h > b/drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h > new file mode 100644 > index ..f360e807e3d1 > --- /dev/null > +++ b/drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h > @@ -0,0 +1,435 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > + > +#ifndef __MIPI_CDPHY_RX_REG_H__ > +#define __MIPI_CDPHY_RX_REG_H__ > + > +/* > + * CSI1 and CSI2 are identical, and similar to CSI0. All CSIx macros > are > + * applicable to the three PHYs. Where differences exist, they are > denoted by > + * macro names using CSI0 and CSI1, the latter being applicable to > CSI1 and > + * CSI2 alike. > + */ > + > +/* > + * Due to lanes supporting C-PHY mode on CSI0, register fields that > control the > + * behaviour of lanes are named differently between CSI0 and > CSI1/CSI2, even > + * when they control parameters that are agnostic to the PHY mode. > In those > + * cases, the macros below use the CSI0 field names (e.g. > + * MIPI_RX_ANA08_CSIxA_RG_CSIxA_L0P_T0A_HSRT_CODE_SHIFT). > + */ > + > > > +#define > MIPI_RX_ANA24_CSIxA_RG_CSIxA_RESERVE_SHIFT > 24 > +#define > MIPI_RX_ANA24_CSIxA_RG_CSIxA_RESERVE_MASK > (0xff << 24) Use GENMASK() > + > +/* CSI0-specific register. */ > +#define > MIPI_RX_ANA28_CSI0A > 0x0028 > +#define > MIPI_RX_ANA28_CSI0A_RG_CSI0A_CPHY_T0_CDR_DIRECT_EN_SHIFT > 0 > > > +#define > MIPI_RX_ANA48_CSIxA_RGS_CSI1A_DPHY_L2_OS_CAL_CPLT_SHIFT > 5 > +#define > MIPI_RX_ANA48_CSIxA_RGS_CSI1A_DPHY_L2_OS_CAL_CPLT_MASK > BIT(5) > +/* Common fields. */ > +#define > MIPI_RX_ANA48_CSIxA_RGS_CSIxA_OS_CAL_CODE_SHIFT > 8 > +#define > MIPI_RX_ANA48_CSIxA_RGS_CSIxA_OS_CAL_CODE_MASK > GENMASK(15, 8) > + > +#define > MIPI_RX_WRAPPER80_CSIxA > 0x0080 > +#define > MIPI_RX_WRAPPER80_CSIxA_CSR_CSI_CLK_MON_SHIFT > 0 > +#define > MIPI_RX_WRAPPER80_CSIxA_CSR_CSI_CLK_MON_MASK > BIT(0) > +#define >
Re: [PATCH 2/2] phy: mtk-mipi-csi: add driver for CSI phy
On Mon, Apr 03, 2023 at 11:51:50AM +0200, Krzysztof Kozlowski wrote:
> On 03/04/2023 09:19, Julien Stephan wrote:
> > From: Phi-bang Nguyen
> >
> > This is a new driver that supports the MIPI CSI CD-PHY for mediatek
> > mt8365 soc
> >
> > Signed-off-by: Louis Kuo
> > Signed-off-by: Phi-bang Nguyen
> > [Julien Stephan: use regmap]
> > [Julien Stephan: use GENMASK]
> > Co-developed-by: Julien Stephan
> > Signed-off-by: Julien Stephan
> > ---
> > .../bindings/phy/mediatek,csi-phy.yaml| 9 +-
> > MAINTAINERS | 1 +
> > drivers/phy/mediatek/Kconfig | 8 +
> > drivers/phy/mediatek/Makefile | 2 +
> > .../phy/mediatek/phy-mtk-mipi-csi-rx-reg.h| 435 ++
> > drivers/phy/mediatek/phy-mtk-mipi-csi.c | 392
> > 6 files changed, 845 insertions(+), 2 deletions(-)
> > create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h
> > create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi.c
> >
> > diff --git a/Documentation/devicetree/bindings/phy/mediatek,csi-phy.yaml
> > b/Documentation/devicetree/bindings/phy/mediatek,csi-phy.yaml
> > index c026e43f35fd..ad4ba1d93a68 100644
> > --- a/Documentation/devicetree/bindings/phy/mediatek,csi-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/mediatek,csi-phy.yaml
>
> NAK, bindings are always separate patches. It also does not make any
> sense - you just added it.
>
:( I messed up my rebase -i. This need to be moved and squashed with the
previous patch. I will fix it in v2. Thank you for reporting it
> > @@ -33,9 +33,14 @@ additionalProperties: false
> >
> > examples:
> >- |
> > -phy@10011800 {
> > +soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + phy@11c1 {
> > compatible = "mediatek,mt8365-mipi-csi";
> > -reg = <0 0x10011800 0 0x60>;
> > +reg = <0 0x11c1 0 0x4000>;
> > #phy-cells = <1>;
> > + };
> > };
>
>
>
> k_mipi_dphy_of_match[] = {
> > + {.compatible = "mediatek,mt8365-mipi-csi"},
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_mipi_dphy_of_match);
> > +
> > +static struct platform_driver mipi_dphy_pdrv = {
> > + .probe = mtk_mipi_dphy_probe,
> > + .remove = mtk_mipi_dphy_remove,
> > + .driver = {
> > + .name = "mtk-mipi-csi",
> > + .of_match_table = of_match_ptr(mtk_mipi_dphy_of_match),
>
> Drop of_match_ptr(). You should see W=1 warnings when compile testing.
>
I do not not see any warnings when trying to compile with W=1. Am I
missing something? I will drop it in v2 anyway
Best
Julien
>
> Best regards,
> Krzysztof
>
Re: [PATCH 2/2] phy: mtk-mipi-csi: add driver for CSI phy
Hi, Julien: Julien Stephan 於 2023年4月3日 週一 下午3:20寫道： > > From: Phi-bang Nguyen > > This is a new driver that supports the MIPI CSI CD-PHY for mediatek > mt8365 soc > > Signed-off-by: Louis Kuo > Signed-off-by: Phi-bang Nguyen > [Julien Stephan: use regmap] > [Julien Stephan: use GENMASK] > Co-developed-by: Julien Stephan > Signed-off-by: Julien Stephan > --- > .../bindings/phy/mediatek,csi-phy.yaml| 9 +- > MAINTAINERS | 1 + > drivers/phy/mediatek/Kconfig | 8 + > drivers/phy/mediatek/Makefile | 2 + > .../phy/mediatek/phy-mtk-mipi-csi-rx-reg.h| 435 ++ > drivers/phy/mediatek/phy-mtk-mipi-csi.c | 392 > 6 files changed, 845 insertions(+), 2 deletions(-) > create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h > create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi.c > [snip] > + > +#define REGMAP_BIT(map, reg, field, val) \ > + regmap_update_bits((map), reg, reg##_##field##_MASK, \ > + (val) << reg##_##field##_SHIFT) > + Use FIELD_PREP() macro so you can drop the definition of SHIFT symbol. Regards, Chun-Kuang.
Re: [PATCH 2/2] phy: mtk-mipi-csi: add driver for CSI phy
Hi, Julien: Julien Stephan 於 2023年4月3日 週一 下午3:20寫道： > > From: Phi-bang Nguyen > > This is a new driver that supports the MIPI CSI CD-PHY for mediatek > mt8365 soc > > Signed-off-by: Louis Kuo > Signed-off-by: Phi-bang Nguyen > [Julien Stephan: use regmap] > [Julien Stephan: use GENMASK] > Co-developed-by: Julien Stephan > Signed-off-by: Julien Stephan > --- > .../bindings/phy/mediatek,csi-phy.yaml| 9 +- > MAINTAINERS | 1 + > drivers/phy/mediatek/Kconfig | 8 + > drivers/phy/mediatek/Makefile | 2 + > .../phy/mediatek/phy-mtk-mipi-csi-rx-reg.h| 435 ++ > drivers/phy/mediatek/phy-mtk-mipi-csi.c | 392 > 6 files changed, 845 insertions(+), 2 deletions(-) > create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h > create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi.c > [snip] > + > +#define MIPI_RX_ANA04_CSIxA > 0x0004 Useless, so drop this. > +#define MIPI_RX_ANA04_CSIxA_RG_CSIxA_BG_LPRX_VTH_SEL_SHIFT > 0 > +#define MIPI_RX_ANA04_CSIxA_RG_CSIxA_BG_LPRX_VTH_SEL_MASK > GENMASK(2, 0) > +#define MIPI_RX_ANA04_CSIxA_RG_CSIxA_BG_LPRX_VTL_SEL_SHIFT > 4 > +#define MIPI_RX_ANA04_CSIxA_RG_CSIxA_BG_LPRX_VTL_SEL_MASK > GENMASK(6, 4) > +#define MIPI_RX_ANA04_CSIxA_RG_CSIxA_BG_HSDET_VTH_SEL_SHIFT > 8 > +#define MIPI_RX_ANA04_CSIxA_RG_CSIxA_BG_HSDET_VTH_SEL_MASK > GENMASK(10, 8) > +#define MIPI_RX_ANA04_CSIxA_RG_CSIxA_BG_HSDET_VTL_SEL_SHIFT > 12 > +#define MIPI_RX_ANA04_CSIxA_RG_CSIxA_BG_HSDET_VTL_SEL_MASK > GENMASK(14, 12) > +#define MIPI_RX_ANA04_CSIxA_RG_CSIxA_BG_VREF_SEL_SHIFT > 16 > +#define MIPI_RX_ANA04_CSIxA_RG_CSIxA_BG_VREF_SEL_MASK > GENMASK(19, 16) > +#define MIPI_RX_ANA04_CSIxA_RG_CSIxA_BG_MON_VREF_SEL_SHIFT > 24 > +#define MIPI_RX_ANA04_CSIxA_RG_CSIxA_BG_MON_VREF_SEL_MASK > GENMASK(27, 24) > +#define MIPI_RX_ANA04_CSIxA_RG_CSIxA_FORCE_HSRT_EN_SHIFT > 28 > +#define MIPI_RX_ANA04_CSIxA_RG_CSIxA_FORCE_HSRT_EN_MASK > BIT(28) > + > +#define MIPI_RX_ANA08_CSIxA > 0x0008 Ditto. > +#define MIPI_RX_ANA08_CSIxA_RG_CSIxA_L0P_T0A_HSRT_CODE_SHIFT > 0 > +#define MIPI_RX_ANA08_CSIxA_RG_CSIxA_L0P_T0A_HSRT_CODE_MASK > GENMASK(4, 0) > +#define MIPI_RX_ANA08_CSIxA_RG_CSIxA_L0N_T0B_HSRT_CODE_SHIFT > 8 > +#define MIPI_RX_ANA08_CSIxA_RG_CSIxA_L0N_T0B_HSRT_CODE_MASK > GENMASK(12, 8) > +#define MIPI_RX_ANA08_CSIxA_RG_CSIxA_L1P_T0C_HSRT_CODE_SHIFT > 16 > +#define MIPI_RX_ANA08_CSIxA_RG_CSIxA_L1P_T0C_HSRT_CODE_MASK > GENMASK(20, 16) > +#define MIPI_RX_ANA08_CSIxA_RG_CSIxA_L1N_T1A_HSRT_CODE_SHIFT > 24 > +#define MIPI_RX_ANA08_CSIxA_RG_CSIxA_L1N_T1A_HSRT_CODE_MASK > GENMASK(28, 24) > + > +#define MIPI_RX_ANA0C_CSIxA > 0x000c Ditto. > +#define MIPI_RX_ANA0C_CSIxA_RG_CSIxA_L2P_T1B_HSRT_CODE_SHIFT > 0 > +#define MIPI_RX_ANA0C_CSIxA_RG_CSIxA_L2P_T1B_HSRT_CODE_MASK > GENMASK(4, 0) > +#define MIPI_RX_ANA0C_CSIxA_RG_CSIxA_L2N_T1C_HSRT_CODE_SHIFT > 8 > +#define MIPI_RX_ANA0C_CSIxA_RG_CSIxA_L2N_T1C_HSRT_CODE_MASK > GENMASK(12, 8) > + > +#define MIPI_RX_ANA10_CSIxA > 0x0010 Ditto. > +#define MIPI_RX_ANA10_CSIxA_RG_CSIxA_DPHY_L0_DELAYCAL_EN_SHIFT > 0 > +#define MIPI_RX_ANA10_CSIxA_RG_CSIxA_DPHY_L0_DELAYCAL_EN_MASK > BIT(0) > +#define MIPI_RX_ANA10_CSIxA_RG_CSIxA_DPHY_L0_DELAYCAL_RSTB_SHIFT > 1 > +#define MIPI_RX_ANA10_CSIxA_RG_CSIxA_DPHY_L0_DELAYCAL_RSTB_MASK > BIT(1) > +#define MIPI_RX_ANA10_CSIxA_RG_CSIxA_DPHY_L0_VREF_SEL_SHIFT > 2 > +#define MIPI_RX_ANA10_CSIxA_RG_CSIxA_DPHY_L0_VREF_SEL_MASK > GENMASK(7, 2) > +#define MIPI_RX_ANA10_CSIxA_RG_CSIxA_DPHY_L1_DELAYCAL_EN_SHIFT > 8 > +#define MIPI_RX_ANA10_CSIxA_RG_CSIxA_DPHY_L1_DELAYCAL_EN_MASK > BIT(8) > +#define MIPI_RX_ANA10_CSIxA_RG_CSIxA_DPHY_L1_DELAYCAL_RSTB_SHIFT > 9 > +#define MIPI_RX_ANA10_CSIxA_RG_CSIxA_DPHY_L1_DELAYCAL_RSTB_MASK > BIT(9) > +#define MIPI_RX_ANA10_CSIxA_RG_CSIxA_DPHY_L1_VREF_SEL_SHIFT > 10 > +#define MIPI_RX_ANA10_CSIxA_RG_CSIxA_DPHY_L1_VREF_SEL_MASK > GENMASK(15, 10) > +#define MIPI_RX_ANA10_CSIxA_RG_CSIxA_DPHY_L2_DELAYCAL_EN_SHIFT
Re: [PATCH 2/2] phy: mtk-mipi-csi: add driver for CSI phy
Hi, Julien:
Julien Stephan 於 2023年4月3日 週一 下午3:20寫道：
>
> From: Phi-bang Nguyen
>
> This is a new driver that supports the MIPI CSI CD-PHY for mediatek
> mt8365 soc
>
> Signed-off-by: Louis Kuo
> Signed-off-by: Phi-bang Nguyen
> [Julien Stephan: use regmap]
> [Julien Stephan: use GENMASK]
> Co-developed-by: Julien Stephan
> Signed-off-by: Julien Stephan
> ---
> .../bindings/phy/mediatek,csi-phy.yaml| 9 +-
> MAINTAINERS | 1 +
> drivers/phy/mediatek/Kconfig | 8 +
> drivers/phy/mediatek/Makefile | 2 +
> .../phy/mediatek/phy-mtk-mipi-csi-rx-reg.h| 435 ++
> drivers/phy/mediatek/phy-mtk-mipi-csi.c | 392
> 6 files changed, 845 insertions(+), 2 deletions(-)
> create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h
> create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi.c
>
[snip]
> +static int mtk_mipi_phy_power_on(struct phy *phy)
> +{
> + struct mtk_mipi_dphy_port *port = phy_get_drvdata(phy);
> + struct mtk_mipi_dphy *priv = port->dev;
> + struct regmap *regmap_base = port->regmap_base;
> + struct regmap *regmap_4d1c = port->regmap_4d1c;
> + int ret = 0;
> +
> + mutex_lock(>lock);
> +
> + switch (port->id) {
> + case MTK_MIPI_PHY_PORT_0:
> + if (priv->ports[MTK_MIPI_PHY_PORT_0A].active ||
> + priv->ports[MTK_MIPI_PHY_PORT_0B].active)
> + ret = -EBUSY;
> + break;
> +
> + case MTK_MIPI_PHY_PORT_0A:
> + case MTK_MIPI_PHY_PORT_0B:
> + if (priv->ports[MTK_MIPI_PHY_PORT_0].active)
> + ret = -EBUSY;
> + break;
> + }
> +
> + if (!ret)
> + port->active = true;
> +
> + mutex_unlock(>lock);
> +
> + if (ret < 0)
> + return ret;
> +
> + /* Set analog phy mode to DPHY */
> + if (port->is_cdphy)
> + REGMAP_BIT(regmap_base, MIPI_RX_ANA00_CSIxA,
> + RG_CSI0A_CPHY_EN, 0);
> +
> + if (port->is_4d1c) {
> + REGMAP_BIT(regmap_base, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L0_CKMODE_EN, 0);
> + REGMAP_BIT(regmap_base, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L0_CKSEL, 1);
> + REGMAP_BIT(regmap_base, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L1_CKMODE_EN, 0);
> + REGMAP_BIT(regmap_base, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L1_CKSEL, 1);
> + REGMAP_BIT(regmap_base, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L2_CKMODE_EN, 1);
> + REGMAP_BIT(regmap_base, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L2_CKSEL, 1);
> + } else {
> + REGMAP_BIT(regmap_base, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L0_CKMODE_EN, 0);
> + REGMAP_BIT(regmap_base, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L0_CKSEL, 0);
> + REGMAP_BIT(regmap_base, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L1_CKMODE_EN, 1);
> + REGMAP_BIT(regmap_base, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L1_CKSEL, 0);
> + REGMAP_BIT(regmap_base, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L2_CKMODE_EN, 0);
> + REGMAP_BIT(regmap_base, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L2_CKSEL, 0);
> + }
> +
> + if (port->is_4d1c) {
> + if (port->is_cdphy)
> + REGMAP_BIT(regmap_4d1c, MIPI_RX_ANA00_CSIxA,
> + RG_CSI0A_CPHY_EN, 0);
> +
> + REGMAP_BIT(regmap_4d1c, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L0_CKMODE_EN, 0);
> + REGMAP_BIT(regmap_4d1c, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L0_CKSEL, 1);
> + REGMAP_BIT(regmap_4d1c, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L1_CKMODE_EN, 0);
> + REGMAP_BIT(regmap_4d1c, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L1_CKSEL, 1);
> + REGMAP_BIT(regmap_4d1c, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L2_CKMODE_EN, 0);
> + REGMAP_BIT(regmap_4d1c, MIPI_RX_ANA00_CSIxA,
> + RG_CSIxA_DPHY_L2_CKSEL, 1);
> + }
> +
> + /* Byte clock invert */
> + REGMAP_BIT(regmap_base, MIPI_RX_ANAA8_CSIxA,
> + RG_CSIxA_CDPHY_L0_T0_BYTECK_INVERT, 1);
> + REGMAP_BIT(regmap_base, MIPI_RX_ANAA8_CSIxA,
> + RG_CSIxA_DPHY_L1_BYTECK_INVERT, 1);
> + REGMAP_BIT(regmap_base, MIPI_RX_ANAA8_CSIxA,
> + RG_CSIxA_CDPHY_L2_T1_BYTECK_INVERT, 1);
> +
> + if
Re: [PATCH 2/2] phy: mtk-mipi-csi: add driver for CSI phy
On 03/04/2023 09:19, Julien Stephan wrote:
> From: Phi-bang Nguyen
>
> This is a new driver that supports the MIPI CSI CD-PHY for mediatek
> mt8365 soc
>
> Signed-off-by: Louis Kuo
> Signed-off-by: Phi-bang Nguyen
> [Julien Stephan: use regmap]
> [Julien Stephan: use GENMASK]
> Co-developed-by: Julien Stephan
> Signed-off-by: Julien Stephan
> ---
> .../bindings/phy/mediatek,csi-phy.yaml| 9 +-
> MAINTAINERS | 1 +
> drivers/phy/mediatek/Kconfig | 8 +
> drivers/phy/mediatek/Makefile | 2 +
> .../phy/mediatek/phy-mtk-mipi-csi-rx-reg.h| 435 ++
> drivers/phy/mediatek/phy-mtk-mipi-csi.c | 392
> 6 files changed, 845 insertions(+), 2 deletions(-)
> create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h
> create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi.c
>
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,csi-phy.yaml
> b/Documentation/devicetree/bindings/phy/mediatek,csi-phy.yaml
> index c026e43f35fd..ad4ba1d93a68 100644
> --- a/Documentation/devicetree/bindings/phy/mediatek,csi-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/mediatek,csi-phy.yaml
NAK, bindings are always separate patches. It also does not make any
sense - you just added it.
> @@ -33,9 +33,14 @@ additionalProperties: false
>
> examples:
>- |
> -phy@10011800 {
> +soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + phy@11c1 {
> compatible = "mediatek,mt8365-mipi-csi";
> -reg = <0 0x10011800 0 0x60>;
> +reg = <0 0x11c1 0 0x4000>;
> #phy-cells = <1>;
> + };
> };
k_mipi_dphy_of_match[] = {
> + {.compatible = "mediatek,mt8365-mipi-csi"},
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_mipi_dphy_of_match);
> +
> +static struct platform_driver mipi_dphy_pdrv = {
> + .probe = mtk_mipi_dphy_probe,
> + .remove = mtk_mipi_dphy_remove,
> + .driver = {
> + .name = "mtk-mipi-csi",
> + .of_match_table = of_match_ptr(mtk_mipi_dphy_of_match),
Drop of_match_ptr(). You should see W=1 warnings when compile testing.
Best regards,
Krzysztof
[PATCH 2/2] phy: mtk-mipi-csi: add driver for CSI phy
From: Phi-bang Nguyen
This is a new driver that supports the MIPI CSI CD-PHY for mediatek
mt8365 soc
Signed-off-by: Louis Kuo
Signed-off-by: Phi-bang Nguyen
[Julien Stephan: use regmap]
[Julien Stephan: use GENMASK]
Co-developed-by: Julien Stephan
Signed-off-by: Julien Stephan
---
.../bindings/phy/mediatek,csi-phy.yaml| 9 +-
MAINTAINERS | 1 +
drivers/phy/mediatek/Kconfig | 8 +
drivers/phy/mediatek/Makefile | 2 +
.../phy/mediatek/phy-mtk-mipi-csi-rx-reg.h| 435 ++
drivers/phy/mediatek/phy-mtk-mipi-csi.c | 392
6 files changed, 845 insertions(+), 2 deletions(-)
create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h
create mode 100644 drivers/phy/mediatek/phy-mtk-mipi-csi.c
diff --git a/Documentation/devicetree/bindings/phy/mediatek,csi-phy.yaml
b/Documentation/devicetree/bindings/phy/mediatek,csi-phy.yaml
index c026e43f35fd..ad4ba1d93a68 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,csi-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,csi-phy.yaml
@@ -33,9 +33,14 @@ additionalProperties: false
examples:
- |
-phy@10011800 {
+soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ phy@11c1 {
compatible = "mediatek,mt8365-mipi-csi";
-reg = <0 0x10011800 0 0x60>;
+reg = <0 0x11c1 0 0x4000>;
#phy-cells = <1>;
+ };
};
...
diff --git a/MAINTAINERS b/MAINTAINERS
index 9308b4bb88bf..b3077eddd0bf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13103,6 +13103,7 @@ M: Julien Stephan
M: Andy Hsieh
S: Supported
F: Documentation/devicetree/bindings/phy/mediatek,csi-phy.yaml
+F: drivers/phy/mediatek/phy-mtk-mipi-csi*
MEDIATEK MMC/SD/SDIO DRIVER
M: Chaotian Jing
diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
index 3125ecb5d119..63fb0fa77573 100644
--- a/drivers/phy/mediatek/Kconfig
+++ b/drivers/phy/mediatek/Kconfig
@@ -74,3 +74,11 @@ config PHY_MTK_DP
select GENERIC_PHY
help
Support DisplayPort PHY for MediaTek SoCs.
+
+config PHY_MTK_MIPI_CSI
+ tristate "MediaTek CSI CD-PHY Driver"
+ depends on ARCH_MEDIATEK && OF
+ select GENERIC_PHY
+ help
+ Enable this to support the MIPI CSI CD-PHY receiver.
+ The driver supports multiple CSI cdphy ports simultaneously.
diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
index fb1f8edaffa7..9a178c1c2628 100644
--- a/drivers/phy/mediatek/Makefile
+++ b/drivers/phy/mediatek/Makefile
@@ -18,3 +18,5 @@ phy-mtk-mipi-dsi-drv-y:=
phy-mtk-mipi-dsi.o
phy-mtk-mipi-dsi-drv-y += phy-mtk-mipi-dsi-mt8173.o
phy-mtk-mipi-dsi-drv-y += phy-mtk-mipi-dsi-mt8183.o
obj-$(CONFIG_PHY_MTK_MIPI_DSI) += phy-mtk-mipi-dsi-drv.o
+
+obj-$(CONFIG_PHY_MTK_MIPI_CSI) += phy-mtk-mipi-csi.o
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h
b/drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h
new file mode 100644
index ..f360e807e3d1
--- /dev/null
+++ b/drivers/phy/mediatek/phy-mtk-mipi-csi-rx-reg.h
@@ -0,0 +1,435 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __MIPI_CDPHY_RX_REG_H__
+#define __MIPI_CDPHY_RX_REG_H__
+
+/*
+ * CSI1 and CSI2 are identical, and similar to CSI0. All CSIx macros are
+ * applicable to the three PHYs. Where differences exist, they are denoted by
+ * macro names using CSI0 and CSI1, the latter being applicable to CSI1 and
+ * CSI2 alike.
+ */
+
+/*
+ * Due to lanes supporting C-PHY mode on CSI0, register fields that control the
+ * behaviour of lanes are named differently between CSI0 and CSI1/CSI2, even
+ * when they control parameters that are agnostic to the PHY mode. In those
+ * cases, the macros below use the CSI0 field names (e.g.
+ * MIPI_RX_ANA08_CSIxA_RG_CSIxA_L0P_T0A_HSRT_CODE_SHIFT).
+ */
+
+#define MIPI_RX_ANA00_CSIxA
0x
+#define MIPI_RX_ANA00_CSIxA_RG_CSI0A_CPHY_EN_SHIFT 0
+#define MIPI_RX_ANA00_CSIxA_RG_CSI0A_CPHY_EN_MASK
BIT(0)
+#define MIPI_RX_ANA00_CSIxA_RG_CSIxA_EQ_PROTECT_EN_SHIFT
1
+#define MIPI_RX_ANA00_CSIxA_RG_CSIxA_EQ_PROTECT_EN_MASK
BIT(1)
+#define MIPI_RX_ANA00_CSIxA_RG_CSIxA_BG_LPF_EN_SHIFT
2
+#define MIPI_RX_ANA00_CSIxA_RG_CSIxA_BG_LPF_EN_MASK
BIT(2)
+#define MIPI_RX_ANA00_CSIxA_RG_CSIxA_BG_CORE_EN_SHIFT
3
+#define MIPI_RX_ANA00_CSIxA_RG_CSIxA_BG_CORE_EN_MASK
BIT(3)
+#define MIPI_RX_ANA00_CSIxA_RG_CSIxA_DPHY_L0_CKMODE_EN_SHIFT
5
+#define MIPI_RX_ANA00_CSIxA_RG_CSIxA_DPHY_L0_CKMODE_EN_MASK
BIT(5)
+#define MIPI_RX_ANA00_CSIxA_RG_CSIxA_DPHY_L0_CKSEL_SHIFT
