Re: [PATCH 2/3] drm/exynos: scaler: Add support for tiled formats
Hi Inki,
On 2018-09-21 05:20, Inki Dae wrote:
> There are several warnings,
> WARNING: line over 80 characters
> #276: FILE: drivers/gpu/drm/exynos/exynos_drm_scaler.c:182:
> + struct drm_exynos_ipp_task_rect *src_pos, const struct scaler_format
> *fmt)
>
> WARNING: line over 80 characters
> #297: FILE: drivers/gpu/drm/exynos/exynos_drm_scaler.c:363:
> + const struct scaler_format *src_fmt =
> scaler_get_format(task->src.buf.fourcc);
>
> WARNING: line over 80 characters
> #301: FILE: drivers/gpu/drm/exynos/exynos_drm_scaler.c:366:
> + const struct scaler_format *dst_fmt =
> scaler_get_format(task->dst.buf.fourcc);
>
> total: 0 errors, 3 warnings, 192 lines checked
>
>
> And comment below.
>
>
> On 2018년 08월 10일 22:29, Marek Szyprowski wrote:
>> From: Andrzej Pietrasiewicz
>>
>> Add support for 16x16 tiled formats: NV12/NV21, YUYV and YUV420.
>>
>> Signed-off-by: Andrzej Pietrasiewicz
>> Signed-off-by: Marek Szyprowski
>> ---
>> drivers/gpu/drm/exynos/exynos_drm_scaler.c | 133 -
>> 1 file changed, 75 insertions(+), 58 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_scaler.c
>> b/drivers/gpu/drm/exynos/exynos_drm_scaler.c
>> index 0ddb6eec7b11..8e761ef63eac 100644
>> --- a/drivers/gpu/drm/exynos/exynos_drm_scaler.c
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_scaler.c
>> @@ -49,56 +49,46 @@ struct scaler_context {
>> const struct scaler_data*scaler_data;
>> };
>>
>> -static u32 scaler_get_format(u32 drm_fmt)
>> +struct scaler_format {
>> +u32 drm_fmt;
>> +u32 internal_fmt;
>> +u32 chroma_tile_w;
>> +u32 chroma_tile_h;
>> +};
>> +
>> +static const struct scaler_format scaler_formats[] = {
>> +{ DRM_FORMAT_NV12, SCALER_YUV420_2P_UV, 8, 8 },
>> +{ DRM_FORMAT_NV21, SCALER_YUV420_2P_VU, 8, 8 },
>> +{ DRM_FORMAT_YUV420, SCALER_YUV420_3P, 8, 8 },
>> +{ DRM_FORMAT_YUYV, SCALER_YUV422_1P_YUYV, 16, 16 },
>> +{ DRM_FORMAT_UYVY, SCALER_YUV422_1P_UYVY, 16, 16 },
>> +{ DRM_FORMAT_YVYU, SCALER_YUV422_1P_YVYU, 16, 16 },
>> +{ DRM_FORMAT_NV16, SCALER_YUV422_2P_UV, 8, 16 },
>> +{ DRM_FORMAT_NV61, SCALER_YUV422_2P_VU, 8, 16 },
>> +{ DRM_FORMAT_YUV422, SCALER_YUV422_3P, 8, 16 },
>> +{ DRM_FORMAT_NV24, SCALER_YUV444_2P_UV, 16, 16 },
>> +{ DRM_FORMAT_NV42, SCALER_YUV444_2P_VU, 16, 16 },
>> +{ DRM_FORMAT_YUV444, SCALER_YUV444_3P, 16, 16 },
>> +{ DRM_FORMAT_RGB565, SCALER_RGB_565, 0, 0 },
>> +{ DRM_FORMAT_XRGB1555, SCALER_ARGB1555, 0, 0 },
>> +{ DRM_FORMAT_ARGB1555, SCALER_ARGB1555, 0, 0 },
>> +{ DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
>> +{ DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
>> +{ DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
>> +{ DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
>> +{ DRM_FORMAT_RGBX, SCALER_RGBA, 0, 0 },
>> +{ DRM_FORMAT_RGBA, SCALER_RGBA, 0, 0 },
>> +};
>> +
>> +static const struct scaler_format *scaler_get_format(u32 drm_fmt)
>> {
>> -switch (drm_fmt) {
>> -case DRM_FORMAT_NV12:
>> -return SCALER_YUV420_2P_UV;
>> -case DRM_FORMAT_NV21:
>> -return SCALER_YUV420_2P_VU;
>> -case DRM_FORMAT_YUV420:
>> -return SCALER_YUV420_3P;
>> -case DRM_FORMAT_YUYV:
>> -return SCALER_YUV422_1P_YUYV;
>> -case DRM_FORMAT_UYVY:
>> -return SCALER_YUV422_1P_UYVY;
>> -case DRM_FORMAT_YVYU:
>> -return SCALER_YUV422_1P_YVYU;
>> -case DRM_FORMAT_NV16:
>> -return SCALER_YUV422_2P_UV;
>> -case DRM_FORMAT_NV61:
>> -return SCALER_YUV422_2P_VU;
>> -case DRM_FORMAT_YUV422:
>> -return SCALER_YUV422_3P;
>> -case DRM_FORMAT_NV24:
>> -return SCALER_YUV444_2P_UV;
>> -case DRM_FORMAT_NV42:
>> -return SCALER_YUV444_2P_VU;
>> -case DRM_FORMAT_YUV444:
>> -return SCALER_YUV444_3P;
>> -case DRM_FORMAT_RGB565:
>> -return SCALER_RGB_565;
>> -case DRM_FORMAT_XRGB1555:
>> -return SCALER_ARGB1555;
>> -case DRM_FORMAT_ARGB1555:
>> -return SCALER_ARGB1555;
>> -case DRM_FORMAT_XRGB:
>> -return SCALER_ARGB;
>> -case DRM_FORMAT_ARGB:
>> -return SCALER_ARGB;
>> -case DRM_FORMAT_XRGB:
>> -return SCALER_ARGB;
>> -case DRM_FORMAT_ARGB:
>> -return SCALER_ARGB;
>> -case DRM_FORMAT_RGBX:
>> -return SCALER_RGBA;
>> -case DRM_FORMAT_RGBA:
>> -return SCALER_RGBA;
>> -default:
>> -break;
>> -}
>> +int i;
>>
>> -return 0;
>> +for (i = 0; i < ARRAY_SIZE(scaler_formats); i++)
>> +if (scaler_formats[i].drm_fmt == drm_fmt)
>> +return _formats[i];
>> +
>> +return NULL;
>> }
>>
>> static inline int scaler_reset(struct scaler_context *scaler)
>> @@ -152,11 +142,11 @@ static inline void
Re: [PATCH 2/3] drm/exynos: scaler: Add support for tiled formats
Hi,
There are several warnings,
WARNING: line over 80 characters
#276: FILE: drivers/gpu/drm/exynos/exynos_drm_scaler.c:182:
+ struct drm_exynos_ipp_task_rect *src_pos, const struct scaler_format
*fmt)
WARNING: line over 80 characters
#297: FILE: drivers/gpu/drm/exynos/exynos_drm_scaler.c:363:
+ const struct scaler_format *src_fmt =
scaler_get_format(task->src.buf.fourcc);
WARNING: line over 80 characters
#301: FILE: drivers/gpu/drm/exynos/exynos_drm_scaler.c:366:
+ const struct scaler_format *dst_fmt =
scaler_get_format(task->dst.buf.fourcc);
total: 0 errors, 3 warnings, 192 lines checked
And comment below.
On 2018년 08월 10일 22:29, Marek Szyprowski wrote:
> From: Andrzej Pietrasiewicz
>
> Add support for 16x16 tiled formats: NV12/NV21, YUYV and YUV420.
>
> Signed-off-by: Andrzej Pietrasiewicz
> Signed-off-by: Marek Szyprowski
> ---
> drivers/gpu/drm/exynos/exynos_drm_scaler.c | 133 -
> 1 file changed, 75 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_scaler.c
> b/drivers/gpu/drm/exynos/exynos_drm_scaler.c
> index 0ddb6eec7b11..8e761ef63eac 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_scaler.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_scaler.c
> @@ -49,56 +49,46 @@ struct scaler_context {
> const struct scaler_data*scaler_data;
> };
>
> -static u32 scaler_get_format(u32 drm_fmt)
> +struct scaler_format {
> + u32 drm_fmt;
> + u32 internal_fmt;
> + u32 chroma_tile_w;
> + u32 chroma_tile_h;
> +};
> +
> +static const struct scaler_format scaler_formats[] = {
> + { DRM_FORMAT_NV12, SCALER_YUV420_2P_UV, 8, 8 },
> + { DRM_FORMAT_NV21, SCALER_YUV420_2P_VU, 8, 8 },
> + { DRM_FORMAT_YUV420, SCALER_YUV420_3P, 8, 8 },
> + { DRM_FORMAT_YUYV, SCALER_YUV422_1P_YUYV, 16, 16 },
> + { DRM_FORMAT_UYVY, SCALER_YUV422_1P_UYVY, 16, 16 },
> + { DRM_FORMAT_YVYU, SCALER_YUV422_1P_YVYU, 16, 16 },
> + { DRM_FORMAT_NV16, SCALER_YUV422_2P_UV, 8, 16 },
> + { DRM_FORMAT_NV61, SCALER_YUV422_2P_VU, 8, 16 },
> + { DRM_FORMAT_YUV422, SCALER_YUV422_3P, 8, 16 },
> + { DRM_FORMAT_NV24, SCALER_YUV444_2P_UV, 16, 16 },
> + { DRM_FORMAT_NV42, SCALER_YUV444_2P_VU, 16, 16 },
> + { DRM_FORMAT_YUV444, SCALER_YUV444_3P, 16, 16 },
> + { DRM_FORMAT_RGB565, SCALER_RGB_565, 0, 0 },
> + { DRM_FORMAT_XRGB1555, SCALER_ARGB1555, 0, 0 },
> + { DRM_FORMAT_ARGB1555, SCALER_ARGB1555, 0, 0 },
> + { DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
> + { DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
> + { DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
> + { DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
> + { DRM_FORMAT_RGBX, SCALER_RGBA, 0, 0 },
> + { DRM_FORMAT_RGBA, SCALER_RGBA, 0, 0 },
> +};
> +
> +static const struct scaler_format *scaler_get_format(u32 drm_fmt)
> {
> - switch (drm_fmt) {
> - case DRM_FORMAT_NV12:
> - return SCALER_YUV420_2P_UV;
> - case DRM_FORMAT_NV21:
> - return SCALER_YUV420_2P_VU;
> - case DRM_FORMAT_YUV420:
> - return SCALER_YUV420_3P;
> - case DRM_FORMAT_YUYV:
> - return SCALER_YUV422_1P_YUYV;
> - case DRM_FORMAT_UYVY:
> - return SCALER_YUV422_1P_UYVY;
> - case DRM_FORMAT_YVYU:
> - return SCALER_YUV422_1P_YVYU;
> - case DRM_FORMAT_NV16:
> - return SCALER_YUV422_2P_UV;
> - case DRM_FORMAT_NV61:
> - return SCALER_YUV422_2P_VU;
> - case DRM_FORMAT_YUV422:
> - return SCALER_YUV422_3P;
> - case DRM_FORMAT_NV24:
> - return SCALER_YUV444_2P_UV;
> - case DRM_FORMAT_NV42:
> - return SCALER_YUV444_2P_VU;
> - case DRM_FORMAT_YUV444:
> - return SCALER_YUV444_3P;
> - case DRM_FORMAT_RGB565:
> - return SCALER_RGB_565;
> - case DRM_FORMAT_XRGB1555:
> - return SCALER_ARGB1555;
> - case DRM_FORMAT_ARGB1555:
> - return SCALER_ARGB1555;
> - case DRM_FORMAT_XRGB:
> - return SCALER_ARGB;
> - case DRM_FORMAT_ARGB:
> - return SCALER_ARGB;
> - case DRM_FORMAT_XRGB:
> - return SCALER_ARGB;
> - case DRM_FORMAT_ARGB:
> - return SCALER_ARGB;
> - case DRM_FORMAT_RGBX:
> - return SCALER_RGBA;
> - case DRM_FORMAT_RGBA:
> - return SCALER_RGBA;
> - default:
> - break;
> - }
> + int i;
>
> - return 0;
> + for (i = 0; i < ARRAY_SIZE(scaler_formats); i++)
> + if (scaler_formats[i].drm_fmt == drm_fmt)
> + return _formats[i];
> +
> + return NULL;
> }
>
> static inline int scaler_reset(struct scaler_context *scaler)
> @@ -152,11 +142,11 @@ static inline void scaler_enable_int(struct
> scaler_context *scaler)
> }
>
> static inline void scaler_set_src_fmt(struct scaler_context
Re: [PATCH 2/3] drm/exynos: scaler: Add support for tiled formats
2018년 09월 13일 17:49에 Marek Szyprowski 이(가) 쓴 글:
> Hi Inki,
>
> On 2018-09-13 10:23, Inki Dae wrote:
>> 2018년 09월 13일 17:03에 Marek Szyprowski 이(가) 쓴 글:
>>> On 2018-09-13 07:14, Inki Dae wrote:
2018년 09월 12일 15:59에 Andrzej Pietrasiewicz 이(가) 쓴 글:
> W dniu 12.09.2018 o 01:54, Inki Dae pisze:
>> Hi Marek and Andrzej,
>>
>> 2018년 08월 10일 22:29에 Marek Szyprowski 이(가) 쓴 글:
>>> From: Andrzej Pietrasiewicz
>>>
>>> Add support for 16x16 tiled formats: NV12/NV21, YUYV and YUV420.
>
>
>>> -static u32 scaler_get_format(u32 drm_fmt)
>>> +struct scaler_format {
>>> + u32 drm_fmt;
>>> + u32 internal_fmt;
>>> + u32 chroma_tile_w;
>>> + u32 chroma_tile_h;
>>> +};
>>> +
>>> +static const struct scaler_format scaler_formats[] = {
>>> + { DRM_FORMAT_NV12, SCALER_YUV420_2P_UV, 8, 8 },
>>> + { DRM_FORMAT_NV21, SCALER_YUV420_2P_VU, 8, 8 },
>>> + { DRM_FORMAT_YUV420, SCALER_YUV420_3P, 8, 8 },
>>> + { DRM_FORMAT_YUYV, SCALER_YUV422_1P_YUYV, 16, 16 },
>>> + { DRM_FORMAT_UYVY, SCALER_YUV422_1P_UYVY, 16, 16 },
>>> + { DRM_FORMAT_YVYU, SCALER_YUV422_1P_YVYU, 16, 16 },
>>> + { DRM_FORMAT_NV16, SCALER_YUV422_2P_UV, 8, 16 },
>>> + { DRM_FORMAT_NV61, SCALER_YUV422_2P_VU, 8, 16 },
>>> + { DRM_FORMAT_YUV422, SCALER_YUV422_3P, 8, 16 },
>>> + { DRM_FORMAT_NV24, SCALER_YUV444_2P_UV, 16, 16 },
>>> + { DRM_FORMAT_NV42, SCALER_YUV444_2P_VU, 16, 16 },
>>> + { DRM_FORMAT_YUV444, SCALER_YUV444_3P, 16, 16 },
>>> + { DRM_FORMAT_RGB565, SCALER_RGB_565, 0, 0 },
>>> + { DRM_FORMAT_XRGB1555, SCALER_ARGB1555, 0, 0 },
>>> + { DRM_FORMAT_ARGB1555, SCALER_ARGB1555, 0, 0 },
>>> + { DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
>>> + { DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
>>> + { DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
>>> + { DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
>>> + { DRM_FORMAT_RGBX, SCALER_RGBA, 0, 0 },
>>> + { DRM_FORMAT_RGBA, SCALER_RGBA, 0, 0 },
>> Seems the tile size of each format you declared above is wrong.
>> According to data sheet for Exynos5420/5422/5433, each plane has
>> different tile size.
>> I.e., SACLE_YUV420_2P_UV/VU has two planes, and Y plane has 16 x 16 tile
>> size but U and V plane have 8 x 8 tile size each other.
>>
>> However, above declaration has only one tile size
> true, but the members of struct scaler_format are called
>
> _chroma_tile_w/h
>
>> and it means that each plane has always same tile size.
> this conclusion is not justified
>
>> And also RGB formats have 16 x 16 tile size in tile mode but you
>> declared it as 0.
> The data sheet says, that all formats have the same Y/RGB tile size
> and it is always 16x16. That is why only chroma tile size is remembered,
> because only chroma tile size can be different between formats.
Ok, chroma_tile_h/w are used to calculate only the position of the chroma
buffer.
By the way, user space would want to know the size limit in tiled mode so
that they can allocate each buffer for Y(luma) and CbCr(chroma).
However, below code would provide Y/RGB tile size limit - 16 - to user
space,
static const struct drm_exynos_ipp_limit scaler_5420_tile_limits[] = {
{ IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K
})},
{ IPP_SIZE_LIMIT(AREA, .h.align = 16, .v.align = 16) },
It would mean that user space will allocate 16 pixels aligned buffer even
for chroma but the actual size limit of it would be 8 pixels in case of
SCALE_YUV420_WP_UV/VU foramt.
Is there some code I'm missing?
>>> Userspace knows everything needed to allocate proper buffers. Those
>> How does user space know everything? Actually, the size of each plane in
>> tiled mode would depend on Hardware, Scaler device in our case. Is there
>> something user space can know it explictly? Or you mean they can know it
>> implictly?
>
> The size of each plane depends on the selected pixel format only. If you
> select DRM_FORMAT_NV12 + DRM_FORMAT_MOD_SAMSUNG_16_16_TILE modifier,
> then this unambiguously defines buffer size for each plane. Hardware has
> nothing to change here. Userspace can even query if given IPP module
> supports such pixel+modifier combo and get alignment requirements for it.
>
>>> limits describes size of the image buffers in pixels. The size of each
>>> plane (luma or chroma if exists for given format) in bytes directly
>>> comes out of the selected pixel format (fourcc).
>> fourcc would say the size not considered for the Hardware limit.
>
> Alignment can be queried by userspace via get EXYNOS_IPP_GET_LIMITS
> ioctl. It provides limits for
Re: [PATCH 2/3] drm/exynos: scaler: Add support for tiled formats
Hi Inki,
On 2018-09-13 10:23, Inki Dae wrote:
> 2018년 09월 13일 17:03에 Marek Szyprowski 이(가) 쓴 글:
>> On 2018-09-13 07:14, Inki Dae wrote:
>>> 2018년 09월 12일 15:59에 Andrzej Pietrasiewicz 이(가) 쓴 글:
W dniu 12.09.2018 o 01:54, Inki Dae pisze:
> Hi Marek and Andrzej,
>
> 2018년 08월 10일 22:29에 Marek Szyprowski 이(가) 쓴 글:
>> From: Andrzej Pietrasiewicz
>>
>> Add support for 16x16 tiled formats: NV12/NV21, YUYV and YUV420.
>> -static u32 scaler_get_format(u32 drm_fmt)
>> +struct scaler_format {
>> +u32 drm_fmt;
>> +u32 internal_fmt;
>> +u32 chroma_tile_w;
>> +u32 chroma_tile_h;
>> +};
>> +
>> +static const struct scaler_format scaler_formats[] = {
>> +{ DRM_FORMAT_NV12, SCALER_YUV420_2P_UV, 8, 8 },
>> +{ DRM_FORMAT_NV21, SCALER_YUV420_2P_VU, 8, 8 },
>> +{ DRM_FORMAT_YUV420, SCALER_YUV420_3P, 8, 8 },
>> +{ DRM_FORMAT_YUYV, SCALER_YUV422_1P_YUYV, 16, 16 },
>> +{ DRM_FORMAT_UYVY, SCALER_YUV422_1P_UYVY, 16, 16 },
>> +{ DRM_FORMAT_YVYU, SCALER_YUV422_1P_YVYU, 16, 16 },
>> +{ DRM_FORMAT_NV16, SCALER_YUV422_2P_UV, 8, 16 },
>> +{ DRM_FORMAT_NV61, SCALER_YUV422_2P_VU, 8, 16 },
>> +{ DRM_FORMAT_YUV422, SCALER_YUV422_3P, 8, 16 },
>> +{ DRM_FORMAT_NV24, SCALER_YUV444_2P_UV, 16, 16 },
>> +{ DRM_FORMAT_NV42, SCALER_YUV444_2P_VU, 16, 16 },
>> +{ DRM_FORMAT_YUV444, SCALER_YUV444_3P, 16, 16 },
>> +{ DRM_FORMAT_RGB565, SCALER_RGB_565, 0, 0 },
>> +{ DRM_FORMAT_XRGB1555, SCALER_ARGB1555, 0, 0 },
>> +{ DRM_FORMAT_ARGB1555, SCALER_ARGB1555, 0, 0 },
>> +{ DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
>> +{ DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
>> +{ DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
>> +{ DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
>> +{ DRM_FORMAT_RGBX, SCALER_RGBA, 0, 0 },
>> +{ DRM_FORMAT_RGBA, SCALER_RGBA, 0, 0 },
> Seems the tile size of each format you declared above is wrong.
> According to data sheet for Exynos5420/5422/5433, each plane has
> different tile size.
> I.e., SACLE_YUV420_2P_UV/VU has two planes, and Y plane has 16 x 16 tile
> size but U and V plane have 8 x 8 tile size each other.
>
> However, above declaration has only one tile size
true, but the members of struct scaler_format are called
_chroma_tile_w/h
> and it means that each plane has always same tile size.
this conclusion is not justified
> And also RGB formats have 16 x 16 tile size in tile mode but you declared
> it as 0.
The data sheet says, that all formats have the same Y/RGB tile size
and it is always 16x16. That is why only chroma tile size is remembered,
because only chroma tile size can be different between formats.
>>> Ok, chroma_tile_h/w are used to calculate only the position of the chroma
>>> buffer.
>>>
>>> By the way, user space would want to know the size limit in tiled mode so
>>> that they can allocate each buffer for Y(luma) and CbCr(chroma).
>>> However, below code would provide Y/RGB tile size limit - 16 - to user
>>> space,
>>> static const struct drm_exynos_ipp_limit scaler_5420_tile_limits[] = {
>>>{ IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K
>>> })},
>>>{ IPP_SIZE_LIMIT(AREA, .h.align = 16, .v.align = 16) },
>>>
>>> It would mean that user space will allocate 16 pixels aligned buffer even
>>> for chroma but the actual size limit of it would be 8 pixels in case of
>>> SCALE_YUV420_WP_UV/VU foramt.
>>> Is there some code I'm missing?
>> Userspace knows everything needed to allocate proper buffers. Those
> How does user space know everything? Actually, the size of each plane in
> tiled mode would depend on Hardware, Scaler device in our case. Is there
> something user space can know it explictly? Or you mean they can know it
> implictly?
The size of each plane depends on the selected pixel format only. If you
select DRM_FORMAT_NV12 + DRM_FORMAT_MOD_SAMSUNG_16_16_TILE modifier,
then this unambiguously defines buffer size for each plane. Hardware has
nothing to change here. Userspace can even query if given IPP module
supports such pixel+modifier combo and get alignment requirements for it.
>> limits describes size of the image buffers in pixels. The size of each
>> plane (luma or chroma if exists for given format) in bytes directly
>> comes out of the selected pixel format (fourcc).
> fourcc would say the size not considered for the Hardware limit.
Alignment can be queried by userspace via get EXYNOS_IPP_GET_LIMITS
ioctl. It provides limits for given pixel format + tile modifier combo,
although in case of Exynos Scaler, the alignment requirements are simple
result of the tiled
Re: [PATCH 2/3] drm/exynos: scaler: Add support for tiled formats
Hi Marek,
2018년 09월 13일 17:03에 Marek Szyprowski 이(가) 쓴 글:
> Hi Inki,
>
> On 2018-09-13 07:14, Inki Dae wrote:
>> 2018년 09월 12일 15:59에 Andrzej Pietrasiewicz 이(가) 쓴 글:
>>> W dniu 12.09.2018 o 01:54, Inki Dae pisze:
Hi Marek and Andrzej,
2018년 08월 10일 22:29에 Marek Szyprowski 이(가) 쓴 글:
> From: Andrzej Pietrasiewicz
>
> Add support for 16x16 tiled formats: NV12/NV21, YUYV and YUV420.
>>>
>>>
> -static u32 scaler_get_format(u32 drm_fmt)
> +struct scaler_format {
> + u32 drm_fmt;
> + u32 internal_fmt;
> + u32 chroma_tile_w;
> + u32 chroma_tile_h;
> +};
> +
> +static const struct scaler_format scaler_formats[] = {
> + { DRM_FORMAT_NV12, SCALER_YUV420_2P_UV, 8, 8 },
> + { DRM_FORMAT_NV21, SCALER_YUV420_2P_VU, 8, 8 },
> + { DRM_FORMAT_YUV420, SCALER_YUV420_3P, 8, 8 },
> + { DRM_FORMAT_YUYV, SCALER_YUV422_1P_YUYV, 16, 16 },
> + { DRM_FORMAT_UYVY, SCALER_YUV422_1P_UYVY, 16, 16 },
> + { DRM_FORMAT_YVYU, SCALER_YUV422_1P_YVYU, 16, 16 },
> + { DRM_FORMAT_NV16, SCALER_YUV422_2P_UV, 8, 16 },
> + { DRM_FORMAT_NV61, SCALER_YUV422_2P_VU, 8, 16 },
> + { DRM_FORMAT_YUV422, SCALER_YUV422_3P, 8, 16 },
> + { DRM_FORMAT_NV24, SCALER_YUV444_2P_UV, 16, 16 },
> + { DRM_FORMAT_NV42, SCALER_YUV444_2P_VU, 16, 16 },
> + { DRM_FORMAT_YUV444, SCALER_YUV444_3P, 16, 16 },
> + { DRM_FORMAT_RGB565, SCALER_RGB_565, 0, 0 },
> + { DRM_FORMAT_XRGB1555, SCALER_ARGB1555, 0, 0 },
> + { DRM_FORMAT_ARGB1555, SCALER_ARGB1555, 0, 0 },
> + { DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
> + { DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
> + { DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
> + { DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
> + { DRM_FORMAT_RGBX, SCALER_RGBA, 0, 0 },
> + { DRM_FORMAT_RGBA, SCALER_RGBA, 0, 0 },
Seems the tile size of each format you declared above is wrong.
According to data sheet for Exynos5420/5422/5433, each plane has different
tile size.
I.e., SACLE_YUV420_2P_UV/VU has two planes, and Y plane has 16 x 16 tile
size but U and V plane have 8 x 8 tile size each other.
However, above declaration has only one tile size
>>> true, but the members of struct scaler_format are called
>>>
>>> _chroma_tile_w/h
>>>
and it means that each plane has always same tile size.
>>> this conclusion is not justified
>>>
And also RGB formats have 16 x 16 tile size in tile mode but you declared
it as 0.
>>> The data sheet says, that all formats have the same Y/RGB tile size
>>> and it is always 16x16. That is why only chroma tile size is remembered,
>>> because only chroma tile size can be different between formats.
>> Ok, chroma_tile_h/w are used to calculate only the position of the chroma
>> buffer.
>>
>> By the way, user space would want to know the size limit in tiled mode so
>> that they can allocate each buffer for Y(luma) and CbCr(chroma).
>> However, below code would provide Y/RGB tile size limit - 16 - to user space,
>> static const struct drm_exynos_ipp_limit scaler_5420_tile_limits[] = {
>> { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K })},
>> { IPP_SIZE_LIMIT(AREA, .h.align = 16, .v.align = 16) },
>>
>> It would mean that user space will allocate 16 pixels aligned buffer even
>> for chroma but the actual size limit of it would be 8 pixels in case of
>> SCALE_YUV420_WP_UV/VU foramt.
>> Is there some code I'm missing?
>
> Userspace knows everything needed to allocate proper buffers. Those
How does user space know everything? Actually, the size of each plane in tiled
mode would depend on Hardware, Scaler device in our case. Is there something
user space can know it explictly? Or you mean they can know it implictly?
> limits describes size of the image buffers in pixels. The size of each
> plane (luma or chroma if exists for given format) in bytes directly
> comes out of the selected pixel format (fourcc).
fourcc would say the size not considered for the Hardware limit.
Thanks,
Inki Dae
>
> Best regards
>
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 2/3] drm/exynos: scaler: Add support for tiled formats
Hi Inki,
On 2018-09-13 07:14, Inki Dae wrote:
> 2018년 09월 12일 15:59에 Andrzej Pietrasiewicz 이(가) 쓴 글:
>> W dniu 12.09.2018 o 01:54, Inki Dae pisze:
>>> Hi Marek and Andrzej,
>>>
>>> 2018년 08월 10일 22:29에 Marek Szyprowski 이(가) 쓴 글:
From: Andrzej Pietrasiewicz
Add support for 16x16 tiled formats: NV12/NV21, YUYV and YUV420.
>>
>>
-static u32 scaler_get_format(u32 drm_fmt)
+struct scaler_format {
+ u32 drm_fmt;
+ u32 internal_fmt;
+ u32 chroma_tile_w;
+ u32 chroma_tile_h;
+};
+
+static const struct scaler_format scaler_formats[] = {
+ { DRM_FORMAT_NV12, SCALER_YUV420_2P_UV, 8, 8 },
+ { DRM_FORMAT_NV21, SCALER_YUV420_2P_VU, 8, 8 },
+ { DRM_FORMAT_YUV420, SCALER_YUV420_3P, 8, 8 },
+ { DRM_FORMAT_YUYV, SCALER_YUV422_1P_YUYV, 16, 16 },
+ { DRM_FORMAT_UYVY, SCALER_YUV422_1P_UYVY, 16, 16 },
+ { DRM_FORMAT_YVYU, SCALER_YUV422_1P_YVYU, 16, 16 },
+ { DRM_FORMAT_NV16, SCALER_YUV422_2P_UV, 8, 16 },
+ { DRM_FORMAT_NV61, SCALER_YUV422_2P_VU, 8, 16 },
+ { DRM_FORMAT_YUV422, SCALER_YUV422_3P, 8, 16 },
+ { DRM_FORMAT_NV24, SCALER_YUV444_2P_UV, 16, 16 },
+ { DRM_FORMAT_NV42, SCALER_YUV444_2P_VU, 16, 16 },
+ { DRM_FORMAT_YUV444, SCALER_YUV444_3P, 16, 16 },
+ { DRM_FORMAT_RGB565, SCALER_RGB_565, 0, 0 },
+ { DRM_FORMAT_XRGB1555, SCALER_ARGB1555, 0, 0 },
+ { DRM_FORMAT_ARGB1555, SCALER_ARGB1555, 0, 0 },
+ { DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
+ { DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
+ { DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
+ { DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
+ { DRM_FORMAT_RGBX, SCALER_RGBA, 0, 0 },
+ { DRM_FORMAT_RGBA, SCALER_RGBA, 0, 0 },
>>> Seems the tile size of each format you declared above is wrong.
>>> According to data sheet for Exynos5420/5422/5433, each plane has different
>>> tile size.
>>> I.e., SACLE_YUV420_2P_UV/VU has two planes, and Y plane has 16 x 16 tile
>>> size but U and V plane have 8 x 8 tile size each other.
>>>
>>> However, above declaration has only one tile size
>> true, but the members of struct scaler_format are called
>>
>> _chroma_tile_w/h
>>
>>> and it means that each plane has always same tile size.
>> this conclusion is not justified
>>
>>> And also RGB formats have 16 x 16 tile size in tile mode but you declared
>>> it as 0.
>> The data sheet says, that all formats have the same Y/RGB tile size
>> and it is always 16x16. That is why only chroma tile size is remembered,
>> because only chroma tile size can be different between formats.
> Ok, chroma_tile_h/w are used to calculate only the position of the chroma
> buffer.
>
> By the way, user space would want to know the size limit in tiled mode so
> that they can allocate each buffer for Y(luma) and CbCr(chroma).
> However, below code would provide Y/RGB tile size limit - 16 - to user space,
> static const struct drm_exynos_ipp_limit scaler_5420_tile_limits[] = {
> { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K })},
> { IPP_SIZE_LIMIT(AREA, .h.align = 16, .v.align = 16) },
>
> It would mean that user space will allocate 16 pixels aligned buffer even for
> chroma but the actual size limit of it would be 8 pixels in case of
> SCALE_YUV420_WP_UV/VU foramt.
> Is there some code I'm missing?
Userspace knows everything needed to allocate proper buffers. Those
limits describes size of the image buffers in pixels. The size of each
plane (luma or chroma if exists for given format) in bytes directly
comes out of the selected pixel format (fourcc).
Best regards
--
Marek Szyprowski, PhD
Samsung R Institute Poland
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 2/3] drm/exynos: scaler: Add support for tiled formats
2018년 09월 12일 15:59에 Andrzej Pietrasiewicz 이(가) 쓴 글:
> Hi Inki,
>
> W dniu 12.09.2018 o 01:54, Inki Dae pisze:
>> Hi Marek and Andrzej,
>>
>> 2018년 08월 10일 22:29에 Marek Szyprowski 이(가) 쓴 글:
>>> From: Andrzej Pietrasiewicz
>>>
>>> Add support for 16x16 tiled formats: NV12/NV21, YUYV and YUV420.
>>>
>
>
>
>>>
>>> -static u32 scaler_get_format(u32 drm_fmt)
>>> +struct scaler_format {
>>> + u32 drm_fmt;
>>> + u32 internal_fmt;
>>> + u32 chroma_tile_w;
>>> + u32 chroma_tile_h;
>>> +};
>>> +
>>> +static const struct scaler_format scaler_formats[] = {
>>> + { DRM_FORMAT_NV12, SCALER_YUV420_2P_UV, 8, 8 },
>>> + { DRM_FORMAT_NV21, SCALER_YUV420_2P_VU, 8, 8 },
>>> + { DRM_FORMAT_YUV420, SCALER_YUV420_3P, 8, 8 },
>>> + { DRM_FORMAT_YUYV, SCALER_YUV422_1P_YUYV, 16, 16 },
>>> + { DRM_FORMAT_UYVY, SCALER_YUV422_1P_UYVY, 16, 16 },
>>> + { DRM_FORMAT_YVYU, SCALER_YUV422_1P_YVYU, 16, 16 },
>>> + { DRM_FORMAT_NV16, SCALER_YUV422_2P_UV, 8, 16 },
>>> + { DRM_FORMAT_NV61, SCALER_YUV422_2P_VU, 8, 16 },
>>> + { DRM_FORMAT_YUV422, SCALER_YUV422_3P, 8, 16 },
>>> + { DRM_FORMAT_NV24, SCALER_YUV444_2P_UV, 16, 16 },
>>> + { DRM_FORMAT_NV42, SCALER_YUV444_2P_VU, 16, 16 },
>>> + { DRM_FORMAT_YUV444, SCALER_YUV444_3P, 16, 16 },
>>> + { DRM_FORMAT_RGB565, SCALER_RGB_565, 0, 0 },
>>> + { DRM_FORMAT_XRGB1555, SCALER_ARGB1555, 0, 0 },
>>> + { DRM_FORMAT_ARGB1555, SCALER_ARGB1555, 0, 0 },
>>> + { DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
>>> + { DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
>>> + { DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
>>> + { DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
>>> + { DRM_FORMAT_RGBX, SCALER_RGBA, 0, 0 },
>>> + { DRM_FORMAT_RGBA, SCALER_RGBA, 0, 0 },
>>
>> Seems the tile size of each format you declared above is wrong.
>> According to data sheet for Exynos5420/5422/5433, each plane has different
>> tile size.
>> I.e., SACLE_YUV420_2P_UV/VU has two planes, and Y plane has 16 x 16 tile
>> size but U and V plane have 8 x 8 tile size each other.
>>
>> However, above declaration has only one tile size
>
> true, but the members of struct scaler_format are called
>
> _chroma_tile_w/h
>
>> and it means that each plane has always same tile size.
>
> this conclusion is not justified
>
>> And also RGB formats have 16 x 16 tile size in tile mode but you declared it
>> as 0.
>
> The data sheet says, that all formats have the same Y/RGB tile size
> and it is always 16x16. That is why only chroma tile size is remembered,
> because only chroma tile size can be different between formats.
Ok, chroma_tile_h/w are used to calculate only the position of the chroma
buffer.
By the way, user space would want to know the size limit in tiled mode so that
they can allocate each buffer for Y(luma) and CbCr(chroma).
However, below code would provide Y/RGB tile size limit - 16 - to user space,
static const struct drm_exynos_ipp_limit scaler_5420_tile_limits[] = {
{ IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K })},
{ IPP_SIZE_LIMIT(AREA, .h.align = 16, .v.align = 16) },
It would mean that user space will allocate 16 pixels aligned buffer even for
chroma but the actual size limit of it would be 8 pixels in case of
SCALE_YUV420_WP_UV/VU foramt.
Is there some code I'm missing?
Thanks,
Inki Dae
>
> RGB formats don't have any chroma component, hence zero chroma_tile_w/h.
>
> Regards,
>
> Andrzej
>
>
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 2/3] drm/exynos: scaler: Add support for tiled formats
Hi Inki,
W dniu 12.09.2018 o 01:54, Inki Dae pisze:
> Hi Marek and Andrzej,
>
> 2018년 08월 10일 22:29에 Marek Szyprowski 이(가) 쓴 글:
>> From: Andrzej Pietrasiewicz
>>
>> Add support for 16x16 tiled formats: NV12/NV21, YUYV and YUV420.
>>
>>
>> -static u32 scaler_get_format(u32 drm_fmt)
>> +struct scaler_format {
>> +u32 drm_fmt;
>> +u32 internal_fmt;
>> +u32 chroma_tile_w;
>> +u32 chroma_tile_h;
>> +};
>> +
>> +static const struct scaler_format scaler_formats[] = {
>> +{ DRM_FORMAT_NV12, SCALER_YUV420_2P_UV, 8, 8 },
>> +{ DRM_FORMAT_NV21, SCALER_YUV420_2P_VU, 8, 8 },
>> +{ DRM_FORMAT_YUV420, SCALER_YUV420_3P, 8, 8 },
>> +{ DRM_FORMAT_YUYV, SCALER_YUV422_1P_YUYV, 16, 16 },
>> +{ DRM_FORMAT_UYVY, SCALER_YUV422_1P_UYVY, 16, 16 },
>> +{ DRM_FORMAT_YVYU, SCALER_YUV422_1P_YVYU, 16, 16 },
>> +{ DRM_FORMAT_NV16, SCALER_YUV422_2P_UV, 8, 16 },
>> +{ DRM_FORMAT_NV61, SCALER_YUV422_2P_VU, 8, 16 },
>> +{ DRM_FORMAT_YUV422, SCALER_YUV422_3P, 8, 16 },
>> +{ DRM_FORMAT_NV24, SCALER_YUV444_2P_UV, 16, 16 },
>> +{ DRM_FORMAT_NV42, SCALER_YUV444_2P_VU, 16, 16 },
>> +{ DRM_FORMAT_YUV444, SCALER_YUV444_3P, 16, 16 },
>> +{ DRM_FORMAT_RGB565, SCALER_RGB_565, 0, 0 },
>> +{ DRM_FORMAT_XRGB1555, SCALER_ARGB1555, 0, 0 },
>> +{ DRM_FORMAT_ARGB1555, SCALER_ARGB1555, 0, 0 },
>> +{ DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
>> +{ DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
>> +{ DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
>> +{ DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
>> +{ DRM_FORMAT_RGBX, SCALER_RGBA, 0, 0 },
>> +{ DRM_FORMAT_RGBA, SCALER_RGBA, 0, 0 },
>
> Seems the tile size of each format you declared above is wrong.
> According to data sheet for Exynos5420/5422/5433, each plane has different
> tile size.
> I.e., SACLE_YUV420_2P_UV/VU has two planes, and Y plane has 16 x 16 tile size
> but U and V plane have 8 x 8 tile size each other.
>
> However, above declaration has only one tile size
true, but the members of struct scaler_format are called
_chroma_tile_w/h
> and it means that each plane has always same tile size.
this conclusion is not justified
> And also RGB formats have 16 x 16 tile size in tile mode but you declared it
> as 0.
The data sheet says, that all formats have the same Y/RGB tile size
and it is always 16x16. That is why only chroma tile size is remembered,
because only chroma tile size can be different between formats.
RGB formats don't have any chroma component, hence zero chroma_tile_w/h.
Regards,
Andrzej
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 2/3] drm/exynos: scaler: Add support for tiled formats
Hi Marek and Andrzej,
2018년 08월 10일 22:29에 Marek Szyprowski 이(가) 쓴 글:
> From: Andrzej Pietrasiewicz
>
> Add support for 16x16 tiled formats: NV12/NV21, YUYV and YUV420.
>
> Signed-off-by: Andrzej Pietrasiewicz
> Signed-off-by: Marek Szyprowski
> ---
> drivers/gpu/drm/exynos/exynos_drm_scaler.c | 133 -
> 1 file changed, 75 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_scaler.c
> b/drivers/gpu/drm/exynos/exynos_drm_scaler.c
> index 0ddb6eec7b11..8e761ef63eac 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_scaler.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_scaler.c
> @@ -49,56 +49,46 @@ struct scaler_context {
> const struct scaler_data*scaler_data;
> };
>
> -static u32 scaler_get_format(u32 drm_fmt)
> +struct scaler_format {
> + u32 drm_fmt;
> + u32 internal_fmt;
> + u32 chroma_tile_w;
> + u32 chroma_tile_h;
> +};
> +
> +static const struct scaler_format scaler_formats[] = {
> + { DRM_FORMAT_NV12, SCALER_YUV420_2P_UV, 8, 8 },
> + { DRM_FORMAT_NV21, SCALER_YUV420_2P_VU, 8, 8 },
> + { DRM_FORMAT_YUV420, SCALER_YUV420_3P, 8, 8 },
> + { DRM_FORMAT_YUYV, SCALER_YUV422_1P_YUYV, 16, 16 },
> + { DRM_FORMAT_UYVY, SCALER_YUV422_1P_UYVY, 16, 16 },
> + { DRM_FORMAT_YVYU, SCALER_YUV422_1P_YVYU, 16, 16 },
> + { DRM_FORMAT_NV16, SCALER_YUV422_2P_UV, 8, 16 },
> + { DRM_FORMAT_NV61, SCALER_YUV422_2P_VU, 8, 16 },
> + { DRM_FORMAT_YUV422, SCALER_YUV422_3P, 8, 16 },
> + { DRM_FORMAT_NV24, SCALER_YUV444_2P_UV, 16, 16 },
> + { DRM_FORMAT_NV42, SCALER_YUV444_2P_VU, 16, 16 },
> + { DRM_FORMAT_YUV444, SCALER_YUV444_3P, 16, 16 },
> + { DRM_FORMAT_RGB565, SCALER_RGB_565, 0, 0 },
> + { DRM_FORMAT_XRGB1555, SCALER_ARGB1555, 0, 0 },
> + { DRM_FORMAT_ARGB1555, SCALER_ARGB1555, 0, 0 },
> + { DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
> + { DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
> + { DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
> + { DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
> + { DRM_FORMAT_RGBX, SCALER_RGBA, 0, 0 },
> + { DRM_FORMAT_RGBA, SCALER_RGBA, 0, 0 },
Seems the tile size of each format you declared above is wrong.
According to data sheet for Exynos5420/5422/5433, each plane has different tile
size.
I.e., SACLE_YUV420_2P_UV/VU has two planes, and Y plane has 16 x 16 tile size
but U and V plane have 8 x 8 tile size each other.
However, above declaration has only one tile size and it means that each plane
has always same tile size.
And also RGB formats have 16 x 16 tile size in tile mode but you declared it as
0.
Could you check it out again?
Thanks,
Inki Dae
> +};
> +
> +static const struct scaler_format *scaler_get_format(u32 drm_fmt)
> {
> - switch (drm_fmt) {
> - case DRM_FORMAT_NV12:
> - return SCALER_YUV420_2P_UV;
> - case DRM_FORMAT_NV21:
> - return SCALER_YUV420_2P_VU;
> - case DRM_FORMAT_YUV420:
> - return SCALER_YUV420_3P;
> - case DRM_FORMAT_YUYV:
> - return SCALER_YUV422_1P_YUYV;
> - case DRM_FORMAT_UYVY:
> - return SCALER_YUV422_1P_UYVY;
> - case DRM_FORMAT_YVYU:
> - return SCALER_YUV422_1P_YVYU;
> - case DRM_FORMAT_NV16:
> - return SCALER_YUV422_2P_UV;
> - case DRM_FORMAT_NV61:
> - return SCALER_YUV422_2P_VU;
> - case DRM_FORMAT_YUV422:
> - return SCALER_YUV422_3P;
> - case DRM_FORMAT_NV24:
> - return SCALER_YUV444_2P_UV;
> - case DRM_FORMAT_NV42:
> - return SCALER_YUV444_2P_VU;
> - case DRM_FORMAT_YUV444:
> - return SCALER_YUV444_3P;
> - case DRM_FORMAT_RGB565:
> - return SCALER_RGB_565;
> - case DRM_FORMAT_XRGB1555:
> - return SCALER_ARGB1555;
> - case DRM_FORMAT_ARGB1555:
> - return SCALER_ARGB1555;
> - case DRM_FORMAT_XRGB:
> - return SCALER_ARGB;
> - case DRM_FORMAT_ARGB:
> - return SCALER_ARGB;
> - case DRM_FORMAT_XRGB:
> - return SCALER_ARGB;
> - case DRM_FORMAT_ARGB:
> - return SCALER_ARGB;
> - case DRM_FORMAT_RGBX:
> - return SCALER_RGBA;
> - case DRM_FORMAT_RGBA:
> - return SCALER_RGBA;
> - default:
> - break;
> - }
> + int i;
>
> - return 0;
> + for (i = 0; i < ARRAY_SIZE(scaler_formats); i++)
> + if (scaler_formats[i].drm_fmt == drm_fmt)
> + return _formats[i];
> +
> + return NULL;
> }
>
> static inline int scaler_reset(struct scaler_context *scaler)
> @@ -152,11 +142,11 @@ static inline void scaler_enable_int(struct
> scaler_context *scaler)
> }
>
> static inline void scaler_set_src_fmt(struct scaler_context *scaler,
> - u32 src_fmt)
> + u32 src_fmt, u32 tile)
> {
> u32 val;
>
> - val =
[PATCH 2/3] drm/exynos: scaler: Add support for tiled formats
From: Andrzej Pietrasiewicz
Add support for 16x16 tiled formats: NV12/NV21, YUYV and YUV420.
Signed-off-by: Andrzej Pietrasiewicz
Signed-off-by: Marek Szyprowski
---
drivers/gpu/drm/exynos/exynos_drm_scaler.c | 133 -
1 file changed, 75 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_scaler.c
b/drivers/gpu/drm/exynos/exynos_drm_scaler.c
index 0ddb6eec7b11..8e761ef63eac 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_scaler.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_scaler.c
@@ -49,56 +49,46 @@ struct scaler_context {
const struct scaler_data*scaler_data;
};
-static u32 scaler_get_format(u32 drm_fmt)
+struct scaler_format {
+ u32 drm_fmt;
+ u32 internal_fmt;
+ u32 chroma_tile_w;
+ u32 chroma_tile_h;
+};
+
+static const struct scaler_format scaler_formats[] = {
+ { DRM_FORMAT_NV12, SCALER_YUV420_2P_UV, 8, 8 },
+ { DRM_FORMAT_NV21, SCALER_YUV420_2P_VU, 8, 8 },
+ { DRM_FORMAT_YUV420, SCALER_YUV420_3P, 8, 8 },
+ { DRM_FORMAT_YUYV, SCALER_YUV422_1P_YUYV, 16, 16 },
+ { DRM_FORMAT_UYVY, SCALER_YUV422_1P_UYVY, 16, 16 },
+ { DRM_FORMAT_YVYU, SCALER_YUV422_1P_YVYU, 16, 16 },
+ { DRM_FORMAT_NV16, SCALER_YUV422_2P_UV, 8, 16 },
+ { DRM_FORMAT_NV61, SCALER_YUV422_2P_VU, 8, 16 },
+ { DRM_FORMAT_YUV422, SCALER_YUV422_3P, 8, 16 },
+ { DRM_FORMAT_NV24, SCALER_YUV444_2P_UV, 16, 16 },
+ { DRM_FORMAT_NV42, SCALER_YUV444_2P_VU, 16, 16 },
+ { DRM_FORMAT_YUV444, SCALER_YUV444_3P, 16, 16 },
+ { DRM_FORMAT_RGB565, SCALER_RGB_565, 0, 0 },
+ { DRM_FORMAT_XRGB1555, SCALER_ARGB1555, 0, 0 },
+ { DRM_FORMAT_ARGB1555, SCALER_ARGB1555, 0, 0 },
+ { DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
+ { DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
+ { DRM_FORMAT_XRGB, SCALER_ARGB, 0, 0 },
+ { DRM_FORMAT_ARGB, SCALER_ARGB, 0, 0 },
+ { DRM_FORMAT_RGBX, SCALER_RGBA, 0, 0 },
+ { DRM_FORMAT_RGBA, SCALER_RGBA, 0, 0 },
+};
+
+static const struct scaler_format *scaler_get_format(u32 drm_fmt)
{
- switch (drm_fmt) {
- case DRM_FORMAT_NV12:
- return SCALER_YUV420_2P_UV;
- case DRM_FORMAT_NV21:
- return SCALER_YUV420_2P_VU;
- case DRM_FORMAT_YUV420:
- return SCALER_YUV420_3P;
- case DRM_FORMAT_YUYV:
- return SCALER_YUV422_1P_YUYV;
- case DRM_FORMAT_UYVY:
- return SCALER_YUV422_1P_UYVY;
- case DRM_FORMAT_YVYU:
- return SCALER_YUV422_1P_YVYU;
- case DRM_FORMAT_NV16:
- return SCALER_YUV422_2P_UV;
- case DRM_FORMAT_NV61:
- return SCALER_YUV422_2P_VU;
- case DRM_FORMAT_YUV422:
- return SCALER_YUV422_3P;
- case DRM_FORMAT_NV24:
- return SCALER_YUV444_2P_UV;
- case DRM_FORMAT_NV42:
- return SCALER_YUV444_2P_VU;
- case DRM_FORMAT_YUV444:
- return SCALER_YUV444_3P;
- case DRM_FORMAT_RGB565:
- return SCALER_RGB_565;
- case DRM_FORMAT_XRGB1555:
- return SCALER_ARGB1555;
- case DRM_FORMAT_ARGB1555:
- return SCALER_ARGB1555;
- case DRM_FORMAT_XRGB:
- return SCALER_ARGB;
- case DRM_FORMAT_ARGB:
- return SCALER_ARGB;
- case DRM_FORMAT_XRGB:
- return SCALER_ARGB;
- case DRM_FORMAT_ARGB:
- return SCALER_ARGB;
- case DRM_FORMAT_RGBX:
- return SCALER_RGBA;
- case DRM_FORMAT_RGBA:
- return SCALER_RGBA;
- default:
- break;
- }
+ int i;
- return 0;
+ for (i = 0; i < ARRAY_SIZE(scaler_formats); i++)
+ if (scaler_formats[i].drm_fmt == drm_fmt)
+ return _formats[i];
+
+ return NULL;
}
static inline int scaler_reset(struct scaler_context *scaler)
@@ -152,11 +142,11 @@ static inline void scaler_enable_int(struct
scaler_context *scaler)
}
static inline void scaler_set_src_fmt(struct scaler_context *scaler,
- u32 src_fmt)
+ u32 src_fmt, u32 tile)
{
u32 val;
- val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt);
+ val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt) | (tile << 10);
scaler_write(val, SCALER_SRC_CFG);
}
@@ -188,15 +178,19 @@ static inline void scaler_set_src_span(struct
scaler_context *scaler,
scaler_write(val, SCALER_SRC_SPAN);
}
-static inline void scaler_set_src_luma_pos(struct scaler_context *scaler,
- struct drm_exynos_ipp_task_rect *src_pos)
+static inline void scaler_set_src_luma_chroma_pos(struct scaler_context
*scaler,
+ struct drm_exynos_ipp_task_rect *src_pos, const struct scaler_format
*fmt)
{
u32 val;
val = SCALER_SRC_Y_POS_SET_YH_POS(src_pos->x << 2);
