[PATCH 29/88] drm/amdgpu: add amdgpu uapi header (v4)
On Tue, Jun 9, 2015 at 4:51 AM, Alex Deucher wrote: > On Fri, Jun 5, 2015 at 2:57 PM, Jerome Glisse wrote: >> On Tue, May 26, 2015 at 11:19:31PM -0400, Alex Deucher wrote: >>> This header defines the ioctl interface to the driver. >>> >>> v2: remove stale tiling defines >>> v3: add appropriate padding >>> v4: remove executable bits on header >>> >>> Acked-by: Christian König >>> Acked-by: Jammy Zhou >>> Signed-off-by: Alex Deucher >>> --- >>> include/uapi/drm/amdgpu_drm.h | 590 >>> ++ >>> 1 file changed, 590 insertions(+) >>> create mode 100644 include/uapi/drm/amdgpu_drm.h >>> >>> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h >>> new file mode 100644 >>> index 000..9e771fb >>> --- /dev/null >>> +++ b/include/uapi/drm/amdgpu_drm.h >>> @@ -0,0 +1,590 @@ >>> +/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- >>> + * >>> + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. >>> + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. >>> + * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. >>> + * Copyright 2014 Advanced Micro Devices, Inc. >>> + * >>> + * Permission is hereby granted, free of charge, to any person obtaining a >>> + * copy of this software and associated documentation files (the >>> "Software"), >>> + * to deal in the Software without restriction, including without >>> limitation >>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense, >>> + * and/or sell copies of the Software, and to permit persons to whom the >>> + * Software is furnished to do so, subject to the following conditions: >>> + * >>> + * The above copyright notice and this permission notice shall be included >>> in >>> + * all copies or substantial portions of the Software. >>> + * >>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS >>> OR >>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >>> + * OTHER DEALINGS IN THE SOFTWARE. >>> + * >>> + * Authors: >>> + *Kevin E. Martin >>> + *Gareth Hughes >>> + *Keith Whitwell >>> + */ >>> + >>> +#ifndef __AMDGPU_DRM_H__ >>> +#define __AMDGPU_DRM_H__ >>> + >>> +#include >>> + >>> +#define DRM_AMDGPU_GEM_CREATE0x00 >>> +#define DRM_AMDGPU_GEM_MMAP 0x01 >>> +#define DRM_AMDGPU_CTX 0x02 >>> +#define DRM_AMDGPU_BO_LIST 0x03 >>> +#define DRM_AMDGPU_CS0x04 >>> +#define DRM_AMDGPU_INFO 0x05 >>> +#define DRM_AMDGPU_GEM_METADATA 0x06 >>> +#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 >>> +#define DRM_AMDGPU_GEM_VA0x08 >>> +#define DRM_AMDGPU_WAIT_CS 0x09 >>> +#define DRM_AMDGPU_GEM_OP0x10 >>> +#define DRM_AMDGPU_GEM_USERPTR 0x11 >>> + >>> +#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + >>> DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) >>> +#define DRM_IOCTL_AMDGPU_GEM_MMAPDRM_IOWR(DRM_COMMAND_BASE + >>> DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) >>> +#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + >>> DRM_AMDGPU_CTX, union drm_amdgpu_ctx) >>> +#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + >>> DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) >>> +#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + >>> DRM_AMDGPU_CS, union drm_amdgpu_cs) >>> +#define DRM_IOCTL_AMDGPU_INFODRM_IOW(DRM_COMMAND_BASE + >>> DRM_AMDGPU_INFO, struct drm_amdgpu_info) >>> +#define DRM_IOCTL_AMDGPU_GEM_METADATADRM_IOWR(DRM_COMMAND_BASE + >>> DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) >>> +#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + >>> DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) >>> +#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + >>> DRM_AMDGPU_GEM_VA, union drm_amdgpu_gem_va) >>> +#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + >>> DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) >>> +#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + >>> DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) >>> +#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + >>> DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) >>> + >>> +#define AMDGPU_GEM_DOMAIN_CPU0x1 >>> +#define AMDGPU_GEM_DOMAIN_GTT0x2 >>> +#define AMDGPU_GEM_DOMAIN_VRAM 0x4 >>> +#define AMDGPU_GEM_DOMAIN_GDS0x8 >>> +#define AMDGPU_GEM_DOMAIN_GWS0x10 >>> +#define
[PATCH 29/88] drm/amdgpu: add amdgpu uapi header (v4)
On Fri, Jun 5, 2015 at 2:57 PM, Jerome Glisse wrote: > On Tue, May 26, 2015 at 11:19:31PM -0400, Alex Deucher wrote: >> This header defines the ioctl interface to the driver. >> >> v2: remove stale tiling defines >> v3: add appropriate padding >> v4: remove executable bits on header >> >> Acked-by: Christian König >> Acked-by: Jammy Zhou >> Signed-off-by: Alex Deucher >> --- >> include/uapi/drm/amdgpu_drm.h | 590 >> ++ >> 1 file changed, 590 insertions(+) >> create mode 100644 include/uapi/drm/amdgpu_drm.h >> >> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h >> new file mode 100644 >> index 000..9e771fb >> --- /dev/null >> +++ b/include/uapi/drm/amdgpu_drm.h >> @@ -0,0 +1,590 @@ >> +/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- >> + * >> + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. >> + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. >> + * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. >> + * Copyright 2014 Advanced Micro Devices, Inc. >> + * >> + * Permission is hereby granted, free of charge, to any person obtaining a >> + * copy of this software and associated documentation files (the >> "Software"), >> + * to deal in the Software without restriction, including without limitation >> + * the rights to use, copy, modify, merge, publish, distribute, sublicense, >> + * and/or sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following conditions: >> + * >> + * The above copyright notice and this permission notice shall be included >> in >> + * all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS >> OR >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + * >> + * Authors: >> + *Kevin E. Martin >> + *Gareth Hughes >> + *Keith Whitwell >> + */ >> + >> +#ifndef __AMDGPU_DRM_H__ >> +#define __AMDGPU_DRM_H__ >> + >> +#include >> + >> +#define DRM_AMDGPU_GEM_CREATE0x00 >> +#define DRM_AMDGPU_GEM_MMAP 0x01 >> +#define DRM_AMDGPU_CTX 0x02 >> +#define DRM_AMDGPU_BO_LIST 0x03 >> +#define DRM_AMDGPU_CS0x04 >> +#define DRM_AMDGPU_INFO 0x05 >> +#define DRM_AMDGPU_GEM_METADATA 0x06 >> +#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 >> +#define DRM_AMDGPU_GEM_VA0x08 >> +#define DRM_AMDGPU_WAIT_CS 0x09 >> +#define DRM_AMDGPU_GEM_OP0x10 >> +#define DRM_AMDGPU_GEM_USERPTR 0x11 >> + >> +#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + >> DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) >> +#define DRM_IOCTL_AMDGPU_GEM_MMAPDRM_IOWR(DRM_COMMAND_BASE + >> DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) >> +#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + >> DRM_AMDGPU_CTX, union drm_amdgpu_ctx) >> +#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + >> DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) >> +#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + >> DRM_AMDGPU_CS, union drm_amdgpu_cs) >> +#define DRM_IOCTL_AMDGPU_INFODRM_IOW(DRM_COMMAND_BASE + >> DRM_AMDGPU_INFO, struct drm_amdgpu_info) >> +#define DRM_IOCTL_AMDGPU_GEM_METADATADRM_IOWR(DRM_COMMAND_BASE + >> DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) >> +#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + >> DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) >> +#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + >> DRM_AMDGPU_GEM_VA, union drm_amdgpu_gem_va) >> +#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + >> DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) >> +#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + >> DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) >> +#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + >> DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) >> + >> +#define AMDGPU_GEM_DOMAIN_CPU0x1 >> +#define AMDGPU_GEM_DOMAIN_GTT0x2 >> +#define AMDGPU_GEM_DOMAIN_VRAM 0x4 >> +#define AMDGPU_GEM_DOMAIN_GDS0x8 >> +#define AMDGPU_GEM_DOMAIN_GWS0x10 >> +#define AMDGPU_GEM_DOMAIN_OA 0x20 > > Can we get a description on this new domains (GDS, GWS, OA) ? GDS, GWS, and OA are on chip shader resources that can be allocated
[PATCH 29/88] drm/amdgpu: add amdgpu uapi header (v4)
On Tue, May 26, 2015 at 11:19:31PM -0400, Alex Deucher wrote: > This header defines the ioctl interface to the driver. > > v2: remove stale tiling defines > v3: add appropriate padding > v4: remove executable bits on header > > Acked-by: Christian König > Acked-by: Jammy Zhou > Signed-off-by: Alex Deucher > --- > include/uapi/drm/amdgpu_drm.h | 590 > ++ > 1 file changed, 590 insertions(+) > create mode 100644 include/uapi/drm/amdgpu_drm.h > > diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h > new file mode 100644 > index 000..9e771fb > --- /dev/null > +++ b/include/uapi/drm/amdgpu_drm.h > @@ -0,0 +1,590 @@ > +/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- > + * > + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. > + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. > + * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. > + * Copyright 2014 Advanced Micro Devices, Inc. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + * > + * Authors: > + *Kevin E. Martin > + *Gareth Hughes > + *Keith Whitwell > + */ > + > +#ifndef __AMDGPU_DRM_H__ > +#define __AMDGPU_DRM_H__ > + > +#include > + > +#define DRM_AMDGPU_GEM_CREATE0x00 > +#define DRM_AMDGPU_GEM_MMAP 0x01 > +#define DRM_AMDGPU_CTX 0x02 > +#define DRM_AMDGPU_BO_LIST 0x03 > +#define DRM_AMDGPU_CS0x04 > +#define DRM_AMDGPU_INFO 0x05 > +#define DRM_AMDGPU_GEM_METADATA 0x06 > +#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 > +#define DRM_AMDGPU_GEM_VA0x08 > +#define DRM_AMDGPU_WAIT_CS 0x09 > +#define DRM_AMDGPU_GEM_OP0x10 > +#define DRM_AMDGPU_GEM_USERPTR 0x11 > + > +#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + > DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) > +#define DRM_IOCTL_AMDGPU_GEM_MMAPDRM_IOWR(DRM_COMMAND_BASE + > DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) > +#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + > DRM_AMDGPU_CTX, union drm_amdgpu_ctx) > +#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + > DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) > +#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + > DRM_AMDGPU_CS, union drm_amdgpu_cs) > +#define DRM_IOCTL_AMDGPU_INFODRM_IOW(DRM_COMMAND_BASE + > DRM_AMDGPU_INFO, struct drm_amdgpu_info) > +#define DRM_IOCTL_AMDGPU_GEM_METADATADRM_IOWR(DRM_COMMAND_BASE + > DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) > +#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + > DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) > +#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + > DRM_AMDGPU_GEM_VA, union drm_amdgpu_gem_va) > +#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + > DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) > +#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + > DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) > +#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + > DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) > + > +#define AMDGPU_GEM_DOMAIN_CPU0x1 > +#define AMDGPU_GEM_DOMAIN_GTT0x2 > +#define AMDGPU_GEM_DOMAIN_VRAM 0x4 > +#define AMDGPU_GEM_DOMAIN_GDS0x8 > +#define AMDGPU_GEM_DOMAIN_GWS0x10 > +#define AMDGPU_GEM_DOMAIN_OA 0x20 Can we get a description on this new domains (GDS, GWS, OA) ? > + > +#define AMDGPU_GEM_DOMAIN_MASK 0x3F > + > +/* Flag that CPU access will be required for the case of VRAM domain */ > +#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED(1 << 0) > +/* Flag that CPU access will not
[PATCH 29/88] drm/amdgpu: add amdgpu uapi header (v4)
This header defines the ioctl interface to the driver. v2: remove stale tiling defines v3: add appropriate padding v4: remove executable bits on header Acked-by: Christian König Acked-by: Jammy Zhou Signed-off-by: Alex Deucher --- include/uapi/drm/amdgpu_drm.h | 590 ++ 1 file changed, 590 insertions(+) create mode 100644 include/uapi/drm/amdgpu_drm.h diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h new file mode 100644 index 000..9e771fb --- /dev/null +++ b/include/uapi/drm/amdgpu_drm.h @@ -0,0 +1,590 @@ +/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- + * + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. + * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + *Kevin E. Martin + *Gareth Hughes + *Keith Whitwell + */ + +#ifndef __AMDGPU_DRM_H__ +#define __AMDGPU_DRM_H__ + +#include + +#define DRM_AMDGPU_GEM_CREATE 0x00 +#define DRM_AMDGPU_GEM_MMAP0x01 +#define DRM_AMDGPU_CTX 0x02 +#define DRM_AMDGPU_BO_LIST 0x03 +#define DRM_AMDGPU_CS 0x04 +#define DRM_AMDGPU_INFO0x05 +#define DRM_AMDGPU_GEM_METADATA0x06 +#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 +#define DRM_AMDGPU_GEM_VA 0x08 +#define DRM_AMDGPU_WAIT_CS 0x09 +#define DRM_AMDGPU_GEM_OP 0x10 +#define DRM_AMDGPU_GEM_USERPTR 0x11 + +#define DRM_IOCTL_AMDGPU_GEM_CREATEDRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) +#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) +#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) +#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) +#define DRM_IOCTL_AMDGPU_CSDRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) +#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) +#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) +#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) +#define DRM_IOCTL_AMDGPU_GEM_VADRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, union drm_amdgpu_gem_va) +#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) +#define DRM_IOCTL_AMDGPU_GEM_OPDRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) +#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) + +#define AMDGPU_GEM_DOMAIN_CPU 0x1 +#define AMDGPU_GEM_DOMAIN_GTT 0x2 +#define AMDGPU_GEM_DOMAIN_VRAM 0x4 +#define AMDGPU_GEM_DOMAIN_GDS 0x8 +#define AMDGPU_GEM_DOMAIN_GWS 0x10 +#define AMDGPU_GEM_DOMAIN_OA 0x20 + +#define AMDGPU_GEM_DOMAIN_MASK 0x3F + +/* Flag that CPU access will be required for the case of VRAM domain */ +#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) +/* Flag that CPU access will not work, this VRAM domain is invisible */ +#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS(1 << 1) +/* Flag that un-cached attributes should be used for GTT */ +#define AMDGPU_GEM_CREATE_CPU_GTT_UC (1 << 2) +/* Flag that USWC attributes should be used for GTT */ +#define AMDGPU_GEM_CREATE_CPU_GTT_WC (1 << 3) + +/* Flag mask for GTT domain_flags */ +#define
