[PATCH 3/3] drm/radeon/kms: fix 2D tiling CS support on EG/CM

2011-11-28 Thread alexdeuc...@gmail.com 
From: Alex Deucher 

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=43191

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/evergreen_cs.c |  149 +++--
 drivers/gpu/drm/radeon/evergreend.h   |   31 +++
 2 files changed, 154 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c 
b/drivers/gpu/drm/radeon/evergreen_cs.c
index 38e1bda..cd4590a 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -38,6 +38,7 @@ struct evergreen_cs_track {
u32 group_size;
u32 nbanks;
u32 npipes;
+   u32 row_size;
/* value we track */
u32 nsamples;
u32 cb_color_base_last[12];
@@ -77,6 +78,44 @@ struct evergreen_cs_track {
struct radeon_bo*db_s_write_bo;
 };

+static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
+{
+   if (tiling_flags & RADEON_TILING_MACRO)
+   return ARRAY_2D_TILED_THIN1;
+   else if (tiling_flags & RADEON_TILING_MICRO)
+   return ARRAY_1D_TILED_THIN1;
+   else
+   return ARRAY_LINEAR_GENERAL;
+}
+
+static u32 evergreen_cs_get_num_banks(u32 nbanks)
+{
+   switch (nbanks) {
+   case 2:
+   return ADDR_SURF_2_BANK;
+   case 4:
+   return ADDR_SURF_4_BANK;
+   case 8:
+   default:
+   return ADDR_SURF_8_BANK;
+   case 16:
+   return ADDR_SURF_16_BANK;
+   }
+}
+
+static u32 evergreen_cs_get_tile_split(u32 row_size)
+{
+   switch (row_size) {
+   case 1:
+   default:
+   return ADDR_SURF_TILE_SPLIT_1KB;
+   case 2:
+   return ADDR_SURF_TILE_SPLIT_2KB;
+   case 4:
+   return ADDR_SURF_TILE_SPLIT_4KB;
+   }
+}
+
 static void evergreen_cs_track_init(struct evergreen_cs_track *track)
 {
int i;
@@ -490,12 +529,11 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser 
*p, u32 reg, u32 idx)
}
ib[idx] &= ~Z_ARRAY_MODE(0xf);
track->db_z_info &= ~Z_ARRAY_MODE(0xf);
+   ib[idx] |= 
Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
+   track->db_z_info |= 
Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
-   ib[idx] |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-   track->db_z_info |= 
Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-   } else {
-   ib[idx] |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
-   track->db_z_info |= 
Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
+   ib[idx] |= 
DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
+   ib[idx] |= 
DB_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size));
}
}
break;
@@ -618,13 +656,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser 
*p, u32 reg, u32 idx)
"0x%04X\n", reg);
return -EINVAL;
}
-   if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
-   ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-   track->cb_color_info[tmp] |= 
CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-   } else if (reloc->lobj.tiling_flags & 
RADEON_TILING_MICRO) {
-   ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
-   track->cb_color_info[tmp] |= 
CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
-   }
+   ib[idx] |= 
CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
+   track->cb_color_info[tmp] |= 
CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
}
break;
case CB_COLOR8_INFO:
@@ -640,13 +673,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser 
*p, u32 reg, u32 idx)
"0x%04X\n", reg);
return -EINVAL;
}
-   if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
-   ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-   track->cb_color_info[tmp] |= 
CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-   } else if (reloc->lobj.tiling_flags & 
RADEON_TILING_MICRO) {
-   ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
-

[PATCH 3/3] drm/radeon/kms: fix 2D tiling CS support on EG/CM

2011-11-28 Thread alexdeucher 
From: Alex Deucher alexander.deuc...@amd.com

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=43191

Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
 drivers/gpu/drm/radeon/evergreen_cs.c |  149 +++--
 drivers/gpu/drm/radeon/evergreend.h   |   31 +++
 2 files changed, 154 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c 
b/drivers/gpu/drm/radeon/evergreen_cs.c
index 38e1bda..cd4590a 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -38,6 +38,7 @@ struct evergreen_cs_track {
u32 group_size;
u32 nbanks;
u32 npipes;
+   u32 row_size;
/* value we track */
u32 nsamples;
u32 cb_color_base_last[12];
@@ -77,6 +78,44 @@ struct evergreen_cs_track {
struct radeon_bo*db_s_write_bo;
 };
 
+static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
+{
+   if (tiling_flags  RADEON_TILING_MACRO)
+   return ARRAY_2D_TILED_THIN1;
+   else if (tiling_flags  RADEON_TILING_MICRO)
+   return ARRAY_1D_TILED_THIN1;
+   else
+   return ARRAY_LINEAR_GENERAL;
+}
+
+static u32 evergreen_cs_get_num_banks(u32 nbanks)
+{
+   switch (nbanks) {
+   case 2:
+   return ADDR_SURF_2_BANK;
+   case 4:
+   return ADDR_SURF_4_BANK;
+   case 8:
+   default:
+   return ADDR_SURF_8_BANK;
+   case 16:
+   return ADDR_SURF_16_BANK;
+   }
+}
+
+static u32 evergreen_cs_get_tile_split(u32 row_size)
+{
+   switch (row_size) {
+   case 1:
+   default:
+   return ADDR_SURF_TILE_SPLIT_1KB;
+   case 2:
+   return ADDR_SURF_TILE_SPLIT_2KB;
+   case 4:
+   return ADDR_SURF_TILE_SPLIT_4KB;
+   }
+}
+
 static void evergreen_cs_track_init(struct evergreen_cs_track *track)
 {
int i;
@@ -490,12 +529,11 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser 
*p, u32 reg, u32 idx)
}
ib[idx] = ~Z_ARRAY_MODE(0xf);
track-db_z_info = ~Z_ARRAY_MODE(0xf);
+   ib[idx] |= 
Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc-lobj.tiling_flags));
+   track-db_z_info |= 
Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc-lobj.tiling_flags));
if (reloc-lobj.tiling_flags  RADEON_TILING_MACRO) {
-   ib[idx] |= Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-   track-db_z_info |= 
Z_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-   } else {
-   ib[idx] |= Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
-   track-db_z_info |= 
Z_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
+   ib[idx] |= 
DB_NUM_BANKS(evergreen_cs_get_num_banks(track-nbanks));
+   ib[idx] |= 
DB_TILE_SPLIT(evergreen_cs_get_tile_split(track-row_size));
}
}
break;
@@ -618,13 +656,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser 
*p, u32 reg, u32 idx)
0x%04X\n, reg);
return -EINVAL;
}
-   if (reloc-lobj.tiling_flags  RADEON_TILING_MACRO) {
-   ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-   track-cb_color_info[tmp] |= 
CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-   } else if (reloc-lobj.tiling_flags  
RADEON_TILING_MICRO) {
-   ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
-   track-cb_color_info[tmp] |= 
CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
-   }
+   ib[idx] |= 
CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc-lobj.tiling_flags));
+   track-cb_color_info[tmp] |= 
CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc-lobj.tiling_flags));
}
break;
case CB_COLOR8_INFO:
@@ -640,13 +673,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser 
*p, u32 reg, u32 idx)
0x%04X\n, reg);
return -EINVAL;
}
-   if (reloc-lobj.tiling_flags  RADEON_TILING_MACRO) {
-   ib[idx] |= CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-   track-cb_color_info[tmp] |= 
CB_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
-   } else if (reloc-lobj.tiling_flags  
RADEON_TILING_MICRO) {
-   ib[idx] |= CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
-