Re: [PATCH 3/4] drm/vc4: Add register defines for CEC.

2017-07-12 Thread Eric Anholt 
Hans Verkuil  writes:

> From: Eric Anholt 
>
> Basic usage:
>
> poweron: HSM clock should be running.  Set the bit clock divider,
> set all the other _US timeouts based on bit clock rate.  Bring RX/TX
> reset up and then down.
>
> powerdown: Set RX/TX reset.
>
> interrupt: read CPU_STATUS, write bits that have been handled to
> CPU_CLEAR.
>
> Bits are added to /debug/dri/0/hdmi_regs so you can check out the
> power-on values.

Let's drop my hints to you from the commit message here :)


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[PATCH 3/4] drm/vc4: Add register defines for CEC.

2017-07-11 Thread Hans Verkuil 
From: Eric Anholt 

Basic usage:

poweron: HSM clock should be running.  Set the bit clock divider,
set all the other _US timeouts based on bit clock rate.  Bring RX/TX
reset up and then down.

powerdown: Set RX/TX reset.

interrupt: read CPU_STATUS, write bits that have been handled to
CPU_CLEAR.

Bits are added to /debug/dri/0/hdmi_regs so you can check out the
power-on values.

Signed-off-by: Eric Anholt 
Signed-off-by: Hans Verkuil 
---
 drivers/gpu/drm/vc4/vc4_hdmi.c |  16 ++
 drivers/gpu/drm/vc4/vc4_regs.h | 108 +
 2 files changed, 124 insertions(+)

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index e0104f96011e..b0521e6cc281 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -149,6 +149,22 @@ static const struct {
HDMI_REG(VC4_HDMI_VERTB1),
HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),
HDMI_REG(VC4_HDMI_TX_PHY_CTL0),
+
+   HDMI_REG(VC4_HDMI_CEC_CNTRL_1),
+   HDMI_REG(VC4_HDMI_CEC_CNTRL_2),
+   HDMI_REG(VC4_HDMI_CEC_CNTRL_3),
+   HDMI_REG(VC4_HDMI_CEC_CNTRL_4),
+   HDMI_REG(VC4_HDMI_CEC_CNTRL_5),
+   HDMI_REG(VC4_HDMI_CPU_STATUS),
+
+   HDMI_REG(VC4_HDMI_CEC_RX_DATA_1),
+   HDMI_REG(VC4_HDMI_CEC_RX_DATA_2),
+   HDMI_REG(VC4_HDMI_CEC_RX_DATA_3),
+   HDMI_REG(VC4_HDMI_CEC_RX_DATA_4),
+   HDMI_REG(VC4_HDMI_CEC_TX_DATA_1),
+   HDMI_REG(VC4_HDMI_CEC_TX_DATA_2),
+   HDMI_REG(VC4_HDMI_CEC_TX_DATA_3),
+   HDMI_REG(VC4_HDMI_CEC_TX_DATA_4),
 };
 
 static const struct {
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index d382c34c1b9e..b18cc20ee185 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -561,16 +561,124 @@
 # define VC4_HDMI_VERTB_VBP_MASK   VC4_MASK(8, 0)
 # define VC4_HDMI_VERTB_VBP_SHIFT  0
 
+#define VC4_HDMI_CEC_CNTRL_1   0x0e8
+/* Set when the transmission has ended. */
+# define VC4_HDMI_CEC_TX_EOM   BIT(31)
+/* If set, transmission was acked on the 1st or 2nd attempt (only one
+ * retry is attempted).  If in continuous mode, this means TX needs to
+ * be filled if !TX_EOM.
+ */
+# define VC4_HDMI_CEC_TX_STATUS_GOOD   BIT(30)
+# define VC4_HDMI_CEC_RX_EOM   BIT(29)
+# define VC4_HDMI_CEC_RX_STATUS_GOOD   BIT(28)
+/* Number of bytes received for the message. */
+# define VC4_HDMI_CEC_REC_WRD_CNT_MASK VC4_MASK(27, 24)
+# define VC4_HDMI_CEC_REC_WRD_CNT_SHIFT24
+/* Sets continuous receive mode.  Generates interrupt after each 8
+ * bytes to signal that RX_DATA should be consumed, and at RX_EOM.
+ *
+ * If disabled, maximum 16 bytes will be received (including header),
+ * and interrupt at RX_EOM.  Later bytes will be acked but not put
+ * into the RX_DATA.
+ */
+# define VC4_HDMI_CEC_RX_CONTINUE  BIT(23)
+# define VC4_HDMI_CEC_TX_CONTINUE  BIT(22)
+/* Set this after a CEC interrupt. */
+# define VC4_HDMI_CEC_CLEAR_RECEIVE_OFFBIT(21)
+/* Starts a TX.  Will wait for appropriate idel time before CEC
+ * activity. Must be cleared in between transmits.
+ */
+# define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20)
+# define VC4_HDMI_CEC_MESSAGE_LENGTH_MASK  VC4_MASK(19, 16)
+# define VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT 16
+/* Device's CEC address */
+# define VC4_HDMI_CEC_ADDR_MASKVC4_MASK(15, 12)
+# define VC4_HDMI_CEC_ADDR_SHIFT   12
+/* Divides off of HSM clock to generate CEC bit clock. */
+# define VC4_HDMI_CEC_DIV_CLK_CNT_MASK VC4_MASK(11, 0)
+# define VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT0
+
+/* Set these fields to how many bit clock cycles get to that many
+ * microseconds.
+ */
+#define VC4_HDMI_CEC_CNTRL_2   0x0ec
+# define VC4_HDMI_CEC_CNT_TO_1500_US_MASK  VC4_MASK(30, 24)
+# define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT 24
+# define VC4_HDMI_CEC_CNT_TO_1300_US_MASK  VC4_MASK(23, 17)
+# define VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT 17
+# define VC4_HDMI_CEC_CNT_TO_800_US_MASK   VC4_MASK(16, 11)
+# define VC4_HDMI_CEC_CNT_TO_800_US_SHIFT  11
+# define VC4_HDMI_CEC_CNT_TO_600_US_MASK   VC4_MASK(10, 5)
+# define VC4_HDMI_CEC_CNT_TO_600_US_SHIFT  5
+# define VC4_HDMI_CEC_CNT_TO_400_US_MASK   VC4_MASK(4, 0)
+# define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT  0
+
+#define VC4_HDMI_CEC_CNTRL_3   0x0f0
+# define VC4_HDMI_CEC_CNT_TO_2750_US_MASK  VC4_MASK(31, 24)
+# define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT 24
+# define VC4_HDMI_CEC_CNT_TO_2400_US_MASK  VC4_MASK(23, 16)
+# define VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT 16
+# define VC4_HDMI_CEC_CNT_TO_2050_US_MASK  VC4_MASK(15, 8)
+# define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT 8
+# define VC4_HDMI_CEC_CNT_TO_1700_US_MASK  VC4_MASK(7, 0)
+# define