Re: [PATCH 4/4] PCI: Add a REBAR size quirk for Sapphire RX 5600 XT Pulse
Am 07.01.21 um 22:32 schrieb Bjorn Helgaas: On Thu, Jan 07, 2021 at 06:50:17PM +0100, Nirmoy Das wrote: RX 5600 XT Pulse advertises support for BAR0 being 256MB, 512MB, or 1GB, but it also supports 2GB, 4GB, and 8GB. Add a rebar size quirk so that CPU can fully access the BAR0. This isn't quite accurate. The CPU can fully access BAR 0 no matter what. I think the problem you're solving is that without this quirk, BAR 0 isn't big enough to cover the VRAM. Signed-off-by: Christian König Reported-by: kernel test robot Reported-by: Dan Carpenter IIRC, these Reported-by lines are from the "cap == 0x3f0" problem. It would make sense to include these if this patch fixed that problem in something that had already been merged. But this *hasn't* been merged, so these lines only make sense to someone who trawls through the mailing list to find the previous version. I don't really think it's worthwhile to include them. It's the same as giving credit to reviewers, which we typically don't do except via a Reviewed-by tag (which I think is too strong for this case) or a "v2" changes note after the "---" line. That doesn't get included in the git history, but is easily findable via the Link: tags as below. If you merge these via a non-PCI tree, please include the "Link:" lines in the PCI patches, e.g., Link: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fr%2F20210107175017.15893-5-nirmoy.das%40amd.com&data=04%7C01%7Cchristian.koenig%40amd.com%7C33c14f5361e84d9d0e4908d8b353c412%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637456519678601616%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=wY9qaz3DTZA069qznMC9Wvoq9SZIzyJHE0XkaVXoqAc%3D&reserved=0 for this one. Obviously the link is different for each patch and will change if you repost the series. I'm not sure why you put the amd patch in the middle of the series. Seems like it would be slightly prettier and just as safe to put it at the end. Signed-off-by: Nirmoy Das Acked-by: Bjorn Helgaas Let me know if you want me to take the series. I will make the suggested changes and take this through the drm subsystem. That makes more sense since it only affects our hardware anyway. --- drivers/pci/pci.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 16216186b51c..b061bbd4afb1 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3577,7 +3577,14 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) return 0; pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); - return (cap & PCI_REBAR_CAP_SIZES) >> 4; + cap = (cap & PCI_REBAR_CAP_SIZES) >> 4; + + /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ + if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && + bar == 0 && cap == 0x700) + cap = 0x3f00; I think this is structured wrong. It should be like this so it's easier to match with the spec: cap &= PCI_REBAR_CAP_SIZES; if (... && cap == 0x7000) cap = 0x3f000; return cap >> 4; Good point. Thanks, Christian. + + return cap; } EXPORT_SYMBOL(pci_rebar_get_possible_sizes); -- 2.29.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 4/4] PCI: Add a REBAR size quirk for Sapphire RX 5600 XT Pulse
On Thu, Jan 07, 2021 at 06:50:17PM +0100, Nirmoy Das wrote: > RX 5600 XT Pulse advertises support for BAR0 being 256MB, 512MB, > or 1GB, but it also supports 2GB, 4GB, and 8GB. Add a rebar > size quirk so that CPU can fully access the BAR0. This isn't quite accurate. The CPU can fully access BAR 0 no matter what. I think the problem you're solving is that without this quirk, BAR 0 isn't big enough to cover the VRAM. > Signed-off-by: Christian König > Reported-by: kernel test robot > Reported-by: Dan Carpenter IIRC, these Reported-by lines are from the "cap == 0x3f0" problem. It would make sense to include these if this patch fixed that problem in something that had already been merged. But this *hasn't* been merged, so these lines only make sense to someone who trawls through the mailing list to find the previous version. I don't really think it's worthwhile to include them. It's the same as giving credit to reviewers, which we typically don't do except via a Reviewed-by tag (which I think is too strong for this case) or a "v2" changes note after the "---" line. That doesn't get included in the git history, but is easily findable via the Link: tags as below. If you merge these via a non-PCI tree, please include the "Link:" lines in the PCI patches, e.g., Link: https://lore.kernel.org/r/20210107175017.15893-5-nirmoy@amd.com for this one. Obviously the link is different for each patch and will change if you repost the series. I'm not sure why you put the amd patch in the middle of the series. Seems like it would be slightly prettier and just as safe to put it at the end. > Signed-off-by: Nirmoy Das Acked-by: Bjorn Helgaas Let me know if you want me to take the series. > --- > drivers/pci/pci.c | 9 - > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index 16216186b51c..b061bbd4afb1 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -3577,7 +3577,14 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, > int bar) > return 0; > > pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); > - return (cap & PCI_REBAR_CAP_SIZES) >> 4; > + cap = (cap & PCI_REBAR_CAP_SIZES) >> 4; > + > + /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ > + if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && > + bar == 0 && cap == 0x700) > + cap = 0x3f00; I think this is structured wrong. It should be like this so it's easier to match with the spec: cap &= PCI_REBAR_CAP_SIZES; if (... && cap == 0x7000) cap = 0x3f000; return cap >> 4; > + > + return cap; > } > EXPORT_SYMBOL(pci_rebar_get_possible_sizes); > > -- > 2.29.2 > ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 4/4] PCI: Add a REBAR size quirk for Sapphire RX 5600 XT Pulse
RX 5600 XT Pulse advertises support for BAR0 being 256MB, 512MB, or 1GB, but it also supports 2GB, 4GB, and 8GB. Add a rebar size quirk so that CPU can fully access the BAR0. Signed-off-by: Christian König Reported-by: kernel test robot Reported-by: Dan Carpenter Signed-off-by: Nirmoy Das --- drivers/pci/pci.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 16216186b51c..b061bbd4afb1 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3577,7 +3577,14 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) return 0; pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); - return (cap & PCI_REBAR_CAP_SIZES) >> 4; + cap = (cap & PCI_REBAR_CAP_SIZES) >> 4; + + /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ + if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && + bar == 0 && cap == 0x700) + cap = 0x3f00; + + return cap; } EXPORT_SYMBOL(pci_rebar_get_possible_sizes); -- 2.29.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[kbuild] Re: [PATCH 4/4] PCI: add a REBAR size quirk for Sapphire RX 5600 XT Pulse.
Hi Christian,
url:
https://github.com/0day-ci/linux/commits/Christian-K-nig/pci-export-pci_rebar_get_possible_sizes/20210105-224446
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: x86_64-randconfig-m001-20210105 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
Reported-by: Dan Carpenter
smatch warnings:
drivers/pci/pci.c:3611 pci_rebar_get_possible_sizes() warn: statement has no
effect 22
vim +3611 drivers/pci/pci.c
276b738deb5bf85 Christian König 2017-10-24 3596 u32
pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
276b738deb5bf85 Christian König 2017-10-24 3597 {
276b738deb5bf85 Christian König 2017-10-24 3598int pos;
276b738deb5bf85 Christian König 2017-10-24 3599u32 cap;
276b738deb5bf85 Christian König 2017-10-24 3600
276b738deb5bf85 Christian König 2017-10-24 3601pos =
pci_rebar_find_pos(pdev, bar);
276b738deb5bf85 Christian König 2017-10-24 3602if (pos < 0)
276b738deb5bf85 Christian König 2017-10-24 3603return 0;
276b738deb5bf85 Christian König 2017-10-24 3604
276b738deb5bf85 Christian König 2017-10-24 3605
pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
6838a45fc2394ec Christian König 2021-01-05 3606cap = (cap &
PCI_REBAR_CAP_SIZES) >> 4;
6838a45fc2394ec Christian König 2021-01-05 3607
6838a45fc2394ec Christian König 2021-01-05 3608/* Sapphire RX 5600 XT
Pulse has an invalid cap dword for BAR 0 */
6838a45fc2394ec Christian König 2021-01-05 3609if (pdev->vendor ==
PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
6838a45fc2394ec Christian König 2021-01-05 3610bar == 0 && cap ==
0x700)
6838a45fc2394ec Christian König 2021-01-05 @3611cap == 0x7f00;
== vs =.
6838a45fc2394ec Christian König 2021-01-05 3612
6838a45fc2394ec Christian König 2021-01-05 3613return cap;
276b738deb5bf85 Christian König 2017-10-24 3614 }
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Re: [PATCH 4/4] PCI: add a REBAR size quirk for Sapphire RX 5600 XT Pulse.
Am 05.01.21 um 17:11 schrieb Ilia Mirkin: On Tue, Jan 5, 2021 at 8:44 AM Christian König wrote: Otherwise the CPU can't fully access the BAR. Signed-off-by: Christian König --- drivers/pci/pci.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 16216186b51c..b66e4703c214 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3577,7 +3577,14 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) return 0; pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); - return (cap & PCI_REBAR_CAP_SIZES) >> 4; + cap = (cap & PCI_REBAR_CAP_SIZES) >> 4; + + /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ + if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && + bar == 0 && cap == 0x700) + cap == 0x7f00; Perhaps you meant cap = 0x7f00? Ups, indeed! Thanks for pointing that out. Christian. + + return cap; } EXPORT_SYMBOL(pci_rebar_get_possible_sizes); -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 4/4] PCI: add a REBAR size quirk for Sapphire RX 5600 XT Pulse.
Hi "Christian,
I love your patch! Perhaps something to improve:
[auto build test WARNING on pci/next]
[also build test WARNING on linus/master v5.11-rc2 next-20210104]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Christian-K-nig/pci-export-pci_rebar_get_possible_sizes/20210105-224446
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: arm64-randconfig-r006-20210105 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
5c951623bc8965fa1e89660f2f5f4a2944e4981a)
reproduce (this is a W=1 build):
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
#
https://github.com/0day-ci/linux/commit/6838a45fc2394ec88455e1fb3998ac865a077168
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Christian-K-nig/pci-export-pci_rebar_get_possible_sizes/20210105-224446
git checkout 6838a45fc2394ec88455e1fb3998ac865a077168
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All warnings (new ones prefixed by >>):
>> drivers/pci/pci.c:3611:7: warning: equality comparison result unused
>> [-Wunused-comparison]
cap == 0x7f00;
^
drivers/pci/pci.c:3611:7: note: use '=' to turn this equality comparison
into an assignment
cap == 0x7f00;
^~
=
1 warning generated.
vim +3611 drivers/pci/pci.c
3587
3588 /**
3589 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3590 * @pdev: PCI device
3591 * @bar: BAR to query
3592 *
3593 * Get the possible sizes of a resizable BAR as bitmask defined in the
spec
3594 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3595 */
3596 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3597 {
3598 int pos;
3599 u32 cap;
3600
3601 pos = pci_rebar_find_pos(pdev, bar);
3602 if (pos < 0)
3603 return 0;
3604
3605 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3606 cap = (cap & PCI_REBAR_CAP_SIZES) >> 4;
3607
3608 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0
*/
3609 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f
&&
3610 bar == 0 && cap == 0x700)
> 3611 cap == 0x7f00;
3612
3613 return cap;
3614 }
3615 EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3616
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Re: [PATCH 4/4] PCI: add a REBAR size quirk for Sapphire RX 5600 XT Pulse.
On Tue, Jan 5, 2021 at 8:44 AM Christian König wrote: > > Otherwise the CPU can't fully access the BAR. > > Signed-off-by: Christian König > --- > drivers/pci/pci.c | 9 - > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index 16216186b51c..b66e4703c214 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -3577,7 +3577,14 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, > int bar) > return 0; > > pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); > - return (cap & PCI_REBAR_CAP_SIZES) >> 4; > + cap = (cap & PCI_REBAR_CAP_SIZES) >> 4; > + > + /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ > + if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && > + bar == 0 && cap == 0x700) > + cap == 0x7f00; Perhaps you meant cap = 0x7f00? > + > + return cap; > } > EXPORT_SYMBOL(pci_rebar_get_possible_sizes); > > -- > 2.25.1 > > ___ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 4/4] PCI: add a REBAR size quirk for Sapphire RX 5600 XT Pulse.
Otherwise the CPU can't fully access the BAR. Signed-off-by: Christian König --- drivers/pci/pci.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 16216186b51c..b66e4703c214 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3577,7 +3577,14 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) return 0; pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); - return (cap & PCI_REBAR_CAP_SIZES) >> 4; + cap = (cap & PCI_REBAR_CAP_SIZES) >> 4; + + /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ + if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && + bar == 0 && cap == 0x700) + cap == 0x7f00; + + return cap; } EXPORT_SYMBOL(pci_rebar_get_possible_sizes); -- 2.25.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
