Re: [PATCH 5/5] arm: dts: sc7180: Add A618 gpu dt blob
Hi Sharat,
on which tree is this patch based on? It does not apply against
qcom/arm64-for-5.6-to-be-rebased.
In one of my repos which has a non-upstream Qualcomm tree as remote git can
make sense of the hashes in the index line, however the parent of your patch
looks quite different from the maintainer version.
Another thing that hints towards a custom tree:
> + interconnects = <&gem_noc 35 &mc_virt 512>;
To my knowledge no patches have been posted to add the referenced interconnect
nodes for SC7180.
Please base your patches on the appropriate maintainer tree(s).
Thanks
Matthias
On Tue, Dec 03, 2019 at 03:16:18PM +, Sharat Masetty wrote:
> This patch adds the required dt nodes and properties
> to enabled A618 GPU.
>
> Signed-off-by: Sharat Masetty
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 116
> +++
> 1 file changed, 116 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index c3db2e5..31223d0 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -18,6 +18,8 @@
> #include
> #include
> #include
> +#include
> +#include
>
> / {
> interrupt-parent = <&intc>;
> @@ -733,6 +735,120 @@
> #power-domain-cells = <1>;
> };
>
> + gpu: gpu@500 {
> + compatible = "qcom,adreno-618.0", "qcom,adreno";
> + #stream-id-cells = <16>;
> + reg = <0 0x500 0 0x4>, <0 0x509e000 0 0x1000>,
> + <0 0x5061000 0 0x800>;
> + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
> +
> + interrupts = ;
> +
> + iommus = <&adreno_smmu 0>;
> +
> + operating-points-v2 = <&gpu_opp_table>;
> +
> + interconnects = <&gem_noc 35 &mc_virt 512>;
> +
> + qcom,gmu = <&gmu>;
> +
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-8 {
> + opp-hz = /bits/ 64 <8>;
> + opp-level =
> ;
> + };
> +
> + opp-65000 {
> + opp-hz = /bits/ 64 <65000>;
> + opp-level =
> ;
> + };
> +
> + opp-56500 {
> + opp-hz = /bits/ 64 <56500>;
> + opp-level = ;
> + };
> +
> + opp-43000 {
> + opp-hz = /bits/ 64 <43000>;
> + opp-level =
> ;
> + };
> +
> +opp-35500 {
> + opp-hz = /bits/ 64 <35500>;
> + opp-level = ;
> + };
> +
> +opp-26700 {
> + opp-hz = /bits/ 64 <26700>;
> + opp-level =
> ;
> + };
> +
> + opp-18000 {
> + opp-hz = /bits/ 64 <18000>;
> + opp-level =
> ;
> + };
> + };
> + };
> +
> + adreno_smmu: iommu@504 {
> + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
> + reg = <0 0x504 0 0x1>;
> + #iommu-cells = <1>;
> + #global-interrupts = <2>;
> + interrupts = ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ,
> + ;
> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gcc GCC_GPU_CFG_AHB_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>;
> +
> + clock-names = "bus", "iface", "mem_iface_clk";
> + power-domains = <&gpucc CX_GDSC>;
> + };
> +
> + gmu: gmu@506a000 {
> + compatible="qcom,adreno-gmu-618", "qcom,adreno-gmu";
> +
> + reg = <0 0x506a000 0 0x31000>,
> + <0 0xb29 0 0x1>,
> +
[PATCH 5/5] arm: dts: sc7180: Add A618 gpu dt blob
This patch adds the required dt nodes and properties
to enabled A618 GPU.
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 116 +++
1 file changed, 116 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index c3db2e5..31223d0 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -18,6 +18,8 @@
#include
#include
#include
+#include
+#include
/ {
interrupt-parent = <&intc>;
@@ -733,6 +735,120 @@
#power-domain-cells = <1>;
};
+ gpu: gpu@500 {
+ compatible = "qcom,adreno-618.0", "qcom,adreno";
+ #stream-id-cells = <16>;
+ reg = <0 0x500 0 0x4>, <0 0x509e000 0 0x1000>,
+ <0 0x5061000 0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
+
+ interrupts = ;
+
+ iommus = <&adreno_smmu 0>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ interconnects = <&gem_noc 35 &mc_virt 512>;
+
+ qcom,gmu = <&gmu>;
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-8 {
+ opp-hz = /bits/ 64 <8>;
+ opp-level =
;
+ };
+
+ opp-65000 {
+ opp-hz = /bits/ 64 <65000>;
+ opp-level =
;
+ };
+
+ opp-56500 {
+ opp-hz = /bits/ 64 <56500>;
+ opp-level = ;
+ };
+
+ opp-43000 {
+ opp-hz = /bits/ 64 <43000>;
+ opp-level =
;
+ };
+
+opp-35500 {
+ opp-hz = /bits/ 64 <35500>;
+ opp-level = ;
+ };
+
+opp-26700 {
+ opp-hz = /bits/ 64 <26700>;
+ opp-level =
;
+ };
+
+ opp-18000 {
+ opp-hz = /bits/ 64 <18000>;
+ opp-level =
;
+ };
+ };
+ };
+
+ adreno_smmu: iommu@504 {
+ compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
+ reg = <0 0x504 0 0x1>;
+ #iommu-cells = <1>;
+ #global-interrupts = <2>;
+ interrupts = ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ;
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_CFG_AHB_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>;
+
+ clock-names = "bus", "iface", "mem_iface_clk";
+ power-domains = <&gpucc CX_GDSC>;
+ };
+
+ gmu: gmu@506a000 {
+ compatible="qcom,adreno-gmu-618", "qcom,adreno-gmu";
+
+ reg = <0 0x506a000 0 0x31000>,
+ <0 0xb29 0 0x1>,
+ <0 0xb49 0 0x1>;
+ reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+ interrupts = ,
+ ;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+ clock-names = "gmu", "cxo", "axi", "memnoc";
+
+ power-domains = <&gpucc CX_GDSC>;
+
+ iommus = <&adreno_smmu 5>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+
[PATCH 5/5] arm: dts: sc7180: Add A618 gpu dt blob
This patch adds the required dt nodes and properties
to enabled A618 GPU.
Change-Id: I7491c4de654c4b84d03dbcf703532448b27d4147
Signed-off-by: Sharat Masetty
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 116 +++
1 file changed, 116 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index c3db2e5..31223d0 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -18,6 +18,8 @@
#include
#include
#include
+#include
+#include
/ {
interrupt-parent = <&intc>;
@@ -733,6 +735,120 @@
#power-domain-cells = <1>;
};
+ gpu: gpu@500 {
+ compatible = "qcom,adreno-618.0", "qcom,adreno";
+ #stream-id-cells = <16>;
+ reg = <0 0x500 0 0x4>, <0 0x509e000 0 0x1000>,
+ <0 0x5061000 0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
+
+ interrupts = ;
+
+ iommus = <&adreno_smmu 0>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ interconnects = <&gem_noc 35 &mc_virt 512>;
+
+ qcom,gmu = <&gmu>;
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-8 {
+ opp-hz = /bits/ 64 <8>;
+ opp-level =
;
+ };
+
+ opp-65000 {
+ opp-hz = /bits/ 64 <65000>;
+ opp-level =
;
+ };
+
+ opp-56500 {
+ opp-hz = /bits/ 64 <56500>;
+ opp-level = ;
+ };
+
+ opp-43000 {
+ opp-hz = /bits/ 64 <43000>;
+ opp-level =
;
+ };
+
+opp-35500 {
+ opp-hz = /bits/ 64 <35500>;
+ opp-level = ;
+ };
+
+opp-26700 {
+ opp-hz = /bits/ 64 <26700>;
+ opp-level =
;
+ };
+
+ opp-18000 {
+ opp-hz = /bits/ 64 <18000>;
+ opp-level =
;
+ };
+ };
+ };
+
+ adreno_smmu: iommu@504 {
+ compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
+ reg = <0 0x504 0 0x1>;
+ #iommu-cells = <1>;
+ #global-interrupts = <2>;
+ interrupts = ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ,
+ ;
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_CFG_AHB_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>;
+
+ clock-names = "bus", "iface", "mem_iface_clk";
+ power-domains = <&gpucc CX_GDSC>;
+ };
+
+ gmu: gmu@506a000 {
+ compatible="qcom,adreno-gmu-618", "qcom,adreno-gmu";
+
+ reg = <0 0x506a000 0 0x31000>,
+ <0 0xb29 0 0x1>,
+ <0 0xb49 0 0x1>;
+ reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+ interrupts = ,
+ ;
+ interrupt-names = "hfi", "gmu";
+
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+ clock-names = "gmu", "cxo", "axi", "memnoc";
+
+ power-domains = <&gpucc CX_GDSC>;
+
+ iommus = <&adreno_smmu 5>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
