Re: [PATCH v10 4/4] arm64: dts: zynqmp: zcu106-revA: Wire up the DisplayPort subsystem

[Laurent Pinchart]

Hi Michal,

On Fri, Nov 15, 2019 at 09:30:10AM +0100, Michal Simek wrote:
> On 08. 11. 19 18:59, Laurent Pinchart wrote:
> > Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to
> > the DisplayPort connector.
> > 
> > Signed-off-by: Laurent Pinchart 
> > ---
> >  .../arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 16 
> >  1 file changed, 16 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts 
> > b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> > index 93ce7eb81498..4656f25b6b04 100644
> > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> > @@ -13,6 +13,7 @@
> >  #include "zynqmp-clk.dtsi"
> >  #include 
> >  #include 
> > +#include 
> >  
> >  / {
> > model = "ZynqMP ZCU106 RevA";
> > @@ -69,6 +70,17 @@
> > status = "okay";
> >  };
> >  
> > + {
> > +   status = "okay";
> > +};
> > +
> > + {
> > +   status = "okay";
> > +   phy-names = "dp-phy0", "dp-phy1";
> > +   phys = < PHY_TYPE_DP 0 3 2700>,
> > +  < PHY_TYPE_DP 1 3 2700>;
> 
> It is aligned with stuff in Xilinx tree.
> I think that putting any clock value here is wrong.
> It should really be pointing to  whatever it is.
> Then you can support more cases where clock doesn't need to be fixed and
> it is also aligned with clock binding.

OK, I'll check that when working on the PHY driver.

> > +};
> > +
> >  /* fpd_dma clk 667MHz, lpd_dma 500MHz */
> >  _dma_chan1 {
> > status = "okay";
> > @@ -503,6 +515,10 @@
> > no-1-8-v;
> >  };
> >  
> > + {
> > +   status = "okay";
> > +};
> > +
> >   {
> > status = "okay";
> >  };

-- 
Regards,

Laurent Pinchart
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Re: [PATCH v10 4/4] arm64: dts: zynqmp: zcu106-revA: Wire up the DisplayPort subsystem

[Michal Simek]

On 08. 11. 19 18:59, Laurent Pinchart wrote:
> Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to
> the DisplayPort connector.
> 
> Signed-off-by: Laurent Pinchart 
> ---
>  .../arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 16 
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts 
> b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> index 93ce7eb81498..4656f25b6b04 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
> @@ -13,6 +13,7 @@
>  #include "zynqmp-clk.dtsi"
>  #include 
>  #include 
> +#include 
>  
>  / {
>   model = "ZynqMP ZCU106 RevA";
> @@ -69,6 +70,17 @@
>   status = "okay";
>  };
>  
> + {
> + status = "okay";
> +};
> +
> + {
> + status = "okay";
> + phy-names = "dp-phy0", "dp-phy1";
> + phys = < PHY_TYPE_DP 0 3 2700>,
> +< PHY_TYPE_DP 1 3 2700>;

It is aligned with stuff in Xilinx tree.
I think that putting any clock value here is wrong.
It should really be pointing to  whatever it is.
Then you can support more cases where clock doesn't need to be fixed and
it is also aligned with clock binding.

> +};
> +
>  /* fpd_dma clk 667MHz, lpd_dma 500MHz */
>  _dma_chan1 {
>   status = "okay";
> @@ -503,6 +515,10 @@
>   no-1-8-v;
>  };
>  
> + {
> + status = "okay";
> +};
> +
>   {
>   status = "okay";
>  };
> 

M
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[PATCH v10 4/4] arm64: dts: zynqmp: zcu106-revA: Wire up the DisplayPort subsystem

[Laurent Pinchart]

Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to
the DisplayPort connector.

Signed-off-by: Laurent Pinchart 
---
 .../arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts 
b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
index 93ce7eb81498..4656f25b6b04 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -13,6 +13,7 @@
 #include "zynqmp-clk.dtsi"
 #include 
 #include 
+#include 
 
 / {
model = "ZynqMP ZCU106 RevA";
@@ -69,6 +70,17 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   phy-names = "dp-phy0", "dp-phy1";
+   phys = < PHY_TYPE_DP 0 3 2700>,
+  < PHY_TYPE_DP 1 3 2700>;
+};
+
 /* fpd_dma clk 667MHz, lpd_dma 500MHz */
 _dma_chan1 {
status = "okay";
@@ -503,6 +515,10 @@
no-1-8-v;
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 };
-- 
Regards,

Laurent Pinchart

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