On 13-06-22, 15:26, Bo-Chen Chen wrote:
> From: Markus Schneider-Pargmann
>
> This is a new driver that supports the integrated DisplayPort phy for
> mediatek SoCs, especially the mt8195. The phy is integrated into the
> DisplayPort controller and will be created by the mtk-dp driver. This
> driver expects a struct regmap to be able to work on the same registers
> as the DisplayPort controller. It sets the device data to be the struct
> phy so that the DisplayPort controller can easily work with it.
>
> The driver does not have any devicetree bindings because the datasheet
> does not list the controller and the phy as distinct units.
>
> The interaction with the controller can be covered by the configure
> callback of the phy framework and its displayport parameters.
>
> Signed-off-by: Markus Schneider-Pargmann
> Signed-off-by: Guillaume Ranquet
> [Bo-Chen: Modify reviewers' comments.]
> Signed-off-by: Bo-Chen Chen
> ---
> MAINTAINERS | 1 +
> drivers/phy/mediatek/Kconfig | 8 ++
> drivers/phy/mediatek/Makefile | 1 +
> drivers/phy/mediatek/phy-mtk-dp.c | 202 ++
> 4 files changed, 212 insertions(+)
> create mode 100644 drivers/phy/mediatek/phy-mtk-dp.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a6d3bd9d2a8d..f1460ee9ce83 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -6698,6 +6698,7 @@ L: linux-media...@lists.infradead.org (moderated
> for non-subscribers)
> S: Supported
> F: Documentation/devicetree/bindings/display/mediatek/
> F: drivers/gpu/drm/mediatek/
> +F: drivers/phy/mediatek/phy-mtk-dp.c
> F: drivers/phy/mediatek/phy-mtk-hdmi*
> F: drivers/phy/mediatek/phy-mtk-mipi*
>
> diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
> index 55f8e6c048ab..d631525d12e1 100644
> --- a/drivers/phy/mediatek/Kconfig
> +++ b/drivers/phy/mediatek/Kconfig
> @@ -55,3 +55,11 @@ config PHY_MTK_MIPI_DSI
> select GENERIC_PHY
> help
> Support MIPI DSI for Mediatek SoCs.
> +
> +config PHY_MTK_DP
> + tristate "MediaTek DP-PHY Driver"
> + depends on ARCH_MEDIATEK || COMPILE_TEST
> + depends on OF
> + select GENERIC_PHY
> + help
> + Support DisplayPort PHY for MediaTek SoCs.
> diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
> index ace660fbed3a..4ba1e0650434 100644
> --- a/drivers/phy/mediatek/Makefile
> +++ b/drivers/phy/mediatek/Makefile
> @@ -3,6 +3,7 @@
> # Makefile for the phy drivers.
> #
>
> +obj-$(CONFIG_PHY_MTK_DP) += phy-mtk-dp.o
> obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
> obj-$(CONFIG_PHY_MTK_UFS)+= phy-mtk-ufs.o
> obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
> diff --git a/drivers/phy/mediatek/phy-mtk-dp.c
> b/drivers/phy/mediatek/phy-mtk-dp.c
> new file mode 100644
> index ..c4d5ca1719a4
> --- /dev/null
> +++ b/drivers/phy/mediatek/phy-mtk-dp.c
> @@ -0,0 +1,202 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * MediaTek DisplayPort PHY driver
> + *
> + * Copyright (c) 2022 BayLibre
> + * Copyright (c) 2022 MediaTek
It should be proper name of companies (hint see other uses)
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define PHY_OFFSET 0x1000
> +
> +#define MTK_DP_PHY_DIG_PLL_CTL_1 (PHY_OFFSET + 0x14)
> +#define TPLL_SSC_EN BIT(3)
> +
> +#define MTK_DP_PHY_DIG_BIT_RATE (PHY_OFFSET + 0x3C)
> +#define BIT_RATE_RBR 0
> +#define BIT_RATE_HBR 1
> +#define BIT_RATE_HBR22
> +#define BIT_RATE_HBR33
> +
> +#define MTK_DP_PHY_DIG_SW_RST(PHY_OFFSET + 0x38)
> +#define DP_GLB_SW_RST_PHYD BIT(0)
> +
> +#define MTK_DP_LANE0_DRIVING_PARAM_3 (PHY_OFFSET + 0x138)
> +#define MTK_DP_LANE1_DRIVING_PARAM_3 (PHY_OFFSET + 0x238)
> +#define MTK_DP_LANE2_DRIVING_PARAM_3 (PHY_OFFSET + 0x338)
> +#define MTK_DP_LANE3_DRIVING_PARAM_3 (PHY_OFFSET + 0x438)
> +#define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULTBIT(4)
> +#define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT(BIT(10) | BIT(12))
> +#define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULTGENMASK(20, 19)
> +#define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULTGENMASK(29, 29)
> +#define DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \
> + XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \
> + XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \
> + XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT)
> +
> +#define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULTGENMASK(4, 3)
> +#define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULTGENMASK(12, 9)
> +#define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT(BIT(18) | BIT(21))
> +#define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULTGENMASK(29, 29)
> +#define DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT |