Re: [PATCH v11 5/7] dt-bindings: display: Add Loongson display controller
On Tue, Mar 29, 2022 at 10:02:11AM +0800, Sui Jingfeng wrote: > > On 2022/3/28 22:04, Rob Herring wrote: > > On Sat, Mar 26, 2022 at 06:04:46PM +0800, Sui Jingfeng wrote: > > > On 2022/3/24 21:26, Rob Herring wrote: > > > > On Thu, Mar 24, 2022 at 09:48:19AM +0800, Sui Jingfeng wrote: > > > > > On 2022/3/23 21:03, Rob Herring wrote: > > > > > > On Wed, Mar 23, 2022 at 11:38:55AM +0800, Sui Jingfeng wrote: > > > > > > > On 2022/3/23 04:55, Rob Herring wrote: > > > > > > > > On Tue, Mar 22, 2022 at 10:33:45AM +0800, Sui Jingfeng wrote: > > > > > > > > > On 2022/3/22 07:20, Rob Herring wrote: > > > > > > > > > > On Tue, Mar 22, 2022 at 12:29:14AM +0800, Sui Jingfeng > > > > > > > > > > wrote: > > > > > > > > > > > From: suijingfeng > > > > > > > > > > > > > > > > > > > > > Needs a commit message. > > > > > > > > > > > > > > > > > > > > > Signed-off-by: suijingfeng > > > > > > > > > > > Signed-off-by: Sui Jingfeng <15330273...@189.cn> > > > > > > > > > > Same person? Don't need both emails. > > > > > > > > > Yes, suijingf...@loongson.cn is my company's email. But it > > > > > > > > > can not be used > > > > > > > > > to send patches to dri-devel, > > > > > > > > > > > > > > > > > > when send patches with this email, the patch will not be > > > > > > > > > shown on patch > > > > > > > > > works. > > > > > > > > > > > > > > > > > > Emails are either blocked or got rejected by loongson's > > > > > > > > > mail server. It > > > > > > > > > can only receive emails > > > > > > > > > > > > > > > > > > from you and other people, but not dri-devel. so have to use > > > > > > > > > my personal > > > > > > > > > email(15330273...@189.cn) to send patches. > > > > > > > > > > > > > > > > > > > > --- > > > > > > > > > > > .../loongson/loongson,display-controller.yaml | 230 > > > > > > > > > > > ++ > > > > > > > > > > > 1 file changed, 230 insertions(+) > > > > > > > > > > > create mode 100644 > > > > > > > > > > > Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > > > > > > > > > > > > > > > > > > diff --git > > > > > > > > > > > a/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > > > > > > > > > > > > > > > > > > b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > > > > > > > new file mode 100644 > > > > > > > > > > > index ..7be63346289e > > > > > > > > > > > --- /dev/null > > > > > > > > > > > +++ > > > > > > > > > > > b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > > > > > > > @@ -0,0 +1,230 @@ > > > > > > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > > > > > > > > +%YAML 1.2 > > > > > > > > > > > +--- > > > > > > > > > > > +$id: > > > > > > > > > > > http://devicetree.org/schemas/display/loongson/loongson,display-controller.yaml# > > > > > > > > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > > > > > > > > + > > > > > > > > > > > +title: Loongson LS7A1000/LS2K1000/LS2K0500 Display > > > > > > > > > > > Controller Device Tree Bindings > > > > > > > > > > > + > > > > > > > > > > > +maintainers: > > > > > > > > > > > + - Sui Jingfeng > > > > > > > > > > > + > > > > > > > > > > > +description: |+ > > > > > > > > > > > + > > > > > > > > > > > + Loongson display controllers are simple which require > > > > > > > > > > > scanout buffers > > > > > > > > > > > + to be physically contiguous. LS2K1000/LS2K0500 is a > > > > > > > > > > > SOC, only system > > > > > > > > > > > + memory is available. LS7A1000/LS7A2000 is bridge chip > > > > > > > > > > > which is equipped > > > > > > > > > > > + with a dedicated video RAM which is 64MB or more, > > > > > > > > > > > precise size can be > > > > > > > > > > > + read from the PCI BAR 2 of the GPU > > > > > > > > > > > device(0x0014:0x7A15) in the bridge > > > > > > > > > > > + chip. > > > > > > > > > > > + > > > > > > > > > > > + LSDC has two display pipes, each way has a DVO > > > > > > > > > > > interface which provide > > > > > > > > > > > + RGB888 signals, vertical & horizontal > > > > > > > > > > > synchronisations, data enable and > > > > > > > > > > > + the pixel clock. LSDC has two CRTC, each CRTC is able > > > > > > > > > > > to scanout from > > > > > > > > > > > + 1920x1080 resolution at 60Hz. Each CRTC has two FB > > > > > > > > > > > address registers. > > > > > > > > > > > + > > > > > > > > > > > + For LS7A1000, there are 4 dedicated GPIOs whose > > > > > > > > > > > control register is > > > > > > > > > > > + located at the DC register space. They are used to > > > > > > > > > > > emulate two way i2c, > > > > > > > > > > > + One for DVO0, another for DVO1. > > > > > > > > > > > + > > > > > > > > > > > + LS2K1000 and LS2K0500 SoC grab i2c adapter from other > > > > > > > > > > > module, either > > > > > > > > > > > + general purpose GPIO
Re: [PATCH v11 5/7] dt-bindings: display: Add Loongson display controller
On 2022/3/28 22:04, Rob Herring wrote: On Sat, Mar 26, 2022 at 06:04:46PM +0800, Sui Jingfeng wrote: On 2022/3/24 21:26, Rob Herring wrote: On Thu, Mar 24, 2022 at 09:48:19AM +0800, Sui Jingfeng wrote: On 2022/3/23 21:03, Rob Herring wrote: On Wed, Mar 23, 2022 at 11:38:55AM +0800, Sui Jingfeng wrote: On 2022/3/23 04:55, Rob Herring wrote: On Tue, Mar 22, 2022 at 10:33:45AM +0800, Sui Jingfeng wrote: On 2022/3/22 07:20, Rob Herring wrote: On Tue, Mar 22, 2022 at 12:29:14AM +0800, Sui Jingfeng wrote: From: suijingfeng Needs a commit message. Signed-off-by: suijingfeng Signed-off-by: Sui Jingfeng <15330273...@189.cn> Same person? Don't need both emails. Yes, suijingf...@loongson.cn is my company's email. But it can not be used to send patches to dri-devel, when send patches with this email, the patch will not be shown on patch works. Emails are either blocked or got rejected by loongson's mail server. It can only receive emails from you and other people, but not dri-devel. so have to use my personal email(15330273...@189.cn) to send patches. --- .../loongson/loongson,display-controller.yaml | 230 ++ 1 file changed, 230 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml diff --git a/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml new file mode 100644 index ..7be63346289e --- /dev/null +++ b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml @@ -0,0 +1,230 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/loongson/loongson,display-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson LS7A1000/LS2K1000/LS2K0500 Display Controller Device Tree Bindings + +maintainers: + - Sui Jingfeng + +description: |+ + + Loongson display controllers are simple which require scanout buffers + to be physically contiguous. LS2K1000/LS2K0500 is a SOC, only system + memory is available. LS7A1000/LS7A2000 is bridge chip which is equipped + with a dedicated video RAM which is 64MB or more, precise size can be + read from the PCI BAR 2 of the GPU device(0x0014:0x7A15) in the bridge + chip. + + LSDC has two display pipes, each way has a DVO interface which provide + RGB888 signals, vertical & horizontal synchronisations, data enable and + the pixel clock. LSDC has two CRTC, each CRTC is able to scanout from + 1920x1080 resolution at 60Hz. Each CRTC has two FB address registers. + + For LS7A1000, there are 4 dedicated GPIOs whose control register is + located at the DC register space. They are used to emulate two way i2c, + One for DVO0, another for DVO1. + + LS2K1000 and LS2K0500 SoC grab i2c adapter from other module, either + general purpose GPIO emulated i2c or hardware i2c in the SoC. + + LSDC's display pipeline have several components as below description, + + The display controller in LS7A1000: + ___ _ +|---| | | +| CRTC0 --> | DVO0 > Encoder0 ---> Connector0 ---> | Monitor | +| _ _ ---|^ ^|_| +| | | | |---|| | +| |_| |_|| i2c0 <+-+ +|---| +| DC IN LS7A1000 | +| _ _ ---| +| | | | || i2c1 <+-+ +| |_| |_|---|| | _ +|---|| || | +| CRTC1 --> | DVO1 > Encoder1 ---> Connector1 ---> | Panel | +|---| |_| +|___| + + Simple usage of LS7A1000 with LS3A4000 CPU: + ++--++---+ +| DDR4 || +---+| ++--+| | PCIe Root complex | LS7A1000 | + || MC0 | +--++-+++| + +--+ HT 3.0 | || || | + | LS3A4000 |<>| +---++---+ +--++--++-+ +--+ + | CPU|<>| | GC1000 | | LSDC |<-->| DDR3 MC |<->| VRAM | + +--+ | ++ +-+--+-++-+ +--+ + || MC1 +---|--|+ ++--+| | +| DDR4 | +---+ DVO0 | | DVO1 +--+ ++--+ VGA <--|ADV7125|<+ +>|TFP410|--> DVI/HDMI + +---+ +--+ + + The display controller in LS2K1000/LS2K0500: + ___
Re: [PATCH v11 5/7] dt-bindings: display: Add Loongson display controller
On Sat, Mar 26, 2022 at 06:04:46PM +0800, Sui Jingfeng wrote: > > On 2022/3/24 21:26, Rob Herring wrote: > > On Thu, Mar 24, 2022 at 09:48:19AM +0800, Sui Jingfeng wrote: > > > On 2022/3/23 21:03, Rob Herring wrote: > > > > On Wed, Mar 23, 2022 at 11:38:55AM +0800, Sui Jingfeng wrote: > > > > > On 2022/3/23 04:55, Rob Herring wrote: > > > > > > On Tue, Mar 22, 2022 at 10:33:45AM +0800, Sui Jingfeng wrote: > > > > > > > On 2022/3/22 07:20, Rob Herring wrote: > > > > > > > > On Tue, Mar 22, 2022 at 12:29:14AM +0800, Sui Jingfeng wrote: > > > > > > > > > From: suijingfeng > > > > > > > > > > > > > > > > > Needs a commit message. > > > > > > > > > > > > > > > > > Signed-off-by: suijingfeng > > > > > > > > > Signed-off-by: Sui Jingfeng <15330273...@189.cn> > > > > > > > > Same person? Don't need both emails. > > > > > > > Yes, suijingf...@loongson.cn is my company's email. But it can > > > > > > > not be used > > > > > > > to send patches to dri-devel, > > > > > > > > > > > > > > when send patches with this email, the patch will not be shown on > > > > > > > patch > > > > > > > works. > > > > > > > > > > > > > > Emails are either blocked or got rejected by loongson's mail > > > > > > > server. It > > > > > > > can only receive emails > > > > > > > > > > > > > > from you and other people, but not dri-devel. so have to use my > > > > > > > personal > > > > > > > email(15330273...@189.cn) to send patches. > > > > > > > > > > > > > > > > --- > > > > > > > > > .../loongson/loongson,display-controller.yaml | 230 > > > > > > > > > ++ > > > > > > > > > 1 file changed, 230 insertions(+) > > > > > > > > > create mode 100644 > > > > > > > > > Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > > > > > > > > > > > > > > diff --git > > > > > > > > > a/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > > > > > > > > > > > > > > b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > > > > > new file mode 100644 > > > > > > > > > index ..7be63346289e > > > > > > > > > --- /dev/null > > > > > > > > > +++ > > > > > > > > > b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > > > > > @@ -0,0 +1,230 @@ > > > > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > > > > > > +%YAML 1.2 > > > > > > > > > +--- > > > > > > > > > +$id: > > > > > > > > > http://devicetree.org/schemas/display/loongson/loongson,display-controller.yaml# > > > > > > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > > > > > > + > > > > > > > > > +title: Loongson LS7A1000/LS2K1000/LS2K0500 Display > > > > > > > > > Controller Device Tree Bindings > > > > > > > > > + > > > > > > > > > +maintainers: > > > > > > > > > + - Sui Jingfeng > > > > > > > > > + > > > > > > > > > +description: |+ > > > > > > > > > + > > > > > > > > > + Loongson display controllers are simple which require > > > > > > > > > scanout buffers > > > > > > > > > + to be physically contiguous. LS2K1000/LS2K0500 is a SOC, > > > > > > > > > only system > > > > > > > > > + memory is available. LS7A1000/LS7A2000 is bridge chip > > > > > > > > > which is equipped > > > > > > > > > + with a dedicated video RAM which is 64MB or more, precise > > > > > > > > > size can be > > > > > > > > > + read from the PCI BAR 2 of the GPU device(0x0014:0x7A15) > > > > > > > > > in the bridge > > > > > > > > > + chip. > > > > > > > > > + > > > > > > > > > + LSDC has two display pipes, each way has a DVO interface > > > > > > > > > which provide > > > > > > > > > + RGB888 signals, vertical & horizontal synchronisations, > > > > > > > > > data enable and > > > > > > > > > + the pixel clock. LSDC has two CRTC, each CRTC is able to > > > > > > > > > scanout from > > > > > > > > > + 1920x1080 resolution at 60Hz. Each CRTC has two FB address > > > > > > > > > registers. > > > > > > > > > + > > > > > > > > > + For LS7A1000, there are 4 dedicated GPIOs whose control > > > > > > > > > register is > > > > > > > > > + located at the DC register space. They are used to emulate > > > > > > > > > two way i2c, > > > > > > > > > + One for DVO0, another for DVO1. > > > > > > > > > + > > > > > > > > > + LS2K1000 and LS2K0500 SoC grab i2c adapter from other > > > > > > > > > module, either > > > > > > > > > + general purpose GPIO emulated i2c or hardware i2c in the > > > > > > > > > SoC. > > > > > > > > > + > > > > > > > > > + LSDC's display pipeline have several components as below > > > > > > > > > description, > > > > > > > > > + > > > > > > > > > + The display controller in LS7A1000: > > > > > > > > > + ___ > > > > > > > > > _ > > > > > > > > > +|---| > > > > > > > > > | | > > > > > > > > > +
Re: [PATCH v11 5/7] dt-bindings: display: Add Loongson display controller
On 2022/3/24 21:26, Rob Herring wrote: On Thu, Mar 24, 2022 at 09:48:19AM +0800, Sui Jingfeng wrote: On 2022/3/23 21:03, Rob Herring wrote: On Wed, Mar 23, 2022 at 11:38:55AM +0800, Sui Jingfeng wrote: On 2022/3/23 04:55, Rob Herring wrote: On Tue, Mar 22, 2022 at 10:33:45AM +0800, Sui Jingfeng wrote: On 2022/3/22 07:20, Rob Herring wrote: On Tue, Mar 22, 2022 at 12:29:14AM +0800, Sui Jingfeng wrote: From: suijingfeng Needs a commit message. Signed-off-by: suijingfeng Signed-off-by: Sui Jingfeng <15330273...@189.cn> Same person? Don't need both emails. Yes, suijingf...@loongson.cn is my company's email. But it can not be used to send patches to dri-devel, when send patches with this email, the patch will not be shown on patch works. Emails are either blocked or got rejected by loongson's mail server. It can only receive emails from you and other people, but not dri-devel. so have to use my personal email(15330273...@189.cn) to send patches. --- .../loongson/loongson,display-controller.yaml | 230 ++ 1 file changed, 230 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml diff --git a/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml new file mode 100644 index ..7be63346289e --- /dev/null +++ b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml @@ -0,0 +1,230 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/loongson/loongson,display-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson LS7A1000/LS2K1000/LS2K0500 Display Controller Device Tree Bindings + +maintainers: + - Sui Jingfeng + +description: |+ + + Loongson display controllers are simple which require scanout buffers + to be physically contiguous. LS2K1000/LS2K0500 is a SOC, only system + memory is available. LS7A1000/LS7A2000 is bridge chip which is equipped + with a dedicated video RAM which is 64MB or more, precise size can be + read from the PCI BAR 2 of the GPU device(0x0014:0x7A15) in the bridge + chip. + + LSDC has two display pipes, each way has a DVO interface which provide + RGB888 signals, vertical & horizontal synchronisations, data enable and + the pixel clock. LSDC has two CRTC, each CRTC is able to scanout from + 1920x1080 resolution at 60Hz. Each CRTC has two FB address registers. + + For LS7A1000, there are 4 dedicated GPIOs whose control register is + located at the DC register space. They are used to emulate two way i2c, + One for DVO0, another for DVO1. + + LS2K1000 and LS2K0500 SoC grab i2c adapter from other module, either + general purpose GPIO emulated i2c or hardware i2c in the SoC. + + LSDC's display pipeline have several components as below description, + + The display controller in LS7A1000: + ___ _ +|---| | | +| CRTC0 --> | DVO0 > Encoder0 ---> Connector0 ---> | Monitor | +| _ _ ---|^ ^|_| +| | | | |---|| | +| |_| |_|| i2c0 <+-+ +|---| +| DC IN LS7A1000 | +| _ _ ---| +| | | | || i2c1 <+-+ +| |_| |_|---|| | _ +|---|| || | +| CRTC1 --> | DVO1 > Encoder1 ---> Connector1 ---> | Panel | +|---| |_| +|___| + + Simple usage of LS7A1000 with LS3A4000 CPU: + ++--++---+ +| DDR4 || +---+| ++--+| | PCIe Root complex | LS7A1000 | + || MC0 | +--++-+++| + +--+ HT 3.0 | || || | + | LS3A4000 |<>| +---++---+ +--++--++-+ +--+ + | CPU|<>| | GC1000 | | LSDC |<-->| DDR3 MC |<->| VRAM | + +--+ | ++ +-+--+-++-+ +--+ + || MC1 +---|--|+ ++--+| | +| DDR4 | +---+ DVO0 | | DVO1 +--+ ++--+ VGA <--|ADV7125|<+ +>|TFP410|--> DVI/HDMI + +---+ +--+ + + The display controller in LS2K1000/LS2K0500: + ___ _ +|---| | | +| CRTC0
Re: [PATCH v11 5/7] dt-bindings: display: Add Loongson display controller
On Thu, Mar 24, 2022 at 09:48:19AM +0800, Sui Jingfeng wrote: > > On 2022/3/23 21:03, Rob Herring wrote: > > On Wed, Mar 23, 2022 at 11:38:55AM +0800, Sui Jingfeng wrote: > > > On 2022/3/23 04:55, Rob Herring wrote: > > > > On Tue, Mar 22, 2022 at 10:33:45AM +0800, Sui Jingfeng wrote: > > > > > On 2022/3/22 07:20, Rob Herring wrote: > > > > > > On Tue, Mar 22, 2022 at 12:29:14AM +0800, Sui Jingfeng wrote: > > > > > > > From: suijingfeng > > > > > > > > > > > > > Needs a commit message. > > > > > > > > > > > > > Signed-off-by: suijingfeng > > > > > > > Signed-off-by: Sui Jingfeng <15330273...@189.cn> > > > > > > Same person? Don't need both emails. > > > > > Yes, suijingf...@loongson.cn is my company's email. But it can not > > > > > be used > > > > > to send patches to dri-devel, > > > > > > > > > > when send patches with this email, the patch will not be shown on > > > > > patch > > > > > works. > > > > > > > > > > Emails are either blocked or got rejected by loongson's mail > > > > > server. It > > > > > can only receive emails > > > > > > > > > > from you and other people, but not dri-devel. so have to use my > > > > > personal > > > > > email(15330273...@189.cn) to send patches. > > > > > > > > > > > > --- > > > > > > > .../loongson/loongson,display-controller.yaml | 230 > > > > > > > ++ > > > > > > > 1 file changed, 230 insertions(+) > > > > > > > create mode 100644 > > > > > > > Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > > > > > > > > > > diff --git > > > > > > > a/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > > > > > > > > > > b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > > > new file mode 100644 > > > > > > > index ..7be63346289e > > > > > > > --- /dev/null > > > > > > > +++ > > > > > > > b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > > > @@ -0,0 +1,230 @@ > > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > > > > +%YAML 1.2 > > > > > > > +--- > > > > > > > +$id: > > > > > > > http://devicetree.org/schemas/display/loongson/loongson,display-controller.yaml# > > > > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > > > > + > > > > > > > +title: Loongson LS7A1000/LS2K1000/LS2K0500 Display Controller > > > > > > > Device Tree Bindings > > > > > > > + > > > > > > > +maintainers: > > > > > > > + - Sui Jingfeng > > > > > > > + > > > > > > > +description: |+ > > > > > > > + > > > > > > > + Loongson display controllers are simple which require scanout > > > > > > > buffers > > > > > > > + to be physically contiguous. LS2K1000/LS2K0500 is a SOC, only > > > > > > > system > > > > > > > + memory is available. LS7A1000/LS7A2000 is bridge chip which is > > > > > > > equipped > > > > > > > + with a dedicated video RAM which is 64MB or more, precise size > > > > > > > can be > > > > > > > + read from the PCI BAR 2 of the GPU device(0x0014:0x7A15) in > > > > > > > the bridge > > > > > > > + chip. > > > > > > > + > > > > > > > + LSDC has two display pipes, each way has a DVO interface which > > > > > > > provide > > > > > > > + RGB888 signals, vertical & horizontal synchronisations, data > > > > > > > enable and > > > > > > > + the pixel clock. LSDC has two CRTC, each CRTC is able to > > > > > > > scanout from > > > > > > > + 1920x1080 resolution at 60Hz. Each CRTC has two FB address > > > > > > > registers. > > > > > > > + > > > > > > > + For LS7A1000, there are 4 dedicated GPIOs whose control > > > > > > > register is > > > > > > > + located at the DC register space. They are used to emulate two > > > > > > > way i2c, > > > > > > > + One for DVO0, another for DVO1. > > > > > > > + > > > > > > > + LS2K1000 and LS2K0500 SoC grab i2c adapter from other module, > > > > > > > either > > > > > > > + general purpose GPIO emulated i2c or hardware i2c in the SoC. > > > > > > > + > > > > > > > + LSDC's display pipeline have several components as below > > > > > > > description, > > > > > > > + > > > > > > > + The display controller in LS7A1000: > > > > > > > + ___ > > > > > > > _ > > > > > > > +|---| | > > > > > > > | > > > > > > > +| CRTC0 --> | DVO0 > Encoder0 ---> Connector0 ---> | > > > > > > > Monitor | > > > > > > > +| _ _ ---|^ ^ > > > > > > > |_| > > > > > > > +| | | | |---|| | > > > > > > > +| |_| |_|| i2c0 <+-+ > > > > > > > +|---| > > > > > > > +| DC IN LS7A1000 | > > > > > > > +| _ _ ---| > > > > > > > +| | | | || i2c1 <+-+ > > > > > > > +| |_| |_|
Re: [PATCH v11 5/7] dt-bindings: display: Add Loongson display controller
On 2022/3/23 21:03, Rob Herring wrote: On Wed, Mar 23, 2022 at 11:38:55AM +0800, Sui Jingfeng wrote: On 2022/3/23 04:55, Rob Herring wrote: On Tue, Mar 22, 2022 at 10:33:45AM +0800, Sui Jingfeng wrote: On 2022/3/22 07:20, Rob Herring wrote: On Tue, Mar 22, 2022 at 12:29:14AM +0800, Sui Jingfeng wrote: From: suijingfeng Needs a commit message. Signed-off-by: suijingfeng Signed-off-by: Sui Jingfeng <15330273...@189.cn> Same person? Don't need both emails. Yes, suijingf...@loongson.cn is my company's email. But it can not be used to send patches to dri-devel, when send patches with this email, the patch will not be shown on patch works. Emails are either blocked or got rejected by loongson's mail server. It can only receive emails from you and other people, but not dri-devel. so have to use my personal email(15330273...@189.cn) to send patches. --- .../loongson/loongson,display-controller.yaml | 230 ++ 1 file changed, 230 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml diff --git a/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml new file mode 100644 index ..7be63346289e --- /dev/null +++ b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml @@ -0,0 +1,230 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/loongson/loongson,display-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson LS7A1000/LS2K1000/LS2K0500 Display Controller Device Tree Bindings + +maintainers: + - Sui Jingfeng + +description: |+ + + Loongson display controllers are simple which require scanout buffers + to be physically contiguous. LS2K1000/LS2K0500 is a SOC, only system + memory is available. LS7A1000/LS7A2000 is bridge chip which is equipped + with a dedicated video RAM which is 64MB or more, precise size can be + read from the PCI BAR 2 of the GPU device(0x0014:0x7A15) in the bridge + chip. + + LSDC has two display pipes, each way has a DVO interface which provide + RGB888 signals, vertical & horizontal synchronisations, data enable and + the pixel clock. LSDC has two CRTC, each CRTC is able to scanout from + 1920x1080 resolution at 60Hz. Each CRTC has two FB address registers. + + For LS7A1000, there are 4 dedicated GPIOs whose control register is + located at the DC register space. They are used to emulate two way i2c, + One for DVO0, another for DVO1. + + LS2K1000 and LS2K0500 SoC grab i2c adapter from other module, either + general purpose GPIO emulated i2c or hardware i2c in the SoC. + + LSDC's display pipeline have several components as below description, + + The display controller in LS7A1000: + ___ _ +|---| | | +| CRTC0 --> | DVO0 > Encoder0 ---> Connector0 ---> | Monitor | +| _ _ ---|^ ^|_| +| | | | |---|| | +| |_| |_|| i2c0 <+-+ +|---| +| DC IN LS7A1000 | +| _ _ ---| +| | | | || i2c1 <+-+ +| |_| |_|---|| | _ +|---|| || | +| CRTC1 --> | DVO1 > Encoder1 ---> Connector1 ---> | Panel | +|---| |_| +|___| + + Simple usage of LS7A1000 with LS3A4000 CPU: + ++--++---+ +| DDR4 || +---+| ++--+| | PCIe Root complex | LS7A1000 | + || MC0 | +--++-+++| + +--+ HT 3.0 | || || | + | LS3A4000 |<>| +---++---+ +--++--++-+ +--+ + | CPU|<>| | GC1000 | | LSDC |<-->| DDR3 MC |<->| VRAM | + +--+ | ++ +-+--+-++-+ +--+ + || MC1 +---|--|+ ++--+| | +| DDR4 | +---+ DVO0 | | DVO1 +--+ ++--+ VGA <--|ADV7125|<+ +>|TFP410|--> DVI/HDMI + +---+ +--+ + + The display controller in LS2K1000/LS2K0500: + ___ _ +|---| | | +| CRTC0 --> | DVO0 > Encoder0 ---> Connector0 ---> | Monitor | +| _ _ ---|^
Re: [PATCH v11 5/7] dt-bindings: display: Add Loongson display controller
On Wed, Mar 23, 2022 at 11:38:55AM +0800, Sui Jingfeng wrote: > > On 2022/3/23 04:55, Rob Herring wrote: > > On Tue, Mar 22, 2022 at 10:33:45AM +0800, Sui Jingfeng wrote: > > > On 2022/3/22 07:20, Rob Herring wrote: > > > > On Tue, Mar 22, 2022 at 12:29:14AM +0800, Sui Jingfeng wrote: > > > > > From: suijingfeng > > > > > > > > > Needs a commit message. > > > > > > > > > Signed-off-by: suijingfeng > > > > > Signed-off-by: Sui Jingfeng <15330273...@189.cn> > > > > Same person? Don't need both emails. > > > Yes, suijingf...@loongson.cn is my company's email. But it can not be > > > used > > > to send patches to dri-devel, > > > > > > when send patches with this email, the patch will not be shown on patch > > > works. > > > > > > Emails are either blocked or got rejected by loongson's mail server. > > > It > > > can only receive emails > > > > > > from you and other people, but not dri-devel. so have to use my personal > > > email(15330273...@189.cn) to send patches. > > > > > > > > --- > > > > >.../loongson/loongson,display-controller.yaml | 230 > > > > > ++ > > > > >1 file changed, 230 insertions(+) > > > > >create mode 100644 > > > > > Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > > > > > > diff --git > > > > > a/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > > > > > > b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > new file mode 100644 > > > > > index ..7be63346289e > > > > > --- /dev/null > > > > > +++ > > > > > b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > @@ -0,0 +1,230 @@ > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > > +%YAML 1.2 > > > > > +--- > > > > > +$id: > > > > > http://devicetree.org/schemas/display/loongson/loongson,display-controller.yaml# > > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > > + > > > > > +title: Loongson LS7A1000/LS2K1000/LS2K0500 Display Controller Device > > > > > Tree Bindings > > > > > + > > > > > +maintainers: > > > > > + - Sui Jingfeng > > > > > + > > > > > +description: |+ > > > > > + > > > > > + Loongson display controllers are simple which require scanout > > > > > buffers > > > > > + to be physically contiguous. LS2K1000/LS2K0500 is a SOC, only > > > > > system > > > > > + memory is available. LS7A1000/LS7A2000 is bridge chip which is > > > > > equipped > > > > > + with a dedicated video RAM which is 64MB or more, precise size can > > > > > be > > > > > + read from the PCI BAR 2 of the GPU device(0x0014:0x7A15) in the > > > > > bridge > > > > > + chip. > > > > > + > > > > > + LSDC has two display pipes, each way has a DVO interface which > > > > > provide > > > > > + RGB888 signals, vertical & horizontal synchronisations, data > > > > > enable and > > > > > + the pixel clock. LSDC has two CRTC, each CRTC is able to scanout > > > > > from > > > > > + 1920x1080 resolution at 60Hz. Each CRTC has two FB address > > > > > registers. > > > > > + > > > > > + For LS7A1000, there are 4 dedicated GPIOs whose control register is > > > > > + located at the DC register space. They are used to emulate two way > > > > > i2c, > > > > > + One for DVO0, another for DVO1. > > > > > + > > > > > + LS2K1000 and LS2K0500 SoC grab i2c adapter from other module, > > > > > either > > > > > + general purpose GPIO emulated i2c or hardware i2c in the SoC. > > > > > + > > > > > + LSDC's display pipeline have several components as below > > > > > description, > > > > > + > > > > > + The display controller in LS7A1000: > > > > > + ___ > > > > > _ > > > > > +|---| | > > > > > | > > > > > +| CRTC0 --> | DVO0 > Encoder0 ---> Connector0 ---> | > > > > > Monitor | > > > > > +| _ _ ---|^ ^ > > > > > |_| > > > > > +| | | | |---|| | > > > > > +| |_| |_|| i2c0 <+-+ > > > > > +|---| > > > > > +| DC IN LS7A1000 | > > > > > +| _ _ ---| > > > > > +| | | | || i2c1 <+-+ > > > > > +| |_| |_|---|| | > > > > > _ > > > > > +|---|| || > > > > > | > > > > > +| CRTC1 --> | DVO1 > Encoder1 ---> Connector1 ---> | Panel > > > > > | > > > > > +|---| > > > > > |_| > > > > > +|___| > > > > > + > > > > > + Simple usage of LS7A1000 with LS3A4000 CPU: > > > > > + > > > > > ++--++---+ > > > > > +| DDR4 |
Re: [PATCH v11 5/7] dt-bindings: display: Add Loongson display controller
On 2022/3/23 04:55, Rob Herring wrote: On Tue, Mar 22, 2022 at 10:33:45AM +0800, Sui Jingfeng wrote: On 2022/3/22 07:20, Rob Herring wrote: On Tue, Mar 22, 2022 at 12:29:14AM +0800, Sui Jingfeng wrote: From: suijingfeng Needs a commit message. Signed-off-by: suijingfeng Signed-off-by: Sui Jingfeng <15330273...@189.cn> Same person? Don't need both emails. Yes, suijingf...@loongson.cn is my company's email. But it can not be used to send patches to dri-devel, when send patches with this email, the patch will not be shown on patch works. Emails are either blocked or got rejected by loongson's mail server. It can only receive emails from you and other people, but not dri-devel. so have to use my personal email(15330273...@189.cn) to send patches. --- .../loongson/loongson,display-controller.yaml | 230 ++ 1 file changed, 230 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml diff --git a/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml new file mode 100644 index ..7be63346289e --- /dev/null +++ b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml @@ -0,0 +1,230 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/loongson/loongson,display-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson LS7A1000/LS2K1000/LS2K0500 Display Controller Device Tree Bindings + +maintainers: + - Sui Jingfeng + +description: |+ + + Loongson display controllers are simple which require scanout buffers + to be physically contiguous. LS2K1000/LS2K0500 is a SOC, only system + memory is available. LS7A1000/LS7A2000 is bridge chip which is equipped + with a dedicated video RAM which is 64MB or more, precise size can be + read from the PCI BAR 2 of the GPU device(0x0014:0x7A15) in the bridge + chip. + + LSDC has two display pipes, each way has a DVO interface which provide + RGB888 signals, vertical & horizontal synchronisations, data enable and + the pixel clock. LSDC has two CRTC, each CRTC is able to scanout from + 1920x1080 resolution at 60Hz. Each CRTC has two FB address registers. + + For LS7A1000, there are 4 dedicated GPIOs whose control register is + located at the DC register space. They are used to emulate two way i2c, + One for DVO0, another for DVO1. + + LS2K1000 and LS2K0500 SoC grab i2c adapter from other module, either + general purpose GPIO emulated i2c or hardware i2c in the SoC. + + LSDC's display pipeline have several components as below description, + + The display controller in LS7A1000: + ___ _ +|---| | | +| CRTC0 --> | DVO0 > Encoder0 ---> Connector0 ---> | Monitor | +| _ _ ---|^ ^|_| +| | | | |---|| | +| |_| |_|| i2c0 <+-+ +|---| +| DC IN LS7A1000 | +| _ _ ---| +| | | | || i2c1 <+-+ +| |_| |_|---|| | _ +|---|| || | +| CRTC1 --> | DVO1 > Encoder1 ---> Connector1 ---> | Panel | +|---| |_| +|___| + + Simple usage of LS7A1000 with LS3A4000 CPU: + ++--++---+ +| DDR4 || +---+| ++--+| | PCIe Root complex | LS7A1000 | + || MC0 | +--++-+++| + +--+ HT 3.0 | || || | + | LS3A4000 |<>| +---++---+ +--++--++-+ +--+ + | CPU|<>| | GC1000 | | LSDC |<-->| DDR3 MC |<->| VRAM | + +--+ | ++ +-+--+-++-+ +--+ + || MC1 +---|--|+ ++--+| | +| DDR4 | +---+ DVO0 | | DVO1 +--+ ++--+ VGA <--|ADV7125|<+ +>|TFP410|--> DVI/HDMI + +---+ +--+ + + The display controller in LS2K1000/LS2K0500: + ___ _ +|---| | | +| CRTC0 --> | DVO0 > Encoder0 ---> Connector0 ---> | Monitor | +| _ _ ---|^ ^ |_| +| | | | | || | +| |_| |_| |
Re: [PATCH v11 5/7] dt-bindings: display: Add Loongson display controller
On Tue, Mar 22, 2022 at 10:33:45AM +0800, Sui Jingfeng wrote: > > On 2022/3/22 07:20, Rob Herring wrote: > > On Tue, Mar 22, 2022 at 12:29:14AM +0800, Sui Jingfeng wrote: > > > From: suijingfeng > > > > > Needs a commit message. > > > > > Signed-off-by: suijingfeng > > > Signed-off-by: Sui Jingfeng <15330273...@189.cn> > > Same person? Don't need both emails. > > Yes, suijingf...@loongson.cn is my company's email. But it can not be used > to send patches to dri-devel, > > when send patches with this email, the patch will not be shown on patch > works. > > Emails are either blocked or got rejected by loongson's mail server. It > can only receive emails > > from you and other people, but not dri-devel. so have to use my personal > email(15330273...@189.cn) to send patches. > > > > --- > > > .../loongson/loongson,display-controller.yaml | 230 ++ > > > 1 file changed, 230 insertions(+) > > > create mode 100644 > > > Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > > diff --git > > > a/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > > > > b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > new file mode 100644 > > > index ..7be63346289e > > > --- /dev/null > > > +++ > > > b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > > @@ -0,0 +1,230 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: > > > http://devicetree.org/schemas/display/loongson/loongson,display-controller.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Loongson LS7A1000/LS2K1000/LS2K0500 Display Controller Device > > > Tree Bindings > > > + > > > +maintainers: > > > + - Sui Jingfeng > > > + > > > +description: |+ > > > + > > > + Loongson display controllers are simple which require scanout buffers > > > + to be physically contiguous. LS2K1000/LS2K0500 is a SOC, only system > > > + memory is available. LS7A1000/LS7A2000 is bridge chip which is equipped > > > + with a dedicated video RAM which is 64MB or more, precise size can be > > > + read from the PCI BAR 2 of the GPU device(0x0014:0x7A15) in the bridge > > > + chip. > > > + > > > + LSDC has two display pipes, each way has a DVO interface which provide > > > + RGB888 signals, vertical & horizontal synchronisations, data enable and > > > + the pixel clock. LSDC has two CRTC, each CRTC is able to scanout from > > > + 1920x1080 resolution at 60Hz. Each CRTC has two FB address registers. > > > + > > > + For LS7A1000, there are 4 dedicated GPIOs whose control register is > > > + located at the DC register space. They are used to emulate two way i2c, > > > + One for DVO0, another for DVO1. > > > + > > > + LS2K1000 and LS2K0500 SoC grab i2c adapter from other module, either > > > + general purpose GPIO emulated i2c or hardware i2c in the SoC. > > > + > > > + LSDC's display pipeline have several components as below description, > > > + > > > + The display controller in LS7A1000: > > > + ___ _ > > > +|---| | | > > > +| CRTC0 --> | DVO0 > Encoder0 ---> Connector0 ---> | Monitor | > > > +| _ _ ---|^ ^|_| > > > +| | | | |---|| | > > > +| |_| |_|| i2c0 <+-+ > > > +|---| > > > +| DC IN LS7A1000 | > > > +| _ _ ---| > > > +| | | | || i2c1 <+-+ > > > +| |_| |_|---|| | _ > > > +|---|| || | > > > +| CRTC1 --> | DVO1 > Encoder1 ---> Connector1 ---> | Panel | > > > +|---| |_| > > > +|___| > > > + > > > + Simple usage of LS7A1000 with LS3A4000 CPU: > > > + > > > ++--++---+ > > > +| DDR4 || +---+| > > > ++--+| | PCIe Root complex | LS7A1000 | > > > + || MC0 | +--++-+++| > > > + +--+ HT 3.0 | || || | > > > + | LS3A4000 |<>| +---++---+ +--++--++-+ +--+ > > > + | CPU|<>| | GC1000 | | LSDC |<-->| DDR3 MC |<->| VRAM | > > > + +--+ | ++ +-+--+-++-+ +--+ > > > + || MC1 +---|--|+ > > > ++--+| | > > > +| DDR4 | +---+ DVO0 | | DVO1 +--+ > > > ++--+ VGA <--|ADV7125|<+
Re: [PATCH v11 5/7] dt-bindings: display: Add Loongson display controller
On Tue, Mar 22, 2022 at 09:54:08PM +0800, Sui Jingfeng wrote: > > On 2022/3/22 21:08, Jiaxun Yang wrote: > > > > > > 在 2022/3/22 2:33, Sui Jingfeng 写道: > > > > > > On 2022/3/22 07:20, Rob Herring wrote: > > > > On Tue, Mar 22, 2022 at 12:29:14AM +0800, Sui Jingfeng wrote: > > > > > From: suijingfeng > > > > > > > > > Needs a commit message. > > > > > > > > > Signed-off-by: suijingfeng > > > > > Signed-off-by: Sui Jingfeng <15330273...@189.cn> > > > > Same person? Don't need both emails. > > > > > > Yes, suijingf...@loongson.cn is my company's email. But it can not > > > be used to send patches to dri-devel, > > > > > > when send patches with this email, the patch will not be shown on > > > patch works. > > > > > > Emails are either blocked or got rejected by loongson's mail > > > server. It can only receive emails > > > > > > from you and other people, but not dri-devel. so have to use my > > > personal email(15330273...@189.cn) to send patches. > > In this case you can just use your company's email to sign-off > > code and sending with your personal email. It's common practice. > > > > If you don't want to receiving kernel email in your company mailbox, > > you can add a entry in .mailmap . > > > |I'm using `git send-email -7 --cover-letter --annotate -v11` command to > send patches, it will automatically sign off patches with the my private > emails. | I think that is only if you set your git config author to your private email. Pretty much anything git might automatically do can be turned off. Rob
Re: [PATCH v11 5/7] dt-bindings: display: Add Loongson display controller
在 2022/3/22 13:54, Sui Jingfeng 写道: On 2022/3/22 21:08, Jiaxun Yang wrote: 在 2022/3/22 2:33, Sui Jingfeng 写道: On 2022/3/22 07:20, Rob Herring wrote: On Tue, Mar 22, 2022 at 12:29:14AM +0800, Sui Jingfeng wrote: From: suijingfeng Needs a commit message. Signed-off-by: suijingfeng Signed-off-by: Sui Jingfeng <15330273...@189.cn> Same person? Don't need both emails. Yes, suijingf...@loongson.cn is my company's email. But it can not be used to send patches to dri-devel, when send patches with this email, the patch will not be shown on patch works. Emails are either blocked or got rejected by loongson's mail server. It can only receive emails from you and other people, but not dri-devel. so have to use my personal email(15330273...@189.cn) to send patches. In this case you can just use your company's email to sign-off code and sending with your personal email. It's common practice. If you don't want to receiving kernel email in your company mailbox, you can add a entry in .mailmap . |I'm using `git send-email -7 --cover-letter --annotate -v11` command to send patches, it will automatically sign off patches with the my private emails. | The alternative solution is: git format-patch -7 -v11 --cover-letter git send-email ./*.patch Thanks. - Jiaxun Thanks. - Jiaxun
Re: [PATCH v11 5/7] dt-bindings: display: Add Loongson display controller
On 2022/3/22 21:08, Jiaxun Yang wrote: 在 2022/3/22 2:33, Sui Jingfeng 写道: On 2022/3/22 07:20, Rob Herring wrote: On Tue, Mar 22, 2022 at 12:29:14AM +0800, Sui Jingfeng wrote: From: suijingfeng Needs a commit message. Signed-off-by: suijingfeng Signed-off-by: Sui Jingfeng <15330273...@189.cn> Same person? Don't need both emails. Yes, suijingf...@loongson.cn is my company's email. But it can not be used to send patches to dri-devel, when send patches with this email, the patch will not be shown on patch works. Emails are either blocked or got rejected by loongson's mail server. It can only receive emails from you and other people, but not dri-devel. so have to use my personal email(15330273...@189.cn) to send patches. In this case you can just use your company's email to sign-off code and sending with your personal email. It's common practice. If you don't want to receiving kernel email in your company mailbox, you can add a entry in .mailmap . |I'm using `git send-email -7 --cover-letter --annotate -v11` command to send patches, it will automatically sign off patches with the my private emails. | Thanks. - Jiaxun
Re: [PATCH v11 5/7] dt-bindings: display: Add Loongson display controller
在 2022/3/22 2:33, Sui Jingfeng 写道: On 2022/3/22 07:20, Rob Herring wrote: On Tue, Mar 22, 2022 at 12:29:14AM +0800, Sui Jingfeng wrote: From: suijingfeng Needs a commit message. Signed-off-by: suijingfeng Signed-off-by: Sui Jingfeng <15330273...@189.cn> Same person? Don't need both emails. Yes, suijingf...@loongson.cn is my company's email. But it can not be used to send patches to dri-devel, when send patches with this email, the patch will not be shown on patch works. Emails are either blocked or got rejected by loongson's mail server. It can only receive emails from you and other people, but not dri-devel. so have to use my personal email(15330273...@189.cn) to send patches. In this case you can just use your company's email to sign-off code and sending with your personal email. It's common practice. If you don't want to receiving kernel email in your company mailbox, you can add a entry in .mailmap . Thanks. - Jiaxun
Re: [PATCH v11 5/7] dt-bindings: display: Add Loongson display controller
On 2022/3/22 07:20, Rob Herring wrote: On Tue, Mar 22, 2022 at 12:29:14AM +0800, Sui Jingfeng wrote: From: suijingfeng Needs a commit message. Signed-off-by: suijingfeng Signed-off-by: Sui Jingfeng <15330273...@189.cn> Same person? Don't need both emails. Yes, suijingf...@loongson.cn is my company's email. But it can not be used to send patches to dri-devel, when send patches with this email, the patch will not be shown on patch works. Emails are either blocked or got rejected by loongson's mail server. It can only receive emails from you and other people, but not dri-devel. so have to use my personal email(15330273...@189.cn) to send patches. --- .../loongson/loongson,display-controller.yaml | 230 ++ 1 file changed, 230 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml diff --git a/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml new file mode 100644 index ..7be63346289e --- /dev/null +++ b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml @@ -0,0 +1,230 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/loongson/loongson,display-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson LS7A1000/LS2K1000/LS2K0500 Display Controller Device Tree Bindings + +maintainers: + - Sui Jingfeng + +description: |+ + + Loongson display controllers are simple which require scanout buffers + to be physically contiguous. LS2K1000/LS2K0500 is a SOC, only system + memory is available. LS7A1000/LS7A2000 is bridge chip which is equipped + with a dedicated video RAM which is 64MB or more, precise size can be + read from the PCI BAR 2 of the GPU device(0x0014:0x7A15) in the bridge + chip. + + LSDC has two display pipes, each way has a DVO interface which provide + RGB888 signals, vertical & horizontal synchronisations, data enable and + the pixel clock. LSDC has two CRTC, each CRTC is able to scanout from + 1920x1080 resolution at 60Hz. Each CRTC has two FB address registers. + + For LS7A1000, there are 4 dedicated GPIOs whose control register is + located at the DC register space. They are used to emulate two way i2c, + One for DVO0, another for DVO1. + + LS2K1000 and LS2K0500 SoC grab i2c adapter from other module, either + general purpose GPIO emulated i2c or hardware i2c in the SoC. + + LSDC's display pipeline have several components as below description, + + The display controller in LS7A1000: + ___ _ +|---| | | +| CRTC0 --> | DVO0 > Encoder0 ---> Connector0 ---> | Monitor | +| _ _ ---|^ ^|_| +| | | | |---|| | +| |_| |_|| i2c0 <+-+ +|---| +| DC IN LS7A1000 | +| _ _ ---| +| | | | || i2c1 <+-+ +| |_| |_|---|| | _ +|---|| || | +| CRTC1 --> | DVO1 > Encoder1 ---> Connector1 ---> | Panel | +|---| |_| +|___| + + Simple usage of LS7A1000 with LS3A4000 CPU: + ++--++---+ +| DDR4 || +---+| ++--+| | PCIe Root complex | LS7A1000 | + || MC0 | +--++-+++| + +--+ HT 3.0 | || || | + | LS3A4000 |<>| +---++---+ +--++--++-+ +--+ + | CPU|<>| | GC1000 | | LSDC |<-->| DDR3 MC |<->| VRAM | + +--+ | ++ +-+--+-++-+ +--+ + || MC1 +---|--|+ ++--+| | +| DDR4 | +---+ DVO0 | | DVO1 +--+ ++--+ VGA <--|ADV7125|<+ +>|TFP410|--> DVI/HDMI + +---+ +--+ + + The display controller in LS2K1000/LS2K0500: + ___ _ +|---| | | +| CRTC0 --> | DVO0 > Encoder0 ---> Connector0 ---> | Monitor | +| _ _ ---|^ ^ |_| +| | | | | || | +| |_| |_| | +--+ | +| <>| i2c0 |<-+ +| DC IN LS2K1000 |
Re: [PATCH v11 5/7] dt-bindings: display: Add Loongson display controller
On Tue, Mar 22, 2022 at 12:29:14AM +0800, Sui Jingfeng wrote: > From: suijingfeng > Needs a commit message. > Signed-off-by: suijingfeng > Signed-off-by: Sui Jingfeng <15330273...@189.cn> Same person? Don't need both emails. > --- > .../loongson/loongson,display-controller.yaml | 230 ++ > 1 file changed, 230 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > diff --git > a/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > > b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > new file mode 100644 > index ..7be63346289e > --- /dev/null > +++ > b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml > @@ -0,0 +1,230 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: > http://devicetree.org/schemas/display/loongson/loongson,display-controller.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Loongson LS7A1000/LS2K1000/LS2K0500 Display Controller Device Tree > Bindings > + > +maintainers: > + - Sui Jingfeng > + > +description: |+ > + > + Loongson display controllers are simple which require scanout buffers > + to be physically contiguous. LS2K1000/LS2K0500 is a SOC, only system > + memory is available. LS7A1000/LS7A2000 is bridge chip which is equipped > + with a dedicated video RAM which is 64MB or more, precise size can be > + read from the PCI BAR 2 of the GPU device(0x0014:0x7A15) in the bridge > + chip. > + > + LSDC has two display pipes, each way has a DVO interface which provide > + RGB888 signals, vertical & horizontal synchronisations, data enable and > + the pixel clock. LSDC has two CRTC, each CRTC is able to scanout from > + 1920x1080 resolution at 60Hz. Each CRTC has two FB address registers. > + > + For LS7A1000, there are 4 dedicated GPIOs whose control register is > + located at the DC register space. They are used to emulate two way i2c, > + One for DVO0, another for DVO1. > + > + LS2K1000 and LS2K0500 SoC grab i2c adapter from other module, either > + general purpose GPIO emulated i2c or hardware i2c in the SoC. > + > + LSDC's display pipeline have several components as below description, > + > + The display controller in LS7A1000: > + ___ _ > +|---| | | > +| CRTC0 --> | DVO0 > Encoder0 ---> Connector0 ---> | Monitor | > +| _ _ ---|^ ^|_| > +| | | | |---|| | > +| |_| |_|| i2c0 <+-+ > +|---| > +| DC IN LS7A1000 | > +| _ _ ---| > +| | | | || i2c1 <+-+ > +| |_| |_|---|| | _ > +|---|| || | > +| CRTC1 --> | DVO1 > Encoder1 ---> Connector1 ---> | Panel | > +|---| |_| > +|___| > + > + Simple usage of LS7A1000 with LS3A4000 CPU: > + > ++--++---+ > +| DDR4 || +---+| > ++--+| | PCIe Root complex | LS7A1000 | > + || MC0 | +--++-+++| > + +--+ HT 3.0 | || || | > + | LS3A4000 |<>| +---++---+ +--++--++-+ +--+ > + | CPU|<>| | GC1000 | | LSDC |<-->| DDR3 MC |<->| VRAM | > + +--+ | ++ +-+--+-++-+ +--+ > + || MC1 +---|--|+ > ++--+| | > +| DDR4 | +---+ DVO0 | | DVO1 +--+ > ++--+ VGA <--|ADV7125|<+ +>|TFP410|--> DVI/HDMI > + +---+ +--+ > + > + The display controller in LS2K1000/LS2K0500: > + ___ _ > +|---| | | > +| CRTC0 --> | DVO0 > Encoder0 ---> Connector0 ---> | Monitor | > +| _ _ ---|^ ^ |_| > +| | | | | || | > +| |_| |_| | +--+ | > +| <>| i2c0 |<-+ > +| DC IN LS2K1000 | +--+ > +| _ _| +--+ > +| | | | | <>| i2c1 |--+ > +| |_| |_| | +--+ |_ > +|---|| | | | > +|
[PATCH v11 5/7] dt-bindings: display: Add Loongson display controller
From: suijingfeng Signed-off-by: suijingfeng Signed-off-by: Sui Jingfeng <15330273...@189.cn> --- .../loongson/loongson,display-controller.yaml | 230 ++ 1 file changed, 230 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml diff --git a/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml new file mode 100644 index ..7be63346289e --- /dev/null +++ b/Documentation/devicetree/bindings/display/loongson/loongson,display-controller.yaml @@ -0,0 +1,230 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/loongson/loongson,display-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson LS7A1000/LS2K1000/LS2K0500 Display Controller Device Tree Bindings + +maintainers: + - Sui Jingfeng + +description: |+ + + Loongson display controllers are simple which require scanout buffers + to be physically contiguous. LS2K1000/LS2K0500 is a SOC, only system + memory is available. LS7A1000/LS7A2000 is bridge chip which is equipped + with a dedicated video RAM which is 64MB or more, precise size can be + read from the PCI BAR 2 of the GPU device(0x0014:0x7A15) in the bridge + chip. + + LSDC has two display pipes, each way has a DVO interface which provide + RGB888 signals, vertical & horizontal synchronisations, data enable and + the pixel clock. LSDC has two CRTC, each CRTC is able to scanout from + 1920x1080 resolution at 60Hz. Each CRTC has two FB address registers. + + For LS7A1000, there are 4 dedicated GPIOs whose control register is + located at the DC register space. They are used to emulate two way i2c, + One for DVO0, another for DVO1. + + LS2K1000 and LS2K0500 SoC grab i2c adapter from other module, either + general purpose GPIO emulated i2c or hardware i2c in the SoC. + + LSDC's display pipeline have several components as below description, + + The display controller in LS7A1000: + ___ _ +|---| | | +| CRTC0 --> | DVO0 > Encoder0 ---> Connector0 ---> | Monitor | +| _ _ ---|^ ^|_| +| | | | |---|| | +| |_| |_|| i2c0 <+-+ +|---| +| DC IN LS7A1000 | +| _ _ ---| +| | | | || i2c1 <+-+ +| |_| |_|---|| | _ +|---|| || | +| CRTC1 --> | DVO1 > Encoder1 ---> Connector1 ---> | Panel | +|---| |_| +|___| + + Simple usage of LS7A1000 with LS3A4000 CPU: + ++--++---+ +| DDR4 || +---+| ++--+| | PCIe Root complex | LS7A1000 | + || MC0 | +--++-+++| + +--+ HT 3.0 | || || | + | LS3A4000 |<>| +---++---+ +--++--++-+ +--+ + | CPU|<>| | GC1000 | | LSDC |<-->| DDR3 MC |<->| VRAM | + +--+ | ++ +-+--+-++-+ +--+ + || MC1 +---|--|+ ++--+| | +| DDR4 | +---+ DVO0 | | DVO1 +--+ ++--+ VGA <--|ADV7125|<+ +>|TFP410|--> DVI/HDMI + +---+ +--+ + + The display controller in LS2K1000/LS2K0500: + ___ _ +|---| | | +| CRTC0 --> | DVO0 > Encoder0 ---> Connector0 ---> | Monitor | +| _ _ ---|^ ^ |_| +| | | | | || | +| |_| |_| | +--+ | +| <>| i2c0 |<-+ +| DC IN LS2K1000 | +--+ +| _ _| +--+ +| | | | | <>| i2c1 |--+ +| |_| |_| | +--+ |_ +|---|| | | | +| CRTC1 --> | DVO1 > Encoder1 ---> Connector1 ---> | Panel | +|---| |_| +|___| + +properties: + $nodename: +pattern: "^display-controller@[0-9a-f],[0-9a-f]$" + + compatible: +oneOf: + - items: + - enum: + -
