[PATCH v12 8/8] drm/i915/display: Read/Write AS sdp only when sink/source has enabled

[Mitul Golani]

Write/Read Adaptive sync SDP only when Sink and Source is enabled
for the same. Also along with write TRANS_VRR_VSYNC values.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++++
 drivers/gpu/drm/i915/display/intel_dp.c  | 4 ++++
 drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++++
 3 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index bea441590204..89b8d50f12c6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3926,6 +3926,7 @@ static void intel_ddi_get_config(struct intel_encoder 
*encoder,
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+       struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
        /* XXX: DSI transcoder paranoia */
        if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
@@ -3972,6 +3973,9 @@ static void intel_ddi_get_config(struct intel_encoder 
*encoder,
        intel_read_dp_sdp(encoder, pipe_config, 
HDMI_PACKET_TYPE_GAMUT_METADATA);
        intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
 
+       if (intel_dp_as_sdp_supported(intel_dp))
+               intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
+
        intel_audio_codec_get_config(encoder, pipe_config);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2ec1f923a5a0..8304ef912767 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4276,6 +4276,7 @@ void intel_dp_set_infoframes(struct intel_encoder 
*encoder,
                         VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |
                         VIDEO_DIP_ENABLE_AS_ADL;
        u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
+       struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 
        /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
        if (!enable && HAS_DSC(dev_priv))
@@ -4293,6 +4294,9 @@ void intel_dp_set_infoframes(struct intel_encoder 
*encoder,
 
        intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
 
+       if (intel_dp_as_sdp_supported(intel_dp))
+               intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
+
        intel_write_dp_sdp(encoder, crtc_state, 
HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 668927524f23..d24a42902e69 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -214,6 +214,10 @@ void intel_vrr_set_transcoder_timings(const struct 
intel_crtc_state *crtc_state)
        intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), 
crtc_state->vrr.vmax - 1);
        intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 
trans_vrr_ctl(crtc_state));
        intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), 
crtc_state->vrr.flipline - 1);
+
+       if (crtc_state->vrr.vsync_end && crtc_state->vrr.vsync_start)
+               intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
+                              crtc_state->vrr.vsync_end << 16 | 
crtc_state->vrr.vsync_start);
 }
 
 void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
-- 
2.25.1