Re: [PATCH v14 4/9] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP

2024-02-29 Thread Nautiyal, Ankit K



On 2/29/2024 10:09 PM, Mitul Golani wrote:

Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.

--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- Remove unrelated comments and changes. [Jani]
- Correct code indent. [Jani]

--v3:
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)

--v4:
- Remove as_sdp_mode from crtc_state.
- Drop metadata keyword.
- For consistency, update ADL_ prefix or post fix as required.

--v5:
- Check if AS_SDP bit is set in crtc_state->infoframes.enable. If not
   return.
- Check for HAS_AS_SDP() before setting VIDEO_DIP_ENABLE_AS_ADL mask.
Signed-off-by: Mitul Golani 
---
  .../drm/i915/display/intel_display_device.h   |  1 +
  drivers/gpu/drm/i915/display/intel_dp.c   | 91 +++
  drivers/gpu/drm/i915/display/intel_hdmi.c | 12 ++-
  drivers/gpu/drm/i915/i915_reg.h   |  8 ++
  include/drm/display/drm_dp_helper.h   |  2 +-
  5 files changed, 112 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h 
b/drivers/gpu/drm/i915/display/intel_display_device.h
index fe4268813786..6399fbc6c738 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -68,6 +68,7 @@ struct drm_printer;
  #define HAS_TRANSCODER(i915, trans)   
((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
  BIT(trans)) != 0)
  #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
+#define HAS_AS_SDP(i915)   (DISPLAY_VER(i915) >= 13)
  #define INTEL_NUM_PIPES(i915) 
(hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
  #define I915_HAS_HOTPLUG(i915)
(DISPLAY_INFO(i915)->has_hotplug)
  #define OVERLAY_NEEDS_PHYSICAL(i915)  
(DISPLAY_INFO(i915)->overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index e13121dc3a03..7cf849015797 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4089,6 +4089,32 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state 
*crtc_state,
return false;
  }
  
+static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,

+   struct dp_sdp *sdp, size_t size)
+{
+   size_t length = sizeof(struct dp_sdp);
+
+   if (size < length)
+   return -ENOSPC;
+
+   memset(sdp, 0, size);
+
+   /* Prepare AS (Adaptive Sync) SDP Header */
+   sdp->sdp_header.HB0 = 0;
+   sdp->sdp_header.HB1 = as_sdp->sdp_type;
+   sdp->sdp_header.HB2 = 0x02;
+   sdp->sdp_header.HB3 = as_sdp->length;
+
+   /* Fill AS (Adaptive Sync) SDP Payload */
+   sdp->db[0] = as_sdp->mode;
+   sdp->db[1] = as_sdp->vtotal & 0xFF;
+   sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;
+   sdp->db[3] = as_sdp->target_rr;
+   sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
+
+   return length;
+}
+
  static ssize_t
  intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
 const struct hdmi_drm_infoframe 
*drm_infoframe,
@@ -4188,6 +4214,10 @@ static void intel_write_dp_sdp(struct intel_encoder 
*encoder,
   
&crtc_state->infoframes.drm.drm,
   &sdp, 
sizeof(sdp));
break;
+   case DP_SDP_ADAPTIVE_SYNC:
+   len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,
+  sizeof(sdp));
+   break;
default:
MISSING_CASE(type);
return;
@@ -4209,6 +4239,10 @@ void intel_dp_set_infoframes(struct intel_encoder 
*encoder,
u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
+
+   if (HAS_AS_SDP(dev_priv))
+   dip_enable |= VIDEO_DIP_ENABLE_AS_ADL;
+
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
  
  	/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */

@@ -4230,6 +4264,36 @@ void intel_dp_set_infoframes(struct intel_encoder 
*encoder,
intel_write_dp_sdp(encoder, crtc_state, 
HDMI_PACKET_TYPE_GAMUT_METADATA);
  }
  
+static

+int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
+  const void *buffer, size_t size)
+{
+   const struct dp_sdp *sdp = buffer;
+
+   if (size < sizeof(struct dp_sdp))
+   return -EINVAL;
+
+   memset(as_sdp, 0, sizeof(*as_sdp));
+
+   if (sdp->sdp_header.HB0 != 0)
+  

[PATCH v14 4/9] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP

2024-02-29 Thread Mitul Golani
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.

--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- Remove unrelated comments and changes. [Jani]
- Correct code indent. [Jani]

--v3:
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)

--v4:
- Remove as_sdp_mode from crtc_state.
- Drop metadata keyword.
- For consistency, update ADL_ prefix or post fix as required.

--v5:
- Check if AS_SDP bit is set in crtc_state->infoframes.enable. If not
  return.
- Check for HAS_AS_SDP() before setting VIDEO_DIP_ENABLE_AS_ADL mask.
Signed-off-by: Mitul Golani 
---
 .../drm/i915/display/intel_display_device.h   |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c   | 91 +++
 drivers/gpu/drm/i915/display/intel_hdmi.c | 12 ++-
 drivers/gpu/drm/i915/i915_reg.h   |  8 ++
 include/drm/display/drm_dp_helper.h   |  2 +-
 5 files changed, 112 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h 
b/drivers/gpu/drm/i915/display/intel_display_device.h
index fe4268813786..6399fbc6c738 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -68,6 +68,7 @@ struct drm_printer;
 #define HAS_TRANSCODER(i915, trans)
((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
  BIT(trans)) != 0)
 #define HAS_VRR(i915)  (DISPLAY_VER(i915) >= 11)
+#define HAS_AS_SDP(i915)   (DISPLAY_VER(i915) >= 13)
 #define INTEL_NUM_PIPES(i915)  
(hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
 #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
 #define OVERLAY_NEEDS_PHYSICAL(i915)   
(DISPLAY_INFO(i915)->overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index e13121dc3a03..7cf849015797 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4089,6 +4089,32 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state 
*crtc_state,
return false;
 }
 
+static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
+   struct dp_sdp *sdp, size_t size)
+{
+   size_t length = sizeof(struct dp_sdp);
+
+   if (size < length)
+   return -ENOSPC;
+
+   memset(sdp, 0, size);
+
+   /* Prepare AS (Adaptive Sync) SDP Header */
+   sdp->sdp_header.HB0 = 0;
+   sdp->sdp_header.HB1 = as_sdp->sdp_type;
+   sdp->sdp_header.HB2 = 0x02;
+   sdp->sdp_header.HB3 = as_sdp->length;
+
+   /* Fill AS (Adaptive Sync) SDP Payload */
+   sdp->db[0] = as_sdp->mode;
+   sdp->db[1] = as_sdp->vtotal & 0xFF;
+   sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;
+   sdp->db[3] = as_sdp->target_rr;
+   sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
+
+   return length;
+}
+
 static ssize_t
 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
 const struct hdmi_drm_infoframe 
*drm_infoframe,
@@ -4188,6 +4214,10 @@ static void intel_write_dp_sdp(struct intel_encoder 
*encoder,
   
&crtc_state->infoframes.drm.drm,
   &sdp, 
sizeof(sdp));
break;
+   case DP_SDP_ADAPTIVE_SYNC:
+   len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,
+  sizeof(sdp));
+   break;
default:
MISSING_CASE(type);
return;
@@ -4209,6 +4239,10 @@ void intel_dp_set_infoframes(struct intel_encoder 
*encoder,
u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
+
+   if (HAS_AS_SDP(dev_priv))
+   dip_enable |= VIDEO_DIP_ENABLE_AS_ADL;
+
u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
 
/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
@@ -4230,6 +4264,36 @@ void intel_dp_set_infoframes(struct intel_encoder 
*encoder,
intel_write_dp_sdp(encoder, crtc_state, 
HDMI_PACKET_TYPE_GAMUT_METADATA);
 }
 
+static
+int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
+  const void *buffer, size_t size)
+{
+   const struct dp_sdp *sdp = buffer;
+
+   if (size < sizeof(struct dp_sdp))
+   return -EINVAL;
+
+   memset(as_sdp, 0, sizeof(*as_sdp));
+
+   if (sdp->sdp_header.HB0 != 0)
+   return -EINVAL;
+
+   if (sdp->sdp_header.HB1 != DP_SDP_ADA