RE:Re: [PATCH v15 6/8] phy: freescale: Add DisplayPort/HDMI Combo-PHY driver for i.MX8MQ
Hi Vinod, Thanks for your comments, > From: Vinod Koul > Sent: 2024年4月5日 22:52 > On 06-03-24, 11:16, Alexander Stein wrote: > > From: Sandor Yu > > > > Add Cadence HDP-TX DisplayPort and HDMI PHY driver for i.MX8MQ. > > > > Cadence HDP-TX PHY could be put in either DP mode or > > HDMI mode base on the configuration chosen. > > DisplayPort or HDMI PHY mode is configured in the driver. > > > > Signed-off-by: Sandor Yu > > Signed-off-by: Alexander Stein > > --- > > drivers/phy/freescale/Kconfig| 10 + > > drivers/phy/freescale/Makefile |1 + > > drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c | 1402 > ++ > > 3 files changed, 1413 insertions(+) > > create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c > > > > diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig > > index 853958fb2c063..abacbe8ba8f46 100644 > > --- a/drivers/phy/freescale/Kconfig > > +++ b/drivers/phy/freescale/Kconfig > > @@ -35,6 +35,16 @@ config PHY_FSL_IMX8M_PCIE > > Enable this to add support for the PCIE PHY as found on > > i.MX8M family of SOCs. > > > > +config PHY_FSL_IMX8MQ_HDPTX > > + tristate "Freescale i.MX8MQ DP/HDMI PHY support" > > + depends on OF && HAS_IOMEM > > + depends on COMMON_CLK > > + select GENERIC_PHY > > + select CDNS_MHDP_HELPER > > + help > > + Enable this to support the Cadence HDPTX DP/HDMI PHY driver > > + on i.MX8MQ SOC. > > + > > endif > > > > config PHY_FSL_LYNX_28G > > diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile > > index cedb328bc4d28..17546a4da840a 100644 > > --- a/drivers/phy/freescale/Makefile > > +++ b/drivers/phy/freescale/Makefile > > @@ -1,4 +1,5 @@ > > # SPDX-License-Identifier: GPL-2.0-only > > +obj-$(CONFIG_PHY_FSL_IMX8MQ_HDPTX) += phy-fsl-imx8mq-hdptx.o > > obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o > > obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o > > obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY)+= phy-fsl-imx8-mipi-dphy.o > > diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c > b/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c > > new file mode 100644 > > index 0..3bf92718f826a > > --- /dev/null > > +++ b/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c > > @@ -0,0 +1,1402 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > +/* > > + * Cadence DP/HDMI PHY driver > > + * > > + * Copyright (C) 2022-2024 NXP Semiconductor, Inc. > > + */ > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#define ADDR_PHY_AFE 0x8 > > + > > +/* PHY registers */ > > +#define CMN_SSM_BIAS_TMR 0x0022 > > +#define CMN_PLLSM0_PLLEN_TMR 0x0029 > > +#define CMN_PLLSM0_PLLPRE_TMR0x002a > > +#define CMN_PLLSM0_PLLVREF_TMR 0x002b > > +#define CMN_PLLSM0_PLLLOCK_TMR 0x002c > > +#define CMN_PLLSM0_USER_DEF_CTRL 0x002f > > +#define CMN_PSM_CLK_CTRL 0x0061 > > +#define CMN_CDIAG_REFCLK_CTRL0x0062 > > +#define CMN_PLL0_VCOCAL_START0x0081 > > +#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084 > > +#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085 > > +#define CMN_PLL0_INTDIV 0x0094 > > +#define CMN_PLL0_FRACDIV 0x0095 > > +#define CMN_PLL0_HIGH_THR0x0096 > > +#define CMN_PLL0_DSM_DIAG0x0097 > > +#define CMN_PLL0_SS_CTRL20x0099 > > +#define CMN_ICAL_INIT_TMR0x00c4 > > +#define CMN_ICAL_ITER_TMR0x00c5 > > +#define CMN_RXCAL_INIT_TMR 0x00d4 > > +#define CMN_RXCAL_ITER_TMR 0x00d5 > > +#define CMN_TXPUCAL_CTRL 0x00e0 > > +#define CMN_TXPUCAL_INIT_TMR 0x00e4 > > +#define CMN_TXPUCAL_ITER_TMR 0x00e5 > > +#define CMN_TXPDCAL_CTRL 0x00f0 > > +#define CMN_TXPDCAL_INIT_TMR 0x00f4 > > +#define CMN_TXPDCAL_ITER_TMR 0x00f5 > > +#define CMN_ICAL_ADJ_INIT_TMR0x0102 > > +#define CMN_ICAL_ADJ_ITER_TMR0x0103 > > +#define CMN_RX_ADJ_INIT_TMR 0x0106 > > +#define CMN_RX_ADJ_ITER_TMR 0x0107 > > +#define CMN_TXPU_ADJ_CTRL0x0108 > > +#define CMN_TXPU_ADJ_INIT_TMR0x010a > > +#define CMN_TXPU_ADJ_ITER_TMR0x010b > > +#define CMN_TXPD_ADJ_CTRL0x010c > > +#define CMN_TXPD_ADJ_INIT_TMR0x010e > > +#define CMN_TXPD_ADJ_ITER_TMR0x010f > > +#define CMN_DIAG_PLL0_FBH_OVRD 0x01c0 > > +#define CMN_DIAG_PLL0_FBL_OVRD 0x01c1 > > +#define CMN_DIAG_PLL0_OVRD
Re: [PATCH v15 6/8] phy: freescale: Add DisplayPort/HDMI Combo-PHY driver for i.MX8MQ
On 06-03-24, 11:16, Alexander Stein wrote: > From: Sandor Yu > > Add Cadence HDP-TX DisplayPort and HDMI PHY driver for i.MX8MQ. > > Cadence HDP-TX PHY could be put in either DP mode or > HDMI mode base on the configuration chosen. > DisplayPort or HDMI PHY mode is configured in the driver. > > Signed-off-by: Sandor Yu > Signed-off-by: Alexander Stein > --- > drivers/phy/freescale/Kconfig| 10 + > drivers/phy/freescale/Makefile |1 + > drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c | 1402 ++ > 3 files changed, 1413 insertions(+) > create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c > > diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig > index 853958fb2c063..abacbe8ba8f46 100644 > --- a/drivers/phy/freescale/Kconfig > +++ b/drivers/phy/freescale/Kconfig > @@ -35,6 +35,16 @@ config PHY_FSL_IMX8M_PCIE > Enable this to add support for the PCIE PHY as found on > i.MX8M family of SOCs. > > +config PHY_FSL_IMX8MQ_HDPTX > + tristate "Freescale i.MX8MQ DP/HDMI PHY support" > + depends on OF && HAS_IOMEM > + depends on COMMON_CLK > + select GENERIC_PHY > + select CDNS_MHDP_HELPER > + help > + Enable this to support the Cadence HDPTX DP/HDMI PHY driver > + on i.MX8MQ SOC. > + > endif > > config PHY_FSL_LYNX_28G > diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile > index cedb328bc4d28..17546a4da840a 100644 > --- a/drivers/phy/freescale/Makefile > +++ b/drivers/phy/freescale/Makefile > @@ -1,4 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0-only > +obj-$(CONFIG_PHY_FSL_IMX8MQ_HDPTX) += phy-fsl-imx8mq-hdptx.o > obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o > obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o > obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY)+= phy-fsl-imx8-mipi-dphy.o > diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c > b/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c > new file mode 100644 > index 0..3bf92718f826a > --- /dev/null > +++ b/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c > @@ -0,0 +1,1402 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Cadence DP/HDMI PHY driver > + * > + * Copyright (C) 2022-2024 NXP Semiconductor, Inc. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define ADDR_PHY_AFE 0x8 > + > +/* PHY registers */ > +#define CMN_SSM_BIAS_TMR 0x0022 > +#define CMN_PLLSM0_PLLEN_TMR 0x0029 > +#define CMN_PLLSM0_PLLPRE_TMR0x002a > +#define CMN_PLLSM0_PLLVREF_TMR 0x002b > +#define CMN_PLLSM0_PLLLOCK_TMR 0x002c > +#define CMN_PLLSM0_USER_DEF_CTRL 0x002f > +#define CMN_PSM_CLK_CTRL 0x0061 > +#define CMN_CDIAG_REFCLK_CTRL0x0062 > +#define CMN_PLL0_VCOCAL_START0x0081 > +#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084 > +#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085 > +#define CMN_PLL0_INTDIV 0x0094 > +#define CMN_PLL0_FRACDIV 0x0095 > +#define CMN_PLL0_HIGH_THR0x0096 > +#define CMN_PLL0_DSM_DIAG0x0097 > +#define CMN_PLL0_SS_CTRL20x0099 > +#define CMN_ICAL_INIT_TMR0x00c4 > +#define CMN_ICAL_ITER_TMR0x00c5 > +#define CMN_RXCAL_INIT_TMR 0x00d4 > +#define CMN_RXCAL_ITER_TMR 0x00d5 > +#define CMN_TXPUCAL_CTRL 0x00e0 > +#define CMN_TXPUCAL_INIT_TMR 0x00e4 > +#define CMN_TXPUCAL_ITER_TMR 0x00e5 > +#define CMN_TXPDCAL_CTRL 0x00f0 > +#define CMN_TXPDCAL_INIT_TMR 0x00f4 > +#define CMN_TXPDCAL_ITER_TMR 0x00f5 > +#define CMN_ICAL_ADJ_INIT_TMR0x0102 > +#define CMN_ICAL_ADJ_ITER_TMR0x0103 > +#define CMN_RX_ADJ_INIT_TMR 0x0106 > +#define CMN_RX_ADJ_ITER_TMR 0x0107 > +#define CMN_TXPU_ADJ_CTRL0x0108 > +#define CMN_TXPU_ADJ_INIT_TMR0x010a > +#define CMN_TXPU_ADJ_ITER_TMR0x010b > +#define CMN_TXPD_ADJ_CTRL0x010c > +#define CMN_TXPD_ADJ_INIT_TMR0x010e > +#define CMN_TXPD_ADJ_ITER_TMR0x010f > +#define CMN_DIAG_PLL0_FBH_OVRD 0x01c0 > +#define CMN_DIAG_PLL0_FBL_OVRD 0x01c1 > +#define CMN_DIAG_PLL0_OVRD 0x01c2 > +#define CMN_DIAG_PLL0_TEST_MODE 0x01c4 > +#define CMN_DIAG_PLL0_V2I_TUNE 0x01c5 > +#define CMN_DIAG_PLL0_CP_TUNE0x01c6 > +#define CMN_DIAG_PLL0_LF_PROG0x01c7 > +#define CMN_DIAG_PL
RE: [EXT] [PATCH v15 6/8] phy: freescale: Add DisplayPort/HDMI Combo-PHY driver for i.MX8MQ
Hi Alexander, Thanks for your combine HDMI and DP PHY driver into one driver. Basically, the HDMI and DP PHY initialize process and configuration same as V14. I have verify the DP and HDMI function with the patch set. I'm OK for the patch. B.R Sandor > > > From: Sandor Yu > > Add Cadence HDP-TX DisplayPort and HDMI PHY driver for i.MX8MQ. > > Cadence HDP-TX PHY could be put in either DP mode or > HDMI mode base on the configuration chosen. > DisplayPort or HDMI PHY mode is configured in the driver. > > Signed-off-by: Sandor Yu > Signed-off-by: Alexander Stein > --- > drivers/phy/freescale/Kconfig| 10 + > drivers/phy/freescale/Makefile |1 + > drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c | 1402 ++ > 3 files changed, 1413 insertions(+) > create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c > > diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig > index 853958fb2c063..abacbe8ba8f46 100644 > --- a/drivers/phy/freescale/Kconfig > +++ b/drivers/phy/freescale/Kconfig > @@ -35,6 +35,16 @@ config PHY_FSL_IMX8M_PCIE > Enable this to add support for the PCIE PHY as found on > i.MX8M family of SOCs. > > +config PHY_FSL_IMX8MQ_HDPTX > + tristate "Freescale i.MX8MQ DP/HDMI PHY support" > + depends on OF && HAS_IOMEM > + depends on COMMON_CLK > + select GENERIC_PHY > + select CDNS_MHDP_HELPER > + help > + Enable this to support the Cadence HDPTX DP/HDMI PHY driver > + on i.MX8MQ SOC. > + > endif > > config PHY_FSL_LYNX_28G > diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile > index cedb328bc4d28..17546a4da840a 100644 > --- a/drivers/phy/freescale/Makefile > +++ b/drivers/phy/freescale/Makefile > @@ -1,4 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0-only > +obj-$(CONFIG_PHY_FSL_IMX8MQ_HDPTX) += phy-fsl-imx8mq-hdptx.o > obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o > obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o > obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o > diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c > b/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c > new file mode 100644 > index 0..3bf92718f826a > --- /dev/null > +++ b/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c > @@ -0,0 +1,1402 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Cadence DP/HDMI PHY driver > + * > + * Copyright (C) 2022-2024 NXP Semiconductor, Inc. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define ADDR_PHY_AFE 0x8 > + > +/* PHY registers */ > +#define CMN_SSM_BIAS_TMR 0x0022 > +#define CMN_PLLSM0_PLLEN_TMR 0x0029 > +#define CMN_PLLSM0_PLLPRE_TMR 0x002a > +#define CMN_PLLSM0_PLLVREF_TMR 0x002b > +#define CMN_PLLSM0_PLLLOCK_TMR 0x002c > +#define CMN_PLLSM0_USER_DEF_CTRL 0x002f > +#define CMN_PSM_CLK_CTRL 0x0061 > +#define CMN_CDIAG_REFCLK_CTRL 0x0062 > +#define CMN_PLL0_VCOCAL_START 0x0081 > +#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084 > +#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085 > +#define CMN_PLL0_INTDIV0x0094 > +#define CMN_PLL0_FRACDIV 0x0095 > +#define CMN_PLL0_HIGH_THR 0x0096 > +#define CMN_PLL0_DSM_DIAG 0x0097 > +#define CMN_PLL0_SS_CTRL2 0x0099 > +#define CMN_ICAL_INIT_TMR 0x00c4 > +#define CMN_ICAL_ITER_TMR 0x00c5 > +#define CMN_RXCAL_INIT_TMR 0x00d4 > +#define CMN_RXCAL_ITER_TMR 0x00d5 > +#define CMN_TXPUCAL_CTRL 0x00e0 > +#define CMN_TXPUCAL_INIT_TMR 0x00e4 > +#define CMN_TXPUCAL_ITER_TMR 0x00e5 > +#define CMN_TXPDCAL_CTRL 0x00f0 > +#define CMN_TXPDCAL_INIT_TMR 0x00f4 > +#define CMN_TXPDCAL_ITER_TMR 0x00f5 > +#define CMN_ICAL_ADJ_INIT_TMR 0x0102 > +#define CMN_ICAL_ADJ_ITER_TMR 0x0103 > +#define CMN_RX_ADJ_INIT_TMR0x0106 > +#define CMN_RX_ADJ_ITER_TMR0x0107 > +#define CMN_TXPU_ADJ_CTRL 0x0108 > +#define CMN_TXPU_ADJ_INIT_TMR 0x010a > +#define CMN_TXPU_ADJ_ITER_TMR 0x010b > +#define CMN_TXPD_ADJ_CTRL 0x010c > +#define CMN_TXPD_ADJ_INIT_TMR 0x010e > +#define CMN_TXPD_ADJ_ITER_TMR 0x010f > +#define CMN_DIAG_PLL0_FBH_OVRD 0x01c0 > +#define CMN_DIAG_PLL0_FBL_OVRD 0x01c1 > +#define CMN_DIAG_PLL0_OVRD 0x01c2 > +#define CMN_DIAG_PLL0_TEST_MODE
[PATCH v15 6/8] phy: freescale: Add DisplayPort/HDMI Combo-PHY driver for i.MX8MQ
From: Sandor Yu Add Cadence HDP-TX DisplayPort and HDMI PHY driver for i.MX8MQ. Cadence HDP-TX PHY could be put in either DP mode or HDMI mode base on the configuration chosen. DisplayPort or HDMI PHY mode is configured in the driver. Signed-off-by: Sandor Yu Signed-off-by: Alexander Stein --- drivers/phy/freescale/Kconfig| 10 + drivers/phy/freescale/Makefile |1 + drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c | 1402 ++ 3 files changed, 1413 insertions(+) create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig index 853958fb2c063..abacbe8ba8f46 100644 --- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig @@ -35,6 +35,16 @@ config PHY_FSL_IMX8M_PCIE Enable this to add support for the PCIE PHY as found on i.MX8M family of SOCs. +config PHY_FSL_IMX8MQ_HDPTX + tristate "Freescale i.MX8MQ DP/HDMI PHY support" + depends on OF && HAS_IOMEM + depends on COMMON_CLK + select GENERIC_PHY + select CDNS_MHDP_HELPER + help + Enable this to support the Cadence HDPTX DP/HDMI PHY driver + on i.MX8MQ SOC. + endif config PHY_FSL_LYNX_28G diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile index cedb328bc4d28..17546a4da840a 100644 --- a/drivers/phy/freescale/Makefile +++ b/drivers/phy/freescale/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_PHY_FSL_IMX8MQ_HDPTX) += phy-fsl-imx8mq-hdptx.o obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c b/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c new file mode 100644 index 0..3bf92718f826a --- /dev/null +++ b/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c @@ -0,0 +1,1402 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cadence DP/HDMI PHY driver + * + * Copyright (C) 2022-2024 NXP Semiconductor, Inc. + */ +#include +#include +#include +#include +#include +#include +#include + +#define ADDR_PHY_AFE 0x8 + +/* PHY registers */ +#define CMN_SSM_BIAS_TMR 0x0022 +#define CMN_PLLSM0_PLLEN_TMR 0x0029 +#define CMN_PLLSM0_PLLPRE_TMR 0x002a +#define CMN_PLLSM0_PLLVREF_TMR 0x002b +#define CMN_PLLSM0_PLLLOCK_TMR 0x002c +#define CMN_PLLSM0_USER_DEF_CTRL 0x002f +#define CMN_PSM_CLK_CTRL 0x0061 +#define CMN_CDIAG_REFCLK_CTRL 0x0062 +#define CMN_PLL0_VCOCAL_START 0x0081 +#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084 +#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085 +#define CMN_PLL0_INTDIV0x0094 +#define CMN_PLL0_FRACDIV 0x0095 +#define CMN_PLL0_HIGH_THR 0x0096 +#define CMN_PLL0_DSM_DIAG 0x0097 +#define CMN_PLL0_SS_CTRL2 0x0099 +#define CMN_ICAL_INIT_TMR 0x00c4 +#define CMN_ICAL_ITER_TMR 0x00c5 +#define CMN_RXCAL_INIT_TMR 0x00d4 +#define CMN_RXCAL_ITER_TMR 0x00d5 +#define CMN_TXPUCAL_CTRL 0x00e0 +#define CMN_TXPUCAL_INIT_TMR 0x00e4 +#define CMN_TXPUCAL_ITER_TMR 0x00e5 +#define CMN_TXPDCAL_CTRL 0x00f0 +#define CMN_TXPDCAL_INIT_TMR 0x00f4 +#define CMN_TXPDCAL_ITER_TMR 0x00f5 +#define CMN_ICAL_ADJ_INIT_TMR 0x0102 +#define CMN_ICAL_ADJ_ITER_TMR 0x0103 +#define CMN_RX_ADJ_INIT_TMR0x0106 +#define CMN_RX_ADJ_ITER_TMR0x0107 +#define CMN_TXPU_ADJ_CTRL 0x0108 +#define CMN_TXPU_ADJ_INIT_TMR 0x010a +#define CMN_TXPU_ADJ_ITER_TMR 0x010b +#define CMN_TXPD_ADJ_CTRL 0x010c +#define CMN_TXPD_ADJ_INIT_TMR 0x010e +#define CMN_TXPD_ADJ_ITER_TMR 0x010f +#define CMN_DIAG_PLL0_FBH_OVRD 0x01c0 +#define CMN_DIAG_PLL0_FBL_OVRD 0x01c1 +#define CMN_DIAG_PLL0_OVRD 0x01c2 +#define CMN_DIAG_PLL0_TEST_MODE0x01c4 +#define CMN_DIAG_PLL0_V2I_TUNE 0x01c5 +#define CMN_DIAG_PLL0_CP_TUNE 0x01c6 +#define CMN_DIAG_PLL0_LF_PROG 0x01c7 +#define CMN_DIAG_PLL0_PTATIS_TUNE1 0x01c8 +#define CMN_DIAG_PLL0_PTATIS_TUNE2 0x01c9 +#define CMN_DIAG_PLL0_INCLK_CTRL 0x01ca +#define CMN_DIAG_PLL0_PXL_DIVH 0x01cb +#define CMN_DIAG_PLL0_PXL_DIVL 0x01cc +#define CMN_DIAG_HSCLK_SEL