Re: [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema
On Fri, 2020-10-16 at 12:00 -0500, Rob Herring wrote: > On Tue, Oct 13, 2020 at 04:52:00PM +0800, Chunfeng Yun wrote: > > Convert phy-mtk-xsphy.txt to YAML schema mediatek,xsphy.yaml > > > > Signed-off-by: Chunfeng Yun > > --- > > v2: modify description and compatible definition suggested by Rob > > --- > > .../bindings/phy/mediatek,xsphy.yaml | 200 ++ > > .../devicetree/bindings/phy/phy-mtk-xsphy.txt | 109 -- > > 2 files changed, 200 insertions(+), 109 deletions(-) > > create mode 100644 > > Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml > > delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt > > > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml > > b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml > > new file mode 100644 > > index ..86511f19277a > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml > > @@ -0,0 +1,200 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +# Copyright (c) 2020 MediaTek > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek XS-PHY Controller Device Tree Bindings > > + > > +maintainers: > > + - Chunfeng Yun > > + > > +description: | > > + The XS-PHY controller supports physical layer functionality for USB3.1 > > + GEN2 controller on MediaTek SoCs. [...] > > + > > + ranges: true > > + > > + mediatek,src-ref-clk-mhz: > > +description: > > + Frequency of reference clock for slew rate calibrate > > +$ref: /schemas/types.yaml#/definitions/uint32 > > Properties with a standard unit suffix don't need a type. Ok, will remove it, and also do it for other patches, thanks > > -- [...] > > 2.18.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema
On Tue, Oct 13, 2020 at 04:52:00PM +0800, Chunfeng Yun wrote: > Convert phy-mtk-xsphy.txt to YAML schema mediatek,xsphy.yaml > > Signed-off-by: Chunfeng Yun > --- > v2: modify description and compatible definition suggested by Rob > --- > .../bindings/phy/mediatek,xsphy.yaml | 200 ++ > .../devicetree/bindings/phy/phy-mtk-xsphy.txt | 109 -- > 2 files changed, 200 insertions(+), 109 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml > delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml > b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml > new file mode 100644 > index ..86511f19277a > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml > @@ -0,0 +1,200 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2020 MediaTek > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek XS-PHY Controller Device Tree Bindings > + > +maintainers: > + - Chunfeng Yun > + > +description: | > + The XS-PHY controller supports physical layer functionality for USB3.1 > + GEN2 controller on MediaTek SoCs. > + > + Banks layout of xsphy > + -- > + portoffsetbank > + u2 port00xMISC > + 0x0100FMREG > + 0x0300U2PHY_COM > + u2 port10x1000MISC > + 0x1100FMREG > + 0x1300U2PHY_COM > + u2 port20x2000MISC > + ... > + u31 common 0x3000DIG_GLB > + 0x3100PHYA_GLB > + u31 port0 0x3400DIG_LN_TOP > + 0x3500DIG_LN_TX0 > + 0x3600DIG_LN_RX0 > + 0x3700DIG_LN_DAIF > + 0x3800PHYA_LN > + u31 port1 0x3a00DIG_LN_TOP > + 0x3b00DIG_LN_TX0 > + 0x3c00DIG_LN_RX0 > + 0x3d00DIG_LN_DAIF > + 0x3e00PHYA_LN > + ... > + DIG_GLB & PHYA_GLB are shared by U31 ports. > + > +properties: > + $nodename: > +pattern: "^xs-phy@[0-9a-f]+$" > + > + compatible: > +items: > + - enum: > + - mediatek,mt3611-xsphy > + - mediatek,mt3612-xsphy > + - const: mediatek,xsphy > + > + reg: > +description: | > + Register shared by multiple U3 ports, exclude port's private register, > + if only U2 ports provided, shouldn't use the property. > +maxItems: 1 > + > + "#address-cells": > + enum: [1, 2] > + > + "#size-cells": > + enum: [1, 2] > + > + ranges: true > + > + mediatek,src-ref-clk-mhz: > +description: > + Frequency of reference clock for slew rate calibrate > +$ref: /schemas/types.yaml#/definitions/uint32 Properties with a standard unit suffix don't need a type. > +default: 26 > + > + mediatek,src-coef: > +description: > + Coefficient for slew rate calibrate, depends on SoC process > +$ref: /schemas/types.yaml#/definitions/uint32 > +default: 17 > + > +# Required child node: > +patternProperties: > + "^usb-phy@[0-9a-f]+$": > +type: object > +description: | > + A sub-node is required for each port the controller provides. > + Address range information including the usual 'reg' property > + is used inside these nodes to describe the controller's topology. > + > +properties: > + reg: > +maxItems: 1 > + > + clocks: > +items: > + - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz) > + > + clock-names: > +items: > + - const: ref > + > + "#phy-cells": > +const: 1 > +description: | > + The cells contain the following arguments. > + > + - description: The PHY type > + enum: > +- PHY_TYPE_USB2 > +- PHY_TYPE_USB3 > + > + #The following optional vendor properties are only for debug or HQA > test > + mediatek,eye-src: > +description: > + The value of slew rate calibrate (U2 phy) > +$ref: /schemas/types.yaml#/definitions/uint32 > +minimum: 1 > +maximum: 7 > + > + mediatek,eye-vrt: > +description: > + The selection of VRT reference voltage (U2 phy) > +$ref: /schemas/types.yaml#/definitions/uint32 > +minimum: 1 > +maximum: 7 > + > + mediatek,eye-term: > +description: > + The selection of HS_TX TERM reference voltage (U2 phy) > +$ref: /schemas/types.yaml#/definitions/uint32 > +minimum: 1 > +maximum: 7 > + > + mediatek,efuse-intr: > +description: > + The selection of Internal Resistor (U2/U3 phy) > +$ref: /schemas/types.yaml#/definitions/uint32 > +
[PATCH v2 1/8] dt-bindings: phy: convert phy-mtk-xsphy.txt to YAML schema
Convert phy-mtk-xsphy.txt to YAML schema mediatek,xsphy.yaml Signed-off-by: Chunfeng Yun --- v2: modify description and compatible definition suggested by Rob --- .../bindings/phy/mediatek,xsphy.yaml | 200 ++ .../devicetree/bindings/phy/phy-mtk-xsphy.txt | 109 -- 2 files changed, 200 insertions(+), 109 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml new file mode 100644 index ..86511f19277a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml @@ -0,0 +1,200 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2020 MediaTek +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek XS-PHY Controller Device Tree Bindings + +maintainers: + - Chunfeng Yun + +description: | + The XS-PHY controller supports physical layer functionality for USB3.1 + GEN2 controller on MediaTek SoCs. + + Banks layout of xsphy + -- + portoffsetbank + u2 port00xMISC + 0x0100FMREG + 0x0300U2PHY_COM + u2 port10x1000MISC + 0x1100FMREG + 0x1300U2PHY_COM + u2 port20x2000MISC + ... + u31 common 0x3000DIG_GLB + 0x3100PHYA_GLB + u31 port0 0x3400DIG_LN_TOP + 0x3500DIG_LN_TX0 + 0x3600DIG_LN_RX0 + 0x3700DIG_LN_DAIF + 0x3800PHYA_LN + u31 port1 0x3a00DIG_LN_TOP + 0x3b00DIG_LN_TX0 + 0x3c00DIG_LN_RX0 + 0x3d00DIG_LN_DAIF + 0x3e00PHYA_LN + ... + DIG_GLB & PHYA_GLB are shared by U31 ports. + +properties: + $nodename: +pattern: "^xs-phy@[0-9a-f]+$" + + compatible: +items: + - enum: + - mediatek,mt3611-xsphy + - mediatek,mt3612-xsphy + - const: mediatek,xsphy + + reg: +description: | + Register shared by multiple U3 ports, exclude port's private register, + if only U2 ports provided, shouldn't use the property. +maxItems: 1 + + "#address-cells": + enum: [1, 2] + + "#size-cells": + enum: [1, 2] + + ranges: true + + mediatek,src-ref-clk-mhz: +description: + Frequency of reference clock for slew rate calibrate +$ref: /schemas/types.yaml#/definitions/uint32 +default: 26 + + mediatek,src-coef: +description: + Coefficient for slew rate calibrate, depends on SoC process +$ref: /schemas/types.yaml#/definitions/uint32 +default: 17 + +# Required child node: +patternProperties: + "^usb-phy@[0-9a-f]+$": +type: object +description: | + A sub-node is required for each port the controller provides. + Address range information including the usual 'reg' property + is used inside these nodes to describe the controller's topology. + +properties: + reg: +maxItems: 1 + + clocks: +items: + - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz) + + clock-names: +items: + - const: ref + + "#phy-cells": +const: 1 +description: | + The cells contain the following arguments. + + - description: The PHY type + enum: +- PHY_TYPE_USB2 +- PHY_TYPE_USB3 + + #The following optional vendor properties are only for debug or HQA test + mediatek,eye-src: +description: + The value of slew rate calibrate (U2 phy) +$ref: /schemas/types.yaml#/definitions/uint32 +minimum: 1 +maximum: 7 + + mediatek,eye-vrt: +description: + The selection of VRT reference voltage (U2 phy) +$ref: /schemas/types.yaml#/definitions/uint32 +minimum: 1 +maximum: 7 + + mediatek,eye-term: +description: + The selection of HS_TX TERM reference voltage (U2 phy) +$ref: /schemas/types.yaml#/definitions/uint32 +minimum: 1 +maximum: 7 + + mediatek,efuse-intr: +description: + The selection of Internal Resistor (U2/U3 phy) +$ref: /schemas/types.yaml#/definitions/uint32 +minimum: 1 +maximum: 63 + + mediatek,efuse-tx-imp: +description: + The selection of TX Impedance (U3 phy) +$ref: /schemas/types.yaml#/definitions/uint32 +minimum: 1 +maximum: 31 + + mediatek,efuse-rx-imp: +description: + The selection of RX Impedance (U3 phy) +$ref: /schemas/types.yaml#/definitions/uint32 +minimum: 1 +maximum: 31
