Re: [PATCH v2 14/14] phy/rockchip: inno-hdmi: Support more pre-pll configuration
Hi,
What's the status for this patch?
This is just what I needed for A95X Z2 to get the vop+hdmi and monitor
working. ;)
Could this become applied to mainline already?
The ack is already there.
Thanks,
Johan Jonker
https://lore.kernel.org/lkml/20200620134659.4592-1-jbx6...@gmail.com/
On 1/8/20 10:07 PM, Jonas Karlman wrote:
> From: Algea Cao
>
> Adding the following freq cfg in 8-bit and 10-bit color depth:
>
> {
> 4000, 6500, 7100, 8350, 8575,
> 8875, 10800, 11900, 16200
> }
>
> New freq has been validated by quantumdata 980.
>
> For some freq which can't be got by only using integer freq div,
> frac freq div is needed, Such as 88.75Mhz 10-bit. But The actual
> freq is different from the target freq, We must try to narrow
> the gap between them. RK322X only support integer freq div.
>
> The VCO of pre-PLL must be more than 2Ghz, otherwise PLL may be
> unlocked.
>
> Signed-off-by: Algea Cao
> Signed-off-by: Jonas Karlman
> Acked-by: Heiko Stuebner
> ---
> drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 74 ---
> 1 file changed, 49 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
> b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
> index 3719309ad0d0..bb8bdf5e3301 100644
> --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
> @@ -291,32 +291,56 @@ struct inno_hdmi_phy_drv_data {
> const struct phy_config *phy_cfg_table;
> };
>
> +/*
> + * If only using integer freq div can't get frequency we want, frac
> + * freq div is needed. For example, pclk 88.75 Mhz and tmdsclk
> + * 110.9375 Mhz must use frac div 0xF0. The actual frequency is different
> + * from the target frequency. Such as the tmds clock 110.9375 Mhz,
> + * the actual tmds clock we get is 110.93719 Mhz. It is important
> + * to note that RK322X platforms do not support frac div.
> + */
> static const struct pre_pll_config pre_pll_cfg_table[] = {
> - { 2700, 2700, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
> - { 2700, 3375, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
> - { 4000, 4000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
> - { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B},
> - { 5940, 5940, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0},
> - { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B},
> - { 5940, 7425, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0},
> - { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B},
> - { 7425, 7425, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0},
> - { 74176000, 9272, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817},
> - { 7425, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0},
> - {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B},
> - {14850, 14850, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0},
> - {148352000, 18544, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817},
> - {14850, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0},
> - {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B},
> - {29700, 29700, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0},
> - {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817},
> - {29700, 37125, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0},
> - {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B},
> - {59400, 29700, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0},
> - {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817},
> - {59400, 37125, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0},
> - {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B},
> - {59400, 59400, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0},
> + { 2700, 2700, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
> + { 2700, 3375, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
> + { 4000, 4000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
> + { 4000, 5000, 1, 100, 2, 2, 2, 1, 0, 0, 15, 0, 0},
> + { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B},
> + { 5940, 5940, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0},
> + { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B},
> + { 5940, 7425, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0},
> + { 6500, 6500, 1, 130, 2, 2, 2, 1, 0, 0, 12, 0, 0},
> + { 6500, 8125, 3, 325, 0, 3, 3, 1, 0, 0, 10, 0, 0},
> + { 7100, 7100, 3, 284, 0, 3, 3, 1, 0, 0, 8, 0, 0},
> + { 7100, 8875, 3, 355, 0, 3, 3, 1, 0, 0, 10, 0, 0},
> + { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B},
> + { 7425, 7425, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0},
> + { 74176000, 9272, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817},
> + { 7425, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0},
> + { 8350, 8350, 2, 167, 2, 1, 1, 1,
Re: [PATCH v2 14/14] phy/rockchip: inno-hdmi: Support more pre-pll configuration
On 2020-07-07 21:53, Johan Jonker wrote:
>
> Hi,
>
> What's the status for this patch?
> This is just what I needed for A95X Z2 to get the vop+hdmi and monitor
> working. ;)
>
> Could this become applied to mainline already?
> The ack is already there.
I will send a v3 of the phy/rockchip parts of this series later
tonight/tomorrow.
The drm side still need work and I have some pending patches that also
improve rk3288/rk3399 hdmi support for up to 4k@30hz, should make its way
onto the list in a few days.
Regards,
Jonas
>
> Thanks,
>
> Johan Jonker
>
> https://lore.kernel.org/lkml/20200620134659.4592-1-jbx6...@gmail.com/
>
> On 1/8/20 10:07 PM, Jonas Karlman wrote:
>> From: Algea Cao
>>
>> Adding the following freq cfg in 8-bit and 10-bit color depth:
>>
>> {
>> 4000, 6500, 7100, 8350, 8575,
>> 8875, 10800, 11900, 16200
>> }
>>
>> New freq has been validated by quantumdata 980.
>>
>> For some freq which can't be got by only using integer freq div,
>> frac freq div is needed, Such as 88.75Mhz 10-bit. But The actual
>> freq is different from the target freq, We must try to narrow
>> the gap between them. RK322X only support integer freq div.
>>
>> The VCO of pre-PLL must be more than 2Ghz, otherwise PLL may be
>> unlocked.
>>
>> Signed-off-by: Algea Cao
>> Signed-off-by: Jonas Karlman
>> Acked-by: Heiko Stuebner
>> ---
>> drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 74 ---
>> 1 file changed, 49 insertions(+), 25 deletions(-)
>>
>> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
>> b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
>> index 3719309ad0d0..bb8bdf5e3301 100644
>> --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
>> +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
>> @@ -291,32 +291,56 @@ struct inno_hdmi_phy_drv_data {
>> const struct phy_config *phy_cfg_table;
>> };
>>
>> +/*
>> + * If only using integer freq div can't get frequency we want, frac
>> + * freq div is needed. For example, pclk 88.75 Mhz and tmdsclk
>> + * 110.9375 Mhz must use frac div 0xF0. The actual frequency is
>> different
>> + * from the target frequency. Such as the tmds clock 110.9375 Mhz,
>> + * the actual tmds clock we get is 110.93719 Mhz. It is important
>> + * to note that RK322X platforms do not support frac div.
>> + */
>> static const struct pre_pll_config pre_pll_cfg_table[] = {
>> -{ 2700, 2700, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
>> -{ 2700, 3375, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
>> -{ 4000, 4000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
>> -{ 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B},
>> -{ 5940, 5940, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0},
>> -{ 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B},
>> -{ 5940, 7425, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0},
>> -{ 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B},
>> -{ 7425, 7425, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0},
>> -{ 74176000, 9272, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817},
>> -{ 7425, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0},
>> -{148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B},
>> -{14850, 14850, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0},
>> -{148352000, 18544, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817},
>> -{14850, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0},
>> -{296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B},
>> -{29700, 29700, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0},
>> -{296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817},
>> -{29700, 37125, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0},
>> -{593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B},
>> -{59400, 29700, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0},
>> -{593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817},
>> -{59400, 37125, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0},
>> -{593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B},
>> -{59400, 59400, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0},
>> +{ 2700, 2700, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
>> +{ 2700, 3375, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
>> +{ 4000, 4000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
>> +{ 4000, 5000, 1, 100, 2, 2, 2, 1, 0, 0, 15, 0, 0},
>> +{ 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B},
>> +{ 5940, 5940, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0},
>> +{ 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B},
>> +{ 5940, 7425, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0},
>> +{ 6500, 6500, 1, 130, 2, 2, 2, 1, 0, 0, 12, 0, 0},
>> +{ 6500, 8125, 3, 325, 0, 3, 3, 1, 0, 0, 10, 0, 0},
>> +{ 7100, 7100, 3, 284, 0, 3, 3, 1, 0, 0, 8, 0, 0},
>> +{ 7100,
[PATCH v2 14/14] phy/rockchip: inno-hdmi: Support more pre-pll configuration
From: Algea Cao
Adding the following freq cfg in 8-bit and 10-bit color depth:
{
4000, 6500, 7100, 8350, 8575,
8875, 10800, 11900, 16200
}
New freq has been validated by quantumdata 980.
For some freq which can't be got by only using integer freq div,
frac freq div is needed, Such as 88.75Mhz 10-bit. But The actual
freq is different from the target freq, We must try to narrow
the gap between them. RK322X only support integer freq div.
The VCO of pre-PLL must be more than 2Ghz, otherwise PLL may be
unlocked.
Signed-off-by: Algea Cao
Signed-off-by: Jonas Karlman
Acked-by: Heiko Stuebner
---
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 74 ---
1 file changed, 49 insertions(+), 25 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
index 3719309ad0d0..bb8bdf5e3301 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
@@ -291,32 +291,56 @@ struct inno_hdmi_phy_drv_data {
const struct phy_config *phy_cfg_table;
};
+/*
+ * If only using integer freq div can't get frequency we want, frac
+ * freq div is needed. For example, pclk 88.75 Mhz and tmdsclk
+ * 110.9375 Mhz must use frac div 0xF0. The actual frequency is different
+ * from the target frequency. Such as the tmds clock 110.9375 Mhz,
+ * the actual tmds clock we get is 110.93719 Mhz. It is important
+ * to note that RK322X platforms do not support frac div.
+ */
static const struct pre_pll_config pre_pll_cfg_table[] = {
- { 2700, 2700, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
- { 2700, 3375, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
- { 4000, 4000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
- { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B},
- { 5940, 5940, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0},
- { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B},
- { 5940, 7425, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0},
- { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B},
- { 7425, 7425, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0},
- { 74176000, 9272, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817},
- { 7425, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0},
- {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B},
- {14850, 14850, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0},
- {148352000, 18544, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817},
- {14850, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0},
- {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B},
- {29700, 29700, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0},
- {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817},
- {29700, 37125, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0},
- {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B},
- {59400, 29700, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0},
- {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817},
- {59400, 37125, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0},
- {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B},
- {59400, 59400, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0},
+ { 2700, 2700, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
+ { 2700, 3375, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
+ { 4000, 4000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
+ { 4000, 5000, 1, 100, 2, 2, 2, 1, 0, 0, 15, 0, 0},
+ { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B},
+ { 5940, 5940, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0},
+ { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B},
+ { 5940, 7425, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0},
+ { 6500, 6500, 1, 130, 2, 2, 2, 1, 0, 0, 12, 0, 0},
+ { 6500, 8125, 3, 325, 0, 3, 3, 1, 0, 0, 10, 0, 0},
+ { 7100, 7100, 3, 284, 0, 3, 3, 1, 0, 0, 8, 0, 0},
+ { 7100, 8875, 3, 355, 0, 3, 3, 1, 0, 0, 10, 0, 0},
+ { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B},
+ { 7425, 7425, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0},
+ { 74176000, 9272, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817},
+ { 7425, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0},
+ { 8350, 8350, 2, 167, 2, 1, 1, 1, 0, 0, 6, 0, 0},
+ { 8350, 104375000, 1, 104, 2, 1, 1, 1, 1, 0, 5, 0, 0x60},
+ { 8575, 8575, 3, 343, 0, 3, 3, 1, 0, 0, 8, 0, 0},
+ { 8875, 8875, 3, 355, 0, 3, 3, 1, 0, 0, 8, 0, 0},
+ { 8875, 110937500, 1, 110, 2, 1, 1, 1, 1, 0, 5, 0, 0xF0},
+ {10800, 10800, 1, 90, 3, 0, 0, 1, 0, 0, 5, 0, 0},
+ {10800, 13500, 1, 90, 0, 2,
