Re: [PATCH v2 2/3] arm64: dts: qcom: sc8280xp: Add GPU related nodes
On Tue, May 30, 2023 at 08:35:14AM -0700, Bjorn Andersson wrote:
>
> On Mon, May 29, 2023 at 02:16:14PM +0530, Manivannan Sadhasivam wrote:
> > On Mon, May 29, 2023 at 09:38:59AM +0200, Konrad Dybcio wrote:
> > > On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> > > > On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
> > > >> On 23.05.2023 03:15, Bjorn Andersson wrote:
> > > >>> From: Bjorn Andersson
> [..]
> > > >>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > > >>> b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> [..]
> > > >>> + gmu: gmu@3d6a000 {
> [..]
> > > >>> + status = "disabled";
> > > >> I've recently discovered that - and I am not 100% sure - all GMUs are
> > > >> cache-coherent. Could you please ask somebody at qc about this?
> > > >>
> > > >
> > > > AFAIU, GMU's job is controlling the voltage and clock to the GPU.
> > > Not just that, it's only the limited functionality we've implemented
> > > upstream so far.
> > >
> >
> > Okay, good to know!
> >
> > > It doesn't do
> > > > any data transactions on its own.
> > > Of course it does. AP communication is done through MMIO writes and
> > > the GMU talks to RPMh via the GPU RSC directly. Apart from that, some
> > > of the GPU registers (that nota bene don't have anything to do with
> > > the GMU M3 core itself) lay within the GMU address space.
> > >
>
> But those aren't shared memory accesses.
>
> >
> > That doesn't justify the fact that cache coherency is needed, especially
> > MMIO writes, unless GMU could snoop the MMIO writes to AP caches.
> >
>
> In reviewing the downstream state again I noticed that the GPU smmu is
> marked dma-coherent, so I will adjust that in v3.
Bjorn,
Would you mind sharing a perf delta (preferrably manhattan offscreen)
you see with and without this dma-coherent property?
-Akhil.
>
> Regards,
> Bjorn
Re: [PATCH v2 2/3] arm64: dts: qcom: sc8280xp: Add GPU related nodes
On Mon, May 29, 2023 at 09:38:59AM +0200, Konrad Dybcio wrote:
>
>
>
> On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> > On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
> >>
> >>
> >> On 23.05.2023 03:15, Bjorn Andersson wrote:
> >>> From: Bjorn Andersson
> >>>
> >>> Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
> >>> SC8280XP.
> >>>
> >>> Signed-off-by: Bjorn Andersson
> >>> Signed-off-by: Bjorn Andersson
> >>> ---
> >> It does not look like you tested the DTS against bindings. Please run
> >> `make dtbs_check` (see
> >> Documentation/devicetree/bindings/writing-schema.rst for instructions).
> >>
> >>>
> >>> Changes since v1:
> >>> - Dropped gmu_pdc_seq region from &gmu, as it shouldn't have been used.
> >>> - Added missing compatible to &adreno_smmu.
> >>> - Dropped aoss_qmp clock in &gmu and &adreno_smmu.
> >>>
> >>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 +
> >>> 1 file changed, 169 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> index d2a2224d138a..329ec2119ecf 100644
> >>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> @@ -6,6 +6,7 @@
> >>>
> >>> #include
> >>> #include
> >>> +#include
> >>> #include
> >>> #include
> >>> #include
> >>> @@ -2331,6 +2332,174 @@ tcsr: syscon@1fc {
> >>> reg = <0x0 0x01fc 0x0 0x3>;
> >>> };
> >>>
> >>> + gpu: gpu@3d0 {
> >>> + compatible = "qcom,adreno-690.0", "qcom,adreno";
> >>> +
> >>> + reg = <0 0x03d0 0 0x4>,
> >>> + <0 0x03d9e000 0 0x1000>,
> >>> + <0 0x03d61000 0 0x800>;
> >>> + reg-names = "kgsl_3d0_reg_memory",
> >>> + "cx_mem",
> >>> + "cx_dbgc";
> >>> + interrupts = ;
> >>> + iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>;
> >>> + operating-points-v2 = <&gpu_opp_table>;
> >>> +
> >>> + qcom,gmu = <&gmu>;
> >>> + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt
> >>> SLAVE_EBI1 0>;
> >>> + interconnect-names = "gfx-mem";
> >>> + #cooling-cells = <2>;
> >>> +
> >>> + status = "disabled";
> >>> +
> >>> + gpu_opp_table: opp-table {
> >>> + compatible = "operating-points-v2";
> >>> +
> >>> + opp-27000 {
> >>> + opp-hz = /bits/ 64 <27000>;
> >>> + opp-level =
> >>> ;
> >>> + opp-peak-kBps = <451000>;
> >>> + };
> >>> +
> >>> + opp-41000 {
> >>> + opp-hz = /bits/ 64 <41000>;
> >>> + opp-level = ;
> >>> + opp-peak-kBps = <1555000>;
> >>> + };
> >>> +
> >>> + opp-5 {
> >>> + opp-hz = /bits/ 64 <5>;
> >>> + opp-level =
> >>> ;
> >>> + opp-peak-kBps = <1555000>;
> >>> + };
> >>> +
> >>> + opp-54700 {
> >>> + opp-hz = /bits/ 64 <54700>;
> >>> + opp-level =
> >>> ;
> >>> + opp-peak-kBps = <1555000>;
> >>> + };
> >>> +
> >>> + opp-60600 {
> >>> + opp-hz = /bits/ 64 <60600>;
> >>> + opp-level = ;
> >>> + opp-peak-kBps = <2736000>;
> >>> + };
> >>> +
> >>> + opp-64000 {
> >>> + opp-hz = /bits/ 64 <64000>;
> >>> + opp-level =
> >>> ;
> >>> + opp-peak-kBps = <2736000>;
> >>> + };
> >>> +
> >>> + opp-69000 {
> >>> + opp-hz = /bits/ 64 <69000>;
> >>> + opp-level =
> >>> ;
> >>> + opp-peak-kBps = <2736000>;
> >>> + };
> >>> + };
> >>> + };
> >>> +
> >>> + gmu: gmu@3d6a000 {
> >>> + compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
> >>> + reg = <0 0x03d6a000 0 0x34000>,
> >>> + <0 0x03de 0 0x1>,
> >>> + <0 0x0b29 0 0x1>;
> >>> + reg-names = "gmu", "rscc", "gmu_pdc";
> >>> +
Re: [PATCH v2 2/3] arm64: dts: qcom: sc8280xp: Add GPU related nodes
On Mon, May 29, 2023 at 02:16:14PM +0530, Manivannan Sadhasivam wrote:
> On Mon, May 29, 2023 at 09:38:59AM +0200, Konrad Dybcio wrote:
> > On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> > > On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
> > >> On 23.05.2023 03:15, Bjorn Andersson wrote:
> > >>> From: Bjorn Andersson
[..]
> > >>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > >>> b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
[..]
> > >>> + gmu: gmu@3d6a000 {
[..]
> > >>> + status = "disabled";
> > >> I've recently discovered that - and I am not 100% sure - all GMUs are
> > >> cache-coherent. Could you please ask somebody at qc about this?
> > >>
> > >
> > > AFAIU, GMU's job is controlling the voltage and clock to the GPU.
> > Not just that, it's only the limited functionality we've implemented
> > upstream so far.
> >
>
> Okay, good to know!
>
> > It doesn't do
> > > any data transactions on its own.
> > Of course it does. AP communication is done through MMIO writes and
> > the GMU talks to RPMh via the GPU RSC directly. Apart from that, some
> > of the GPU registers (that nota bene don't have anything to do with
> > the GMU M3 core itself) lay within the GMU address space.
> >
But those aren't shared memory accesses.
>
> That doesn't justify the fact that cache coherency is needed, especially
> MMIO writes, unless GMU could snoop the MMIO writes to AP caches.
>
In reviewing the downstream state again I noticed that the GPU smmu is
marked dma-coherent, so I will adjust that in v3.
Regards,
Bjorn
Re: [PATCH v2 2/3] arm64: dts: qcom: sc8280xp: Add GPU related nodes
On Mon, May 29, 2023 at 09:38:59AM +0200, Konrad Dybcio wrote:
>
>
> On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> > On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
> >>
> >>
> >> On 23.05.2023 03:15, Bjorn Andersson wrote:
> >>> From: Bjorn Andersson
> >>>
> >>> Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
> >>> SC8280XP.
> >>>
> >>> Signed-off-by: Bjorn Andersson
> >>> Signed-off-by: Bjorn Andersson
> >>> ---
> >> It does not look like you tested the DTS against bindings. Please run
> >> `make dtbs_check` (see
> >> Documentation/devicetree/bindings/writing-schema.rst for instructions).
> >>
> >>>
> >>> Changes since v1:
> >>> - Dropped gmu_pdc_seq region from &gmu, as it shouldn't have been used.
> >>> - Added missing compatible to &adreno_smmu.
> >>> - Dropped aoss_qmp clock in &gmu and &adreno_smmu.
> >>>
> >>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 +
> >>> 1 file changed, 169 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> index d2a2224d138a..329ec2119ecf 100644
> >>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >>> @@ -6,6 +6,7 @@
> >>>
> >>> #include
> >>> #include
> >>> +#include
> >>> #include
> >>> #include
> >>> #include
> >>> @@ -2331,6 +2332,174 @@ tcsr: syscon@1fc {
> >>> reg = <0x0 0x01fc 0x0 0x3>;
> >>> };
> >>>
> >>> + gpu: gpu@3d0 {
> >>> + compatible = "qcom,adreno-690.0", "qcom,adreno";
> >>> +
> >>> + reg = <0 0x03d0 0 0x4>,
> >>> + <0 0x03d9e000 0 0x1000>,
> >>> + <0 0x03d61000 0 0x800>;
> >>> + reg-names = "kgsl_3d0_reg_memory",
> >>> + "cx_mem",
> >>> + "cx_dbgc";
> >>> + interrupts = ;
> >>> + iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>;
> >>> + operating-points-v2 = <&gpu_opp_table>;
> >>> +
> >>> + qcom,gmu = <&gmu>;
> >>> + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt
> >>> SLAVE_EBI1 0>;
> >>> + interconnect-names = "gfx-mem";
> >>> + #cooling-cells = <2>;
> >>> +
> >>> + status = "disabled";
> >>> +
> >>> + gpu_opp_table: opp-table {
> >>> + compatible = "operating-points-v2";
> >>> +
> >>> + opp-27000 {
> >>> + opp-hz = /bits/ 64 <27000>;
> >>> + opp-level =
> >>> ;
> >>> + opp-peak-kBps = <451000>;
> >>> + };
> >>> +
> >>> + opp-41000 {
> >>> + opp-hz = /bits/ 64 <41000>;
> >>> + opp-level = ;
> >>> + opp-peak-kBps = <1555000>;
> >>> + };
> >>> +
> >>> + opp-5 {
> >>> + opp-hz = /bits/ 64 <5>;
> >>> + opp-level =
> >>> ;
> >>> + opp-peak-kBps = <1555000>;
> >>> + };
> >>> +
> >>> + opp-54700 {
> >>> + opp-hz = /bits/ 64 <54700>;
> >>> + opp-level =
> >>> ;
> >>> + opp-peak-kBps = <1555000>;
> >>> + };
> >>> +
> >>> + opp-60600 {
> >>> + opp-hz = /bits/ 64 <60600>;
> >>> + opp-level = ;
> >>> + opp-peak-kBps = <2736000>;
> >>> + };
> >>> +
> >>> + opp-64000 {
> >>> + opp-hz = /bits/ 64 <64000>;
> >>> + opp-level =
> >>> ;
> >>> + opp-peak-kBps = <2736000>;
> >>> + };
> >>> +
> >>> + opp-69000 {
> >>> + opp-hz = /bits/ 64 <69000>;
> >>> + opp-level =
> >>> ;
> >>> + opp-peak-kBps = <2736000>;
> >>> + };
> >>> + };
> >>> + };
> >>> +
> >>> + gmu: gmu@3d6a000 {
> >>> + compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
> >>> + reg = <0 0x03d6a000 0 0x34000>,
> >>> + <0 0x03de 0 0x1>,
> >>> + <0 0x0b29 0 0x1>;
> >>> + reg-names = "gmu", "rscc", "gmu_pdc";
> >>> +
Re: [PATCH v2 2/3] arm64: dts: qcom: sc8280xp: Add GPU related nodes
On 28.05.2023 19:07, Manivannan Sadhasivam wrote:
> On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
>>
>>
>> On 23.05.2023 03:15, Bjorn Andersson wrote:
>>> From: Bjorn Andersson
>>>
>>> Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
>>> SC8280XP.
>>>
>>> Signed-off-by: Bjorn Andersson
>>> Signed-off-by: Bjorn Andersson
>>> ---
>> It does not look like you tested the DTS against bindings. Please run
>> `make dtbs_check` (see
>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>>
>>>
>>> Changes since v1:
>>> - Dropped gmu_pdc_seq region from &gmu, as it shouldn't have been used.
>>> - Added missing compatible to &adreno_smmu.
>>> - Dropped aoss_qmp clock in &gmu and &adreno_smmu.
>>>
>>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 +
>>> 1 file changed, 169 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> index d2a2224d138a..329ec2119ecf 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> @@ -6,6 +6,7 @@
>>>
>>> #include
>>> #include
>>> +#include
>>> #include
>>> #include
>>> #include
>>> @@ -2331,6 +2332,174 @@ tcsr: syscon@1fc {
>>> reg = <0x0 0x01fc 0x0 0x3>;
>>> };
>>>
>>> + gpu: gpu@3d0 {
>>> + compatible = "qcom,adreno-690.0", "qcom,adreno";
>>> +
>>> + reg = <0 0x03d0 0 0x4>,
>>> + <0 0x03d9e000 0 0x1000>,
>>> + <0 0x03d61000 0 0x800>;
>>> + reg-names = "kgsl_3d0_reg_memory",
>>> + "cx_mem",
>>> + "cx_dbgc";
>>> + interrupts = ;
>>> + iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>;
>>> + operating-points-v2 = <&gpu_opp_table>;
>>> +
>>> + qcom,gmu = <&gmu>;
>>> + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt
>>> SLAVE_EBI1 0>;
>>> + interconnect-names = "gfx-mem";
>>> + #cooling-cells = <2>;
>>> +
>>> + status = "disabled";
>>> +
>>> + gpu_opp_table: opp-table {
>>> + compatible = "operating-points-v2";
>>> +
>>> + opp-27000 {
>>> + opp-hz = /bits/ 64 <27000>;
>>> + opp-level =
>>> ;
>>> + opp-peak-kBps = <451000>;
>>> + };
>>> +
>>> + opp-41000 {
>>> + opp-hz = /bits/ 64 <41000>;
>>> + opp-level = ;
>>> + opp-peak-kBps = <1555000>;
>>> + };
>>> +
>>> + opp-5 {
>>> + opp-hz = /bits/ 64 <5>;
>>> + opp-level =
>>> ;
>>> + opp-peak-kBps = <1555000>;
>>> + };
>>> +
>>> + opp-54700 {
>>> + opp-hz = /bits/ 64 <54700>;
>>> + opp-level =
>>> ;
>>> + opp-peak-kBps = <1555000>;
>>> + };
>>> +
>>> + opp-60600 {
>>> + opp-hz = /bits/ 64 <60600>;
>>> + opp-level = ;
>>> + opp-peak-kBps = <2736000>;
>>> + };
>>> +
>>> + opp-64000 {
>>> + opp-hz = /bits/ 64 <64000>;
>>> + opp-level =
>>> ;
>>> + opp-peak-kBps = <2736000>;
>>> + };
>>> +
>>> + opp-69000 {
>>> + opp-hz = /bits/ 64 <69000>;
>>> + opp-level =
>>> ;
>>> + opp-peak-kBps = <2736000>;
>>> + };
>>> + };
>>> + };
>>> +
>>> + gmu: gmu@3d6a000 {
>>> + compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
>>> + reg = <0 0x03d6a000 0 0x34000>,
>>> + <0 0x03de 0 0x1>,
>>> + <0 0x0b29 0 0x1>;
>>> + reg-names = "gmu", "rscc", "gmu_pdc";
>>> + interrupts = ,
>>> +;
>>> + interrupt-names = "hfi", "gmu";
>>> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
Re: [PATCH v2 2/3] arm64: dts: qcom: sc8280xp: Add GPU related nodes
On Tue, May 23, 2023 at 09:59:53AM +0200, Konrad Dybcio wrote:
>
>
> On 23.05.2023 03:15, Bjorn Andersson wrote:
> > From: Bjorn Andersson
> >
> > Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
> > SC8280XP.
> >
> > Signed-off-by: Bjorn Andersson
> > Signed-off-by: Bjorn Andersson
> > ---
> It does not look like you tested the DTS against bindings. Please run
> `make dtbs_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>
> >
> > Changes since v1:
> > - Dropped gmu_pdc_seq region from &gmu, as it shouldn't have been used.
> > - Added missing compatible to &adreno_smmu.
> > - Dropped aoss_qmp clock in &gmu and &adreno_smmu.
> >
> > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 +
> > 1 file changed, 169 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > index d2a2224d138a..329ec2119ecf 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > @@ -6,6 +6,7 @@
> >
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -2331,6 +2332,174 @@ tcsr: syscon@1fc {
> > reg = <0x0 0x01fc 0x0 0x3>;
> > };
> >
> > + gpu: gpu@3d0 {
> > + compatible = "qcom,adreno-690.0", "qcom,adreno";
> > +
> > + reg = <0 0x03d0 0 0x4>,
> > + <0 0x03d9e000 0 0x1000>,
> > + <0 0x03d61000 0 0x800>;
> > + reg-names = "kgsl_3d0_reg_memory",
> > + "cx_mem",
> > + "cx_dbgc";
> > + interrupts = ;
> > + iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>;
> > + operating-points-v2 = <&gpu_opp_table>;
> > +
> > + qcom,gmu = <&gmu>;
> > + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt
> > SLAVE_EBI1 0>;
> > + interconnect-names = "gfx-mem";
> > + #cooling-cells = <2>;
> > +
> > + status = "disabled";
> > +
> > + gpu_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > +
> > + opp-27000 {
> > + opp-hz = /bits/ 64 <27000>;
> > + opp-level =
> > ;
> > + opp-peak-kBps = <451000>;
> > + };
> > +
> > + opp-41000 {
> > + opp-hz = /bits/ 64 <41000>;
> > + opp-level = ;
> > + opp-peak-kBps = <1555000>;
> > + };
> > +
> > + opp-5 {
> > + opp-hz = /bits/ 64 <5>;
> > + opp-level =
> > ;
> > + opp-peak-kBps = <1555000>;
> > + };
> > +
> > + opp-54700 {
> > + opp-hz = /bits/ 64 <54700>;
> > + opp-level =
> > ;
> > + opp-peak-kBps = <1555000>;
> > + };
> > +
> > + opp-60600 {
> > + opp-hz = /bits/ 64 <60600>;
> > + opp-level = ;
> > + opp-peak-kBps = <2736000>;
> > + };
> > +
> > + opp-64000 {
> > + opp-hz = /bits/ 64 <64000>;
> > + opp-level =
> > ;
> > + opp-peak-kBps = <2736000>;
> > + };
> > +
> > + opp-69000 {
> > + opp-hz = /bits/ 64 <69000>;
> > + opp-level =
> > ;
> > + opp-peak-kBps = <2736000>;
> > + };
> > + };
> > + };
> > +
> > + gmu: gmu@3d6a000 {
> > + compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
> > + reg = <0 0x03d6a000 0 0x34000>,
> > + <0 0x03de 0 0x1>,
> > + <0 0x0b29 0 0x1>;
> > + reg-names = "gmu", "rscc", "gmu_pdc";
> > + interrupts = ,
> > +;
> > + interrupt-names = "hfi", "gmu";
> > + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> > +<&gpucc GPU_CC_CXO_CLK
Re: [PATCH v2 2/3] arm64: dts: qcom: sc8280xp: Add GPU related nodes
On 23.05.2023 09:59, Konrad Dybcio wrote:
>
>
> On 23.05.2023 03:15, Bjorn Andersson wrote:
>> From: Bjorn Andersson
>>
>> Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
>> SC8280XP.
>>
>> Signed-off-by: Bjorn Andersson
>> Signed-off-by: Bjorn Andersson
>> ---
> It does not look like you tested the DTS against bindings. Please run
> `make dtbs_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>
>>
>> Changes since v1:
>> - Dropped gmu_pdc_seq region from &gmu, as it shouldn't have been used.
>> - Added missing compatible to &adreno_smmu.
>> - Dropped aoss_qmp clock in &gmu and &adreno_smmu.
>>
>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 +
>> 1 file changed, 169 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> index d2a2224d138a..329ec2119ecf 100644
>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> @@ -6,6 +6,7 @@
>>
>> #include
>> #include
>> +#include
>> #include
>> #include
>> #include
>> @@ -2331,6 +2332,174 @@ tcsr: syscon@1fc {
>> reg = <0x0 0x01fc 0x0 0x3>;
>> };
>>
>> +gpu: gpu@3d0 {
>> +compatible = "qcom,adreno-690.0", "qcom,adreno";
>> +
>> +reg = <0 0x03d0 0 0x4>,
>> + <0 0x03d9e000 0 0x1000>,
>> + <0 0x03d61000 0 0x800>;
>> +reg-names = "kgsl_3d0_reg_memory",
>> +"cx_mem",
>> +"cx_dbgc";
>> +interrupts = ;
>> +iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>;
>> +operating-points-v2 = <&gpu_opp_table>;
>> +
>> +qcom,gmu = <&gmu>;
>> +interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt
>> SLAVE_EBI1 0>;
>> +interconnect-names = "gfx-mem";
I also noticed downstream adds additional votes for L3 (*not* LLCC), should
we explore that?
Konrad
>> +#cooling-cells = <2>;
>> +
>> +status = "disabled";
>> +
>> +gpu_opp_table: opp-table {
>> +compatible = "operating-points-v2";
>> +
>> +opp-27000 {
>> +opp-hz = /bits/ 64 <27000>;
>> +opp-level =
>> ;
>> +opp-peak-kBps = <451000>;
>> +};
>> +
>> +opp-41000 {
>> +opp-hz = /bits/ 64 <41000>;
>> +opp-level = ;
>> +opp-peak-kBps = <1555000>;
>> +};
>> +
>> +opp-5 {
>> +opp-hz = /bits/ 64 <5>;
>> +opp-level =
>> ;
>> +opp-peak-kBps = <1555000>;
>> +};
>> +
>> +opp-54700 {
>> +opp-hz = /bits/ 64 <54700>;
>> +opp-level =
>> ;
>> +opp-peak-kBps = <1555000>;
>> +};
>> +
>> +opp-60600 {
>> +opp-hz = /bits/ 64 <60600>;
>> +opp-level = ;
>> +opp-peak-kBps = <2736000>;
>> +};
>> +
>> +opp-64000 {
>> +opp-hz = /bits/ 64 <64000>;
>> +opp-level =
>> ;
>> +opp-peak-kBps = <2736000>;
>> +};
>> +
>> +opp-69000 {
>> +opp-hz = /bits/ 64 <69000>;
>> +opp-level =
>> ;
>> +opp-peak-kBps = <2736000>;
>> +};
>> +};
>> +};
>> +
>> +gmu: gmu@3d6a000 {
>> +compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
>> +reg = <0 0x03d6a000 0 0x34000>,
>> + <0 0x03de 0 0x1>,
>> + <0 0x0b29 0 0x1>;
>> +reg-names = "gmu", "rscc", "gmu_pdc";
>> +interrupts = ,
>> + ;
>> +interrupt-names = "hfi", "gmu";
>> +clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
>> +
Re: [PATCH v2 2/3] arm64: dts: qcom: sc8280xp: Add GPU related nodes
On 23.05.2023 03:15, Bjorn Andersson wrote:
> From: Bjorn Andersson
>
> Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
> SC8280XP.
>
> Signed-off-by: Bjorn Andersson
> Signed-off-by: Bjorn Andersson
> ---
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
>
> Changes since v1:
> - Dropped gmu_pdc_seq region from &gmu, as it shouldn't have been used.
> - Added missing compatible to &adreno_smmu.
> - Dropped aoss_qmp clock in &gmu and &adreno_smmu.
>
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 +
> 1 file changed, 169 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index d2a2224d138a..329ec2119ecf 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -6,6 +6,7 @@
>
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -2331,6 +2332,174 @@ tcsr: syscon@1fc {
> reg = <0x0 0x01fc 0x0 0x3>;
> };
>
> + gpu: gpu@3d0 {
> + compatible = "qcom,adreno-690.0", "qcom,adreno";
> +
> + reg = <0 0x03d0 0 0x4>,
> + <0 0x03d9e000 0 0x1000>,
> + <0 0x03d61000 0 0x800>;
> + reg-names = "kgsl_3d0_reg_memory",
> + "cx_mem",
> + "cx_dbgc";
> + interrupts = ;
> + iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>;
> + operating-points-v2 = <&gpu_opp_table>;
> +
> + qcom,gmu = <&gmu>;
> + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt
> SLAVE_EBI1 0>;
> + interconnect-names = "gfx-mem";
> + #cooling-cells = <2>;
> +
> + status = "disabled";
> +
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-27000 {
> + opp-hz = /bits/ 64 <27000>;
> + opp-level =
> ;
> + opp-peak-kBps = <451000>;
> + };
> +
> + opp-41000 {
> + opp-hz = /bits/ 64 <41000>;
> + opp-level = ;
> + opp-peak-kBps = <1555000>;
> + };
> +
> + opp-5 {
> + opp-hz = /bits/ 64 <5>;
> + opp-level =
> ;
> + opp-peak-kBps = <1555000>;
> + };
> +
> + opp-54700 {
> + opp-hz = /bits/ 64 <54700>;
> + opp-level =
> ;
> + opp-peak-kBps = <1555000>;
> + };
> +
> + opp-60600 {
> + opp-hz = /bits/ 64 <60600>;
> + opp-level = ;
> + opp-peak-kBps = <2736000>;
> + };
> +
> + opp-64000 {
> + opp-hz = /bits/ 64 <64000>;
> + opp-level =
> ;
> + opp-peak-kBps = <2736000>;
> + };
> +
> + opp-69000 {
> + opp-hz = /bits/ 64 <69000>;
> + opp-level =
> ;
> + opp-peak-kBps = <2736000>;
> + };
> + };
> + };
> +
> + gmu: gmu@3d6a000 {
> + compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
> + reg = <0 0x03d6a000 0 0x34000>,
> + <0 0x03de 0 0x1>,
> + <0 0x0b29 0 0x1>;
> + reg-names = "gmu", "rscc", "gmu_pdc";
> + interrupts = ,
> + ;
> + interrupt-names = "hfi", "gmu";
> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_CXO_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gpucc GPU_C
[PATCH v2 2/3] arm64: dts: qcom: sc8280xp: Add GPU related nodes
From: Bjorn Andersson
Add Adreno SMMU, GPU clock controller, GMU and GPU nodes for the
SC8280XP.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v1:
- Dropped gmu_pdc_seq region from &gmu, as it shouldn't have been used.
- Added missing compatible to &adreno_smmu.
- Dropped aoss_qmp clock in &gmu and &adreno_smmu.
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 169 +
1 file changed, 169 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index d2a2224d138a..329ec2119ecf 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -6,6 +6,7 @@
#include
#include
+#include
#include
#include
#include
@@ -2331,6 +2332,174 @@ tcsr: syscon@1fc {
reg = <0x0 0x01fc 0x0 0x3>;
};
+ gpu: gpu@3d0 {
+ compatible = "qcom,adreno-690.0", "qcom,adreno";
+
+ reg = <0 0x03d0 0 0x4>,
+ <0 0x03d9e000 0 0x1000>,
+ <0 0x03d61000 0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+ interrupts = ;
+ iommus = <&adreno_smmu 0 0xc00>, <&adreno_smmu 1 0xc00>;
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+ interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt
SLAVE_EBI1 0>;
+ interconnect-names = "gfx-mem";
+ #cooling-cells = <2>;
+
+ status = "disabled";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-27000 {
+ opp-hz = /bits/ 64 <27000>;
+ opp-level =
;
+ opp-peak-kBps = <451000>;
+ };
+
+ opp-41000 {
+ opp-hz = /bits/ 64 <41000>;
+ opp-level = ;
+ opp-peak-kBps = <1555000>;
+ };
+
+ opp-5 {
+ opp-hz = /bits/ 64 <5>;
+ opp-level =
;
+ opp-peak-kBps = <1555000>;
+ };
+
+ opp-54700 {
+ opp-hz = /bits/ 64 <54700>;
+ opp-level =
;
+ opp-peak-kBps = <1555000>;
+ };
+
+ opp-60600 {
+ opp-hz = /bits/ 64 <60600>;
+ opp-level = ;
+ opp-peak-kBps = <2736000>;
+ };
+
+ opp-64000 {
+ opp-hz = /bits/ 64 <64000>;
+ opp-level =
;
+ opp-peak-kBps = <2736000>;
+ };
+
+ opp-69000 {
+ opp-hz = /bits/ 64 <69000>;
+ opp-level =
;
+ opp-peak-kBps = <2736000>;
+ };
+ };
+ };
+
+ gmu: gmu@3d6a000 {
+ compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
+ reg = <0 0x03d6a000 0 0x34000>,
+ <0 0x03de 0 0x1>,
+ <0 0x0b29 0 0x1>;
+ reg-names = "gmu", "rscc", "gmu_pdc";
+ interrupts = ,
+;
+ interrupt-names = "hfi", "gmu";
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+<&gpucc GPU_CC_CXO_CLK>,
+<&gcc GCC_DDRSS_GPU_AXI_CLK>,
+<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+<&gpucc GPU_CC_AHB_CLK>,
+<&gpucc GPU_CC_HUB_CX_INT_CLK>,
+<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+
