Re: [PATCH v2 9/9] drm/i915: Add render decompression support

[Ville Syrjälä]

On Wed, Mar 01, 2017 at 09:50:56AM -0800, Ben Widawsky wrote:
> On 17-03-01 12:51:17, Ville Syrjälä wrote:
> >On Tue, Feb 28, 2017 at 03:20:38PM -0800, Ben Widawsky wrote:
> >> On 17-02-28 12:18:39, Jason Ekstrand wrote:
> >
> >> >I've said it before but reading through Ben's patches again make me want 
> >> >to
> >> >be peskier about it.  I would really like the UABI to treat the CCS as if
> >> >it's Y-tiled with a tile size of 128B x 32 rows.  Why?  Because this is
> >> >what all the docs say it is.  From the display docs for "Color Control
> >> >Surface":
> >> >
> >> >"The Color Control Surface (CCS) contains the compression status of the
> >> >cache-line pairs. The
> >> >compression state of the cache-line pair is specified by 2 bits in the 
> >> >CCS.
> >> >Each CCS cache-line represents
> >> >an area on the main surface of 16 x16 sets of 128 byte Y-tiled
> >> >cache-line-pairs. CCS is always Y tiled."
> >> >
> >> >This contains 95% of the information needed to know the relation between
> >> >the CCS and the main surface.  The other 5% (which is badly documented) is
> >> >that cache line pairs are horizontally adjacent.  This gives a 
> >> >relationship
> >> >of one cache line in the CCS maps to 32x64 cache lines in the main 
> >> >surface.
> >> >
> >> >But it's not actually Y-tiled?  Of course not.  I've worked out the exact
> >> >tiling and it looks something like Y but isn't quite the same.  However,
> >> >this isn't unique to CCS.  Stencil (W-tiled), HiZ, and gen7-8
> >> >single-sampled MCS also each have their own tiling (Haswell MCS is
> >> >especially exotic) but the docs call all of them Y-tiled and I think the
> >> >hardware internally treats them as Y-tiled with the cache lines shuffled
> >> >around a bit.
> >> >
> >> >Given the fact that they seem to like to change the MCS/CCS tiling around
> >> >on every hardware generation, I'm reluctant to base UABI on the fact that
> >> >the CCS appears to have 64x64 "pixels" per tile with each "pixel"
> >> >corresponding to 16x8 pixels in the color surface.  That's not what we had
> >> >on any previous gen and may change on gen10 for no aparent reason.  I'd
> >> >much rather base it on Y-tiling and a relationship between cache lines
> >> >which, even if they change the exact swizzle on gen10, will probably 
> >> >remain
> >> >the same.  (For the gen7-8 analogue of CCS, they changed the tiling every
> >> >generation but the relationship of one MCS cache line maps to 32x128 color
> >> >cache lines remained the same).
> >> >
> >> >Ok, I've said my peice.  If we have to divide by 2 in userspace, we won't
> >> >die, but I'd like to get the UABI right before we chissel it in stone.
> >> >
> >> >--Jason
> >> >
> >> >
> >>
> >> I vote we make the stride in units of tiles when we have the CCS modifier.
> >
> >That won't fly with the KMS API. I suppose I could make the tile 128 bytes
> >wide by swapping the "1 byte == 16x8 pixels" notion with a
> >"1 byte == 8x16 pixels" notion. Doesn't match the actual truth anymore,
> >but I guess no one really cares.
> >
> 
> KMS API goes right out the window with modifiers. Isn't that really the whole
> point of modifiers?

Not in my opinion. It's just a mild extension. The basics still apply
perfectly fine. 

And I really don't want to add special exceptions for CCS since
that'll just mean more code and more bugs. Right now the same code
that works for your typical planar formats works for CCS as well.

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v2 9/9] drm/i915: Add render decompression support

[Ben Widawsky]

On 17-03-01 12:51:17, Ville Syrjälä wrote:

On Tue, Feb 28, 2017 at 03:20:38PM -0800, Ben Widawsky wrote:

On 17-02-28 12:18:39, Jason Ekstrand wrote:



>I've said it before but reading through Ben's patches again make me want to
>be peskier about it.  I would really like the UABI to treat the CCS as if
>it's Y-tiled with a tile size of 128B x 32 rows.  Why?  Because this is
>what all the docs say it is.  From the display docs for "Color Control
>Surface":
>
>"The Color Control Surface (CCS) contains the compression status of the
>cache-line pairs. The
>compression state of the cache-line pair is specified by 2 bits in the CCS.
>Each CCS cache-line represents
>an area on the main surface of 16 x16 sets of 128 byte Y-tiled
>cache-line-pairs. CCS is always Y tiled."
>
>This contains 95% of the information needed to know the relation between
>the CCS and the main surface.  The other 5% (which is badly documented) is
>that cache line pairs are horizontally adjacent.  This gives a relationship
>of one cache line in the CCS maps to 32x64 cache lines in the main surface.
>
>But it's not actually Y-tiled?  Of course not.  I've worked out the exact
>tiling and it looks something like Y but isn't quite the same.  However,
>this isn't unique to CCS.  Stencil (W-tiled), HiZ, and gen7-8
>single-sampled MCS also each have their own tiling (Haswell MCS is
>especially exotic) but the docs call all of them Y-tiled and I think the
>hardware internally treats them as Y-tiled with the cache lines shuffled
>around a bit.
>
>Given the fact that they seem to like to change the MCS/CCS tiling around
>on every hardware generation, I'm reluctant to base UABI on the fact that
>the CCS appears to have 64x64 "pixels" per tile with each "pixel"
>corresponding to 16x8 pixels in the color surface.  That's not what we had
>on any previous gen and may change on gen10 for no aparent reason.  I'd
>much rather base it on Y-tiling and a relationship between cache lines
>which, even if they change the exact swizzle on gen10, will probably remain
>the same.  (For the gen7-8 analogue of CCS, they changed the tiling every
>generation but the relationship of one MCS cache line maps to 32x128 color
>cache lines remained the same).
>
>Ok, I've said my peice.  If we have to divide by 2 in userspace, we won't
>die, but I'd like to get the UABI right before we chissel it in stone.
>
>--Jason
>
>

I vote we make the stride in units of tiles when we have the CCS modifier.


That won't fly with the KMS API. I suppose I could make the tile 128 bytes
wide by swapping the "1 byte == 16x8 pixels" notion with a
"1 byte == 8x16 pixels" notion. Doesn't match the actual truth anymore,
but I guess no one really cares.



KMS API goes right out the window with modifiers. Isn't that really the whole
point of modifiers?



>> +   /* fall through */
>> case I915_FORMAT_MOD_Yf_TILED:
>> /*
>>  * Bspec seems to suggest that the Yf tile width would
>> @@ -2156,7 +2164,7 @@ static unsigned int intel_surf_alignment(const
>> struct drm_framebuffer *fb,
>> struct drm_i915_private *dev_priv = to_i915(fb->dev);
>>
>> /* AUX_DIST needs only 4K alignment */
>> -   if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
>> +   if (plane == 1)
>> return 4096;
>>
>> switch (fb->modifier) {
>> @@ -2166,6 +2174,8 @@ static unsigned int intel_surf_alignment(const
>> struct drm_framebuffer *fb,
>> if (INTEL_GEN(dev_priv) >= 9)
>> return 256 * 1024;
>> return 0;
>> +   case I915_FORMAT_MOD_Y_TILED_CCS:
>> +   case I915_FORMAT_MOD_Yf_TILED_CCS:
>> case I915_FORMAT_MOD_Y_TILED:
>> case I915_FORMAT_MOD_Yf_TILED:
>> return 1 * 1024 * 1024;
>> @@ -2472,6 +2482,7 @@ static unsigned int 
intel_fb_modifier_to_tiling(uint64_t
>> fb_modifier)
>> case I915_FORMAT_MOD_X_TILED:
>> return I915_TILING_X;
>> case I915_FORMAT_MOD_Y_TILED:
>> +   case I915_FORMAT_MOD_Y_TILED_CCS:
>> return I915_TILING_Y;
>> default:
>> return I915_TILING_NONE;
>> @@ -2536,6 +2547,35 @@ intel_fill_fb_info(struct drm_i915_private
>> *dev_priv,
>>
>> intel_fb_offset_to_xy(, , fb, i);
>>
>> +   if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>> +fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i ==
>> 1) {
>> +   int main_x, main_y;
>> +   int ccs_x, ccs_y;
>> +
>> +   /*
>> +* Each byte of CCS corresponds to a 16x8 area of
>> the main surface, and
>> +* each CCS tile is 64x64 bytes.
>> +*/
>> +   ccs_x = (x * 16) % (64 * 16);
>> +   ccs_y = (y * 8) % (64 * 8);
>> +   main_x = intel_fb->normal[0].x % (64 * 16);
>> + 

Re: [PATCH v2 9/9] drm/i915: Add render decompression support

[Ville Syrjälä]

On Tue, Feb 28, 2017 at 03:20:38PM -0800, Ben Widawsky wrote:
> On 17-02-28 12:18:39, Jason Ekstrand wrote:

> >I've said it before but reading through Ben's patches again make me want to
> >be peskier about it.  I would really like the UABI to treat the CCS as if
> >it's Y-tiled with a tile size of 128B x 32 rows.  Why?  Because this is
> >what all the docs say it is.  From the display docs for "Color Control
> >Surface":
> >
> >"The Color Control Surface (CCS) contains the compression status of the
> >cache-line pairs. The
> >compression state of the cache-line pair is specified by 2 bits in the CCS.
> >Each CCS cache-line represents
> >an area on the main surface of 16 x16 sets of 128 byte Y-tiled
> >cache-line-pairs. CCS is always Y tiled."
> >
> >This contains 95% of the information needed to know the relation between
> >the CCS and the main surface.  The other 5% (which is badly documented) is
> >that cache line pairs are horizontally adjacent.  This gives a relationship
> >of one cache line in the CCS maps to 32x64 cache lines in the main surface.
> >
> >But it's not actually Y-tiled?  Of course not.  I've worked out the exact
> >tiling and it looks something like Y but isn't quite the same.  However,
> >this isn't unique to CCS.  Stencil (W-tiled), HiZ, and gen7-8
> >single-sampled MCS also each have their own tiling (Haswell MCS is
> >especially exotic) but the docs call all of them Y-tiled and I think the
> >hardware internally treats them as Y-tiled with the cache lines shuffled
> >around a bit.
> >
> >Given the fact that they seem to like to change the MCS/CCS tiling around
> >on every hardware generation, I'm reluctant to base UABI on the fact that
> >the CCS appears to have 64x64 "pixels" per tile with each "pixel"
> >corresponding to 16x8 pixels in the color surface.  That's not what we had
> >on any previous gen and may change on gen10 for no aparent reason.  I'd
> >much rather base it on Y-tiling and a relationship between cache lines
> >which, even if they change the exact swizzle on gen10, will probably remain
> >the same.  (For the gen7-8 analogue of CCS, they changed the tiling every
> >generation but the relationship of one MCS cache line maps to 32x128 color
> >cache lines remained the same).
> >
> >Ok, I've said my peice.  If we have to divide by 2 in userspace, we won't
> >die, but I'd like to get the UABI right before we chissel it in stone.
> >
> >--Jason
> >
> >
> 
> I vote we make the stride in units of tiles when we have the CCS modifier.

That won't fly with the KMS API. I suppose I could make the tile 128 bytes
wide by swapping the "1 byte == 16x8 pixels" notion with a
"1 byte == 8x16 pixels" notion. Doesn't match the actual truth anymore,
but I guess no one really cares.

> 
> >> +   /* fall through */
> >> case I915_FORMAT_MOD_Yf_TILED:
> >> /*
> >>  * Bspec seems to suggest that the Yf tile width would
> >> @@ -2156,7 +2164,7 @@ static unsigned int intel_surf_alignment(const
> >> struct drm_framebuffer *fb,
> >> struct drm_i915_private *dev_priv = to_i915(fb->dev);
> >>
> >> /* AUX_DIST needs only 4K alignment */
> >> -   if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
> >> +   if (plane == 1)
> >> return 4096;
> >>
> >> switch (fb->modifier) {
> >> @@ -2166,6 +2174,8 @@ static unsigned int intel_surf_alignment(const
> >> struct drm_framebuffer *fb,
> >> if (INTEL_GEN(dev_priv) >= 9)
> >> return 256 * 1024;
> >> return 0;
> >> +   case I915_FORMAT_MOD_Y_TILED_CCS:
> >> +   case I915_FORMAT_MOD_Yf_TILED_CCS:
> >> case I915_FORMAT_MOD_Y_TILED:
> >> case I915_FORMAT_MOD_Yf_TILED:
> >> return 1 * 1024 * 1024;
> >> @@ -2472,6 +2482,7 @@ static unsigned int 
> >> intel_fb_modifier_to_tiling(uint64_t
> >> fb_modifier)
> >> case I915_FORMAT_MOD_X_TILED:
> >> return I915_TILING_X;
> >> case I915_FORMAT_MOD_Y_TILED:
> >> +   case I915_FORMAT_MOD_Y_TILED_CCS:
> >> return I915_TILING_Y;
> >> default:
> >> return I915_TILING_NONE;
> >> @@ -2536,6 +2547,35 @@ intel_fill_fb_info(struct drm_i915_private
> >> *dev_priv,
> >>
> >> intel_fb_offset_to_xy(, , fb, i);
> >>
> >> +   if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> >> +fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i ==
> >> 1) {
> >> +   int main_x, main_y;
> >> +   int ccs_x, ccs_y;
> >> +
> >> +   /*
> >> +* Each byte of CCS corresponds to a 16x8 area of
> >> the main surface, and
> >> +* each CCS tile is 64x64 bytes.
> >> +*/
> >> +   ccs_x = (x * 16) % (64 * 16);
> >> +   ccs_y = (y * 8) % (64 * 8);
> >> +

Re: [PATCH v2 9/9] drm/i915: Add render decompression support

[Jason Ekstrand]

On Thu, Jan 5, 2017 at 7:14 AM,  wrote:

> From: Ville Syrjälä 
>
> SKL+ display engine can scan out certain kinds of compressed surfaces
> produced by the render engine. This involved telling the display engine
> the location of the color control surfae (CCS) which describes
> which parts of the main surface are compressed and which are not. The
> location of CCS is provided by userspace as just another plane with its
> own offset.
>
> Add the required stuff to validate the user provided AUX plane metadata
> and convert the user provided linear offset into something the hardware
> can consume.
>
> Due to hardware limitations we require that the main surface and
> the AUX surface (CCS) be part of the same bo. The hardware also
> makes life hard by not allowing you to provide separate x/y offsets
> for the main and AUX surfaces (excpet with NV12), so finding suitable
> offsets for both requires a bit of work. Assuming we still want keep
> playing tricks with the offsets. I've just gone with a dumb "search
> backward for suitable offsets" approach, which is far from optimal,
> but it works.
>
> Also not all planes will be capable of scanning out compressed surfaces,
> and eg. 90/270 degree rotation is not supported in combination with
> decompression either.
>
> This patch may contain work from at least the following people:
> * Vandana Kannan 
> * Daniel Vetter 
> * Ben Widawsky 
>
> v2: Deal with display workarounds 0390, 0531, 1125 (Paulo)
>
> Cc: Paulo Zanoni 
> Cc: Vandana Kannan 
> Cc: Daniel Vetter 
> Cc: Ben Widawsky 
> Cc: Jason Ekstrand 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  23 
>  drivers/gpu/drm/i915/intel_display.c | 234 ++
> ++---
>  drivers/gpu/drm/i915/intel_pm.c  |  29 -
>  drivers/gpu/drm/i915/intel_sprite.c  |   5 +
>  4 files changed, 274 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_
> reg.h
> index 00970aa77afa..6849ba93f1d9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6209,6 +6209,28 @@ enum {
> _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
> _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
>
> +#define PLANE_AUX_DIST_1_A 0x701c0
> +#define PLANE_AUX_DIST_2_A 0x702c0
> +#define PLANE_AUX_DIST_1_B 0x711c0
> +#define PLANE_AUX_DIST_2_B 0x712c0
> +#define _PLANE_AUX_DIST_1(pipe) \
> +   _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
> +#define _PLANE_AUX_DIST_2(pipe) \
> +   _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
> +#define PLANE_AUX_DIST(pipe, plane) \
> +   _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe),
> _PLANE_AUX_DIST_2(pipe))
> +
> +#define PLANE_AUX_OFFSET_1_A   0x701c4
> +#define PLANE_AUX_OFFSET_2_A   0x702c4
> +#define PLANE_AUX_OFFSET_1_B   0x711c4
> +#define PLANE_AUX_OFFSET_2_B   0x712c4
> +#define _PLANE_AUX_OFFSET_1(pipe)   \
> +   _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
> +#define _PLANE_AUX_OFFSET_2(pipe)   \
> +   _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
> +#define PLANE_AUX_OFFSET(pipe, plane)   \
> +   _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe),
> _PLANE_AUX_OFFSET_2(pipe))
> +
>  /* legacy palette */
>  #define _LGC_PALETTE_A   0x4a000
>  #define _LGC_PALETTE_B   0x4a800
> @@ -6433,6 +6455,7 @@ enum {
>  # define CHICKEN3_DGMG_DONE_FIX_DISABLE(1 << 2)
>
>  #define CHICKEN_PAR1_1 _MMIO(0x42080)
> +#define  SKL_RC_HASH_OUTSIDE   (1 << 15)
>  #define  DPA_MASK_VBLANK_SRD   (1 << 15)
>  #define  FORCE_ARB_IDLE_PLANES (1 << 14)
>  #define  SKL_EDP_PSR_FIX_RDWRAP(1 << 3)
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 38de9df0ec60..2236abebd8bc 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2064,11 +2064,19 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int plane)
> return 128;
> else
> return 512;
> +   case I915_FORMAT_MOD_Y_TILED_CCS:
> +   if (plane == 1)
> +   return 64;
> +   /* fall through */
> case I915_FORMAT_MOD_Y_TILED:
> if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
> return 128;
> else
> return 512;
> +   case I915_FORMAT_MOD_Yf_TILED_CCS:
> +   if (plane == 1)
> +

Re: [PATCH v2 9/9] drm/i915: Add render decompression support

[Ben Widawsky]

On 17-02-28 12:18:39, Jason Ekstrand wrote:

On Thu, Jan 5, 2017 at 7:14 AM,  wrote:


From: Ville Syrjälä 

SKL+ display engine can scan out certain kinds of compressed surfaces
produced by the render engine. This involved telling the display engine
the location of the color control surfae (CCS) which describes
which parts of the main surface are compressed and which are not. The
location of CCS is provided by userspace as just another plane with its
own offset.

Add the required stuff to validate the user provided AUX plane metadata
and convert the user provided linear offset into something the hardware
can consume.

Due to hardware limitations we require that the main surface and
the AUX surface (CCS) be part of the same bo. The hardware also
makes life hard by not allowing you to provide separate x/y offsets
for the main and AUX surfaces (excpet with NV12), so finding suitable
offsets for both requires a bit of work. Assuming we still want keep
playing tricks with the offsets. I've just gone with a dumb "search
backward for suitable offsets" approach, which is far from optimal,
but it works.

Also not all planes will be capable of scanning out compressed surfaces,
and eg. 90/270 degree rotation is not supported in combination with
decompression either.

This patch may contain work from at least the following people:
* Vandana Kannan 
* Daniel Vetter 
* Ben Widawsky 

v2: Deal with display workarounds 0390, 0531, 1125 (Paulo)

Cc: Paulo Zanoni 
Cc: Vandana Kannan 
Cc: Daniel Vetter 
Cc: Ben Widawsky 
Cc: Jason Ekstrand 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  |  23 
 drivers/gpu/drm/i915/intel_display.c | 234 ++
++---
 drivers/gpu/drm/i915/intel_pm.c  |  29 -
 drivers/gpu/drm/i915/intel_sprite.c  |   5 +
 4 files changed, 274 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_
reg.h
index 00970aa77afa..6849ba93f1d9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6209,6 +6209,28 @@ enum {
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))

+#define PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DIST_2_A 0x702c0
+#define PLANE_AUX_DIST_1_B 0x711c0
+#define PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe) \
+   _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe) \
+   _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane) \
+   _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe),
_PLANE_AUX_DIST_2(pipe))
+
+#define PLANE_AUX_OFFSET_1_A   0x701c4
+#define PLANE_AUX_OFFSET_2_A   0x702c4
+#define PLANE_AUX_OFFSET_1_B   0x711c4
+#define PLANE_AUX_OFFSET_2_B   0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe)   \
+   _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe)   \
+   _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane)   \
+   _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe),
_PLANE_AUX_OFFSET_2(pipe))
+
 /* legacy palette */
 #define _LGC_PALETTE_A   0x4a000
 #define _LGC_PALETTE_B   0x4a800
@@ -6433,6 +6455,7 @@ enum {
 # define CHICKEN3_DGMG_DONE_FIX_DISABLE(1 << 2)

 #define CHICKEN_PAR1_1 _MMIO(0x42080)
+#define  SKL_RC_HASH_OUTSIDE   (1 << 15)
 #define  DPA_MASK_VBLANK_SRD   (1 << 15)
 #define  FORCE_ARB_IDLE_PLANES (1 << 14)
 #define  SKL_EDP_PSR_FIX_RDWRAP(1 << 3)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 38de9df0ec60..2236abebd8bc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2064,11 +2064,19 @@ intel_tile_width_bytes(const struct
drm_framebuffer *fb, int plane)
return 128;
else
return 512;
+   case I915_FORMAT_MOD_Y_TILED_CCS:
+   if (plane == 1)
+   return 64;
+   /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
else
return 512;
+   case I915_FORMAT_MOD_Yf_TILED_CCS:
+   if (plane == 1)
+   return 64;



I've said it before but reading through Ben's patches again make me want to
be peskier about it.  I would really like the UABI to treat 

Re: [PATCH v2 9/9] drm/i915: Add render decompression support

[Ben Widawsky]

On 17-02-28 12:18:39, Jason Ekstrand wrote:

On Thu, Jan 5, 2017 at 7:14 AM,  wrote:


From: Ville Syrjälä 

SKL+ display engine can scan out certain kinds of compressed surfaces
produced by the render engine. This involved telling the display engine
the location of the color control surfae (CCS) which describes
which parts of the main surface are compressed and which are not. The
location of CCS is provided by userspace as just another plane with its
own offset.

Add the required stuff to validate the user provided AUX plane metadata
and convert the user provided linear offset into something the hardware
can consume.

Due to hardware limitations we require that the main surface and
the AUX surface (CCS) be part of the same bo. The hardware also
makes life hard by not allowing you to provide separate x/y offsets
for the main and AUX surfaces (excpet with NV12), so finding suitable
offsets for both requires a bit of work. Assuming we still want keep
playing tricks with the offsets. I've just gone with a dumb "search
backward for suitable offsets" approach, which is far from optimal,
but it works.

Also not all planes will be capable of scanning out compressed surfaces,
and eg. 90/270 degree rotation is not supported in combination with
decompression either.

This patch may contain work from at least the following people:
* Vandana Kannan 
* Daniel Vetter 
* Ben Widawsky 

v2: Deal with display workarounds 0390, 0531, 1125 (Paulo)

Cc: Paulo Zanoni 
Cc: Vandana Kannan 
Cc: Daniel Vetter 
Cc: Ben Widawsky 
Cc: Jason Ekstrand 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  |  23 
 drivers/gpu/drm/i915/intel_display.c | 234 ++
++---
 drivers/gpu/drm/i915/intel_pm.c  |  29 -
 drivers/gpu/drm/i915/intel_sprite.c  |   5 +
 4 files changed, 274 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_
reg.h
index 00970aa77afa..6849ba93f1d9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6209,6 +6209,28 @@ enum {
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))

+#define PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DIST_2_A 0x702c0
+#define PLANE_AUX_DIST_1_B 0x711c0
+#define PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe) \
+   _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe) \
+   _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane) \
+   _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe),
_PLANE_AUX_DIST_2(pipe))
+
+#define PLANE_AUX_OFFSET_1_A   0x701c4
+#define PLANE_AUX_OFFSET_2_A   0x702c4
+#define PLANE_AUX_OFFSET_1_B   0x711c4
+#define PLANE_AUX_OFFSET_2_B   0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe)   \
+   _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe)   \
+   _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane)   \
+   _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe),
_PLANE_AUX_OFFSET_2(pipe))
+
 /* legacy palette */
 #define _LGC_PALETTE_A   0x4a000
 #define _LGC_PALETTE_B   0x4a800
@@ -6433,6 +6455,7 @@ enum {
 # define CHICKEN3_DGMG_DONE_FIX_DISABLE(1 << 2)

 #define CHICKEN_PAR1_1 _MMIO(0x42080)
+#define  SKL_RC_HASH_OUTSIDE   (1 << 15)
 #define  DPA_MASK_VBLANK_SRD   (1 << 15)
 #define  FORCE_ARB_IDLE_PLANES (1 << 14)
 #define  SKL_EDP_PSR_FIX_RDWRAP(1 << 3)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 38de9df0ec60..2236abebd8bc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2064,11 +2064,19 @@ intel_tile_width_bytes(const struct
drm_framebuffer *fb, int plane)
return 128;
else
return 512;
+   case I915_FORMAT_MOD_Y_TILED_CCS:
+   if (plane == 1)
+   return 64;
+   /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
else
return 512;
+   case I915_FORMAT_MOD_Yf_TILED_CCS:
+   if (plane == 1)
+   return 64;



I've said it before but reading through Ben's patches again make me want to
be peskier about it.  I would really like the UABI to treat 

Re: [PATCH v2 9/9] drm/i915: Add render decompression support

[Ville Syrjälä]

On Tue, Feb 07, 2017 at 05:37:44PM +0200, Imre Deak wrote:
> On Thu, Jan 05, 2017 at 05:14:54PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä 
> > 
> > SKL+ display engine can scan out certain kinds of compressed surfaces
> > produced by the render engine. This involved telling the display engine
> > the location of the color control surfae (CCS) which describes
> > which parts of the main surface are compressed and which are not. The
> > location of CCS is provided by userspace as just another plane with its
> > own offset.
> > 
> > Add the required stuff to validate the user provided AUX plane metadata
> > and convert the user provided linear offset into something the hardware
> > can consume.
> > 
> > Due to hardware limitations we require that the main surface and
> > the AUX surface (CCS) be part of the same bo. The hardware also
> > makes life hard by not allowing you to provide separate x/y offsets
> > for the main and AUX surfaces (excpet with NV12), so finding suitable
> > offsets for both requires a bit of work. Assuming we still want keep
> > playing tricks with the offsets. I've just gone with a dumb "search
> > backward for suitable offsets" approach, which is far from optimal,
> > but it works.
> > 
> > Also not all planes will be capable of scanning out compressed surfaces,
> > and eg. 90/270 degree rotation is not supported in combination with
> > decompression either.
> > 
> > This patch may contain work from at least the following people:
> > * Vandana Kannan 
> > * Daniel Vetter 
> > * Ben Widawsky 
> > 
> > v2: Deal with display workarounds 0390, 0531, 1125 (Paulo)
> > 
> > Cc: Paulo Zanoni 
> > Cc: Vandana Kannan 
> > Cc: Daniel Vetter 
> > Cc: Ben Widawsky 
> > Cc: Jason Ekstrand 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |  23 
> >  drivers/gpu/drm/i915/intel_display.c | 234 
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c  |  29 -
> >  drivers/gpu/drm/i915/intel_sprite.c  |   5 +
> >  4 files changed, 274 insertions(+), 17 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 00970aa77afa..6849ba93f1d9 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6209,6 +6209,28 @@ enum {
> > _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
> > _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
> >  
> > +#define PLANE_AUX_DIST_1_A 0x701c0
> > +#define PLANE_AUX_DIST_2_A 0x702c0
> > +#define PLANE_AUX_DIST_1_B 0x711c0
> > +#define PLANE_AUX_DIST_2_B 0x712c0
> > +#define _PLANE_AUX_DIST_1(pipe) \
> > +   _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
> > +#define _PLANE_AUX_DIST_2(pipe) \
> > +   _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
> > +#define PLANE_AUX_DIST(pipe, plane) \
> > +   _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
> > +
> > +#define PLANE_AUX_OFFSET_1_A   0x701c4
> > +#define PLANE_AUX_OFFSET_2_A   0x702c4
> > +#define PLANE_AUX_OFFSET_1_B   0x711c4
> > +#define PLANE_AUX_OFFSET_2_B   0x712c4
> > +#define _PLANE_AUX_OFFSET_1(pipe)   \
> > +   _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
> > +#define _PLANE_AUX_OFFSET_2(pipe)   \
> > +   _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
> > +#define PLANE_AUX_OFFSET(pipe, plane)   \
> > +   _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
> > +
> >  /* legacy palette */
> >  #define _LGC_PALETTE_A   0x4a000
> >  #define _LGC_PALETTE_B   0x4a800
> > @@ -6433,6 +6455,7 @@ enum {
> >  # define CHICKEN3_DGMG_DONE_FIX_DISABLE(1 << 2)
> >  
> >  #define CHICKEN_PAR1_1 _MMIO(0x42080)
> > +#define  SKL_RC_HASH_OUTSIDE   (1 << 15)
> >  #define  DPA_MASK_VBLANK_SRD   (1 << 15)
> >  #define  FORCE_ARB_IDLE_PLANES (1 << 14)
> >  #define  SKL_EDP_PSR_FIX_RDWRAP(1 << 3)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 38de9df0ec60..2236abebd8bc 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2064,11 +2064,19 @@ intel_tile_width_bytes(const struct drm_framebuffer 
> > *fb, int plane)
> > return 128;
> > else
> > return 512;
> > +   case I915_FORMAT_MOD_Y_TILED_CCS:
> > +   if (plane == 1)
> > +   return 64;
> > +   /* fall through */
> > case I915_FORMAT_MOD_Y_TILED:
> > if 

Re: [PATCH v2 9/9] drm/i915: Add render decompression support

[Imre Deak]

On Thu, Jan 05, 2017 at 05:14:54PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> SKL+ display engine can scan out certain kinds of compressed surfaces
> produced by the render engine. This involved telling the display engine
> the location of the color control surfae (CCS) which describes
> which parts of the main surface are compressed and which are not. The
> location of CCS is provided by userspace as just another plane with its
> own offset.
> 
> Add the required stuff to validate the user provided AUX plane metadata
> and convert the user provided linear offset into something the hardware
> can consume.
> 
> Due to hardware limitations we require that the main surface and
> the AUX surface (CCS) be part of the same bo. The hardware also
> makes life hard by not allowing you to provide separate x/y offsets
> for the main and AUX surfaces (excpet with NV12), so finding suitable
> offsets for both requires a bit of work. Assuming we still want keep
> playing tricks with the offsets. I've just gone with a dumb "search
> backward for suitable offsets" approach, which is far from optimal,
> but it works.
> 
> Also not all planes will be capable of scanning out compressed surfaces,
> and eg. 90/270 degree rotation is not supported in combination with
> decompression either.
> 
> This patch may contain work from at least the following people:
> * Vandana Kannan 
> * Daniel Vetter 
> * Ben Widawsky 
> 
> v2: Deal with display workarounds 0390, 0531, 1125 (Paulo)
> 
> Cc: Paulo Zanoni 
> Cc: Vandana Kannan 
> Cc: Daniel Vetter 
> Cc: Ben Widawsky 
> Cc: Jason Ekstrand 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  23 
>  drivers/gpu/drm/i915/intel_display.c | 234 
> ---
>  drivers/gpu/drm/i915/intel_pm.c  |  29 -
>  drivers/gpu/drm/i915/intel_sprite.c  |   5 +
>  4 files changed, 274 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 00970aa77afa..6849ba93f1d9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6209,6 +6209,28 @@ enum {
>   _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
>   _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
>  
> +#define PLANE_AUX_DIST_1_A   0x701c0
> +#define PLANE_AUX_DIST_2_A   0x702c0
> +#define PLANE_AUX_DIST_1_B   0x711c0
> +#define PLANE_AUX_DIST_2_B   0x712c0
> +#define _PLANE_AUX_DIST_1(pipe) \
> + _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
> +#define _PLANE_AUX_DIST_2(pipe) \
> + _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
> +#define PLANE_AUX_DIST(pipe, plane) \
> + _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
> +
> +#define PLANE_AUX_OFFSET_1_A 0x701c4
> +#define PLANE_AUX_OFFSET_2_A 0x702c4
> +#define PLANE_AUX_OFFSET_1_B 0x711c4
> +#define PLANE_AUX_OFFSET_2_B 0x712c4
> +#define _PLANE_AUX_OFFSET_1(pipe)   \
> + _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
> +#define _PLANE_AUX_OFFSET_2(pipe)   \
> + _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
> +#define PLANE_AUX_OFFSET(pipe, plane)   \
> + _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
> +
>  /* legacy palette */
>  #define _LGC_PALETTE_A   0x4a000
>  #define _LGC_PALETTE_B   0x4a800
> @@ -6433,6 +6455,7 @@ enum {
>  # define CHICKEN3_DGMG_DONE_FIX_DISABLE  (1 << 2)
>  
>  #define CHICKEN_PAR1_1   _MMIO(0x42080)
> +#define  SKL_RC_HASH_OUTSIDE (1 << 15)
>  #define  DPA_MASK_VBLANK_SRD (1 << 15)
>  #define  FORCE_ARB_IDLE_PLANES   (1 << 14)
>  #define  SKL_EDP_PSR_FIX_RDWRAP  (1 << 3)
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 38de9df0ec60..2236abebd8bc 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2064,11 +2064,19 @@ intel_tile_width_bytes(const struct drm_framebuffer 
> *fb, int plane)
>   return 128;
>   else
>   return 512;
> + case I915_FORMAT_MOD_Y_TILED_CCS:
> + if (plane == 1)
> + return 64;
> + /* fall through */
>   case I915_FORMAT_MOD_Y_TILED:
>   if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
>   return 128;
>   else
>   return 512;
> + case I915_FORMAT_MOD_Yf_TILED_CCS:
> + if (plane == 1)
> + return 64;
> +   

Re: [PATCH v2 9/9] drm/i915: Add render decompression support

[Jason Ekstrand]

On Tue, Jan 10, 2017 at 9:04 AM, Ville Syrjälä <
ville.syrj...@linux.intel.com> wrote:

> On Mon, Jan 09, 2017 at 11:20:57AM -0800, Jason Ekstrand wrote:
> > On Thu, Jan 5, 2017 at 7:14 AM,  wrote:
> >
> > > From: Ville Syrjälä 
> > >
> > > SKL+ display engine can scan out certain kinds of compressed surfaces
> > > produced by the render engine. This involved telling the display engine
> > > the location of the color control surfae (CCS) which describes
> > > which parts of the main surface are compressed and which are not. The
> > > location of CCS is provided by userspace as just another plane with its
> > > own offset.
> > >
> > > Add the required stuff to validate the user provided AUX plane metadata
> > > and convert the user provided linear offset into something the hardware
> > > can consume.
> > >
> > > Due to hardware limitations we require that the main surface and
> > > the AUX surface (CCS) be part of the same bo. The hardware also
> > > makes life hard by not allowing you to provide separate x/y offsets
> > > for the main and AUX surfaces (excpet with NV12), so finding suitable
> > > offsets for both requires a bit of work. Assuming we still want keep
> > > playing tricks with the offsets. I've just gone with a dumb "search
> > > backward for suitable offsets" approach, which is far from optimal,
> > > but it works.
> > >
> > > Also not all planes will be capable of scanning out compressed
> surfaces,
> > > and eg. 90/270 degree rotation is not supported in combination with
> > > decompression either.
> > >
> > > This patch may contain work from at least the following people:
> > > * Vandana Kannan 
> > > * Daniel Vetter 
> > > * Ben Widawsky 
> > >
> > > v2: Deal with display workarounds 0390, 0531, 1125 (Paulo)
> > >
> > > Cc: Paulo Zanoni 
> > > Cc: Vandana Kannan 
> > > Cc: Daniel Vetter 
> > > Cc: Ben Widawsky 
> > > Cc: Jason Ekstrand 
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h  |  23 
> > >  drivers/gpu/drm/i915/intel_display.c | 234
> ++
> > > ++---
> > >  drivers/gpu/drm/i915/intel_pm.c  |  29 -
> > >  drivers/gpu/drm/i915/intel_sprite.c  |   5 +
> > >  4 files changed, 274 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_
> > > reg.h
> > > index 00970aa77afa..6849ba93f1d9 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -6209,6 +6209,28 @@ enum {
> > > _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
> > > _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
> > >
> > > +#define PLANE_AUX_DIST_1_A 0x701c0
> > > +#define PLANE_AUX_DIST_2_A 0x702c0
> > > +#define PLANE_AUX_DIST_1_B 0x711c0
> > > +#define PLANE_AUX_DIST_2_B 0x712c0
> > > +#define _PLANE_AUX_DIST_1(pipe) \
> > > +   _PIPE(pipe, PLANE_AUX_DIST_1_A,
> PLANE_AUX_DIST_1_B)
> > > +#define _PLANE_AUX_DIST_2(pipe) \
> > > +   _PIPE(pipe, PLANE_AUX_DIST_2_A,
> PLANE_AUX_DIST_2_B)
> > > +#define PLANE_AUX_DIST(pipe, plane) \
> > > +   _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe),
> > > _PLANE_AUX_DIST_2(pipe))
> > > +
> > > +#define PLANE_AUX_OFFSET_1_A   0x701c4
> > > +#define PLANE_AUX_OFFSET_2_A   0x702c4
> > > +#define PLANE_AUX_OFFSET_1_B   0x711c4
> > > +#define PLANE_AUX_OFFSET_2_B   0x712c4
> > > +#define _PLANE_AUX_OFFSET_1(pipe)   \
> > > +   _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
> > > +#define _PLANE_AUX_OFFSET_2(pipe)   \
> > > +   _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
> > > +#define PLANE_AUX_OFFSET(pipe, plane)   \
> > > +   _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe),
> > > _PLANE_AUX_OFFSET_2(pipe))
> > > +
> > >  /* legacy palette */
> > >  #define _LGC_PALETTE_A   0x4a000
> > >  #define _LGC_PALETTE_B   0x4a800
> > > @@ -6433,6 +6455,7 @@ enum {
> > >  # define CHICKEN3_DGMG_DONE_FIX_DISABLE(1 << 2)
> > >
> > >  #define CHICKEN_PAR1_1 _MMIO(0x42080)
> > > +#define  SKL_RC_HASH_OUTSIDE   (1 << 15)
> > >  #define  DPA_MASK_VBLANK_SRD   (1 << 15)
> > >  #define  FORCE_ARB_IDLE_PLANES (1 << 14)
> > >  #define  SKL_EDP_PSR_FIX_RDWRAP(1 << 3)
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 38de9df0ec60..2236abebd8bc 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -2064,11 +2064,19 @@ intel_tile_width_bytes(const struct
> > > drm_framebuffer *fb, 

Re: [PATCH v2 9/9] drm/i915: Add render decompression support

[Jason Ekstrand]

On Wed, Jan 11, 2017 at 1:49 PM, Jason Ekstrand 
wrote:

> On Tue, Jan 10, 2017 at 9:04 AM, Ville Syrjälä <
> ville.syrj...@linux.intel.com> wrote:
>
>> On Mon, Jan 09, 2017 at 11:20:57AM -0800, Jason Ekstrand wrote:
>> > On Thu, Jan 5, 2017 at 7:14 AM,  wrote:
>> >
>> > > From: Ville Syrjälä 
>> > >
>> > > SKL+ display engine can scan out certain kinds of compressed surfaces
>> > > produced by the render engine. This involved telling the display
>> engine
>> > > the location of the color control surfae (CCS) which describes
>> > > which parts of the main surface are compressed and which are not. The
>> > > location of CCS is provided by userspace as just another plane with
>> its
>> > > own offset.
>> > >
>> > > Add the required stuff to validate the user provided AUX plane
>> metadata
>> > > and convert the user provided linear offset into something the
>> hardware
>> > > can consume.
>> > >
>> > > Due to hardware limitations we require that the main surface and
>> > > the AUX surface (CCS) be part of the same bo. The hardware also
>> > > makes life hard by not allowing you to provide separate x/y offsets
>> > > for the main and AUX surfaces (excpet with NV12), so finding suitable
>> > > offsets for both requires a bit of work. Assuming we still want keep
>> > > playing tricks with the offsets. I've just gone with a dumb "search
>> > > backward for suitable offsets" approach, which is far from optimal,
>> > > but it works.
>> > >
>> > > Also not all planes will be capable of scanning out compressed
>> surfaces,
>> > > and eg. 90/270 degree rotation is not supported in combination with
>> > > decompression either.
>> > >
>> > > This patch may contain work from at least the following people:
>> > > * Vandana Kannan 
>> > > * Daniel Vetter 
>> > > * Ben Widawsky 
>> > >
>> > > v2: Deal with display workarounds 0390, 0531, 1125 (Paulo)
>> > >
>> > > Cc: Paulo Zanoni 
>> > > Cc: Vandana Kannan 
>> > > Cc: Daniel Vetter 
>> > > Cc: Ben Widawsky 
>> > > Cc: Jason Ekstrand 
>> > > Signed-off-by: Ville Syrjälä 
>> > > ---
>> > >  drivers/gpu/drm/i915/i915_reg.h  |  23 
>> > >  drivers/gpu/drm/i915/intel_display.c | 234
>> ++
>> > > ++---
>> > >  drivers/gpu/drm/i915/intel_pm.c  |  29 -
>> > >  drivers/gpu/drm/i915/intel_sprite.c  |   5 +
>> > >  4 files changed, 274 insertions(+), 17 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_
>> > > reg.h
>> > > index 00970aa77afa..6849ba93f1d9 100644
>> > > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > > @@ -6209,6 +6209,28 @@ enum {
>> > > _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
>> > > _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
>> > >
>> > > +#define PLANE_AUX_DIST_1_A 0x701c0
>> > > +#define PLANE_AUX_DIST_2_A 0x702c0
>> > > +#define PLANE_AUX_DIST_1_B 0x711c0
>> > > +#define PLANE_AUX_DIST_2_B 0x712c0
>> > > +#define _PLANE_AUX_DIST_1(pipe) \
>> > > +   _PIPE(pipe, PLANE_AUX_DIST_1_A,
>> PLANE_AUX_DIST_1_B)
>> > > +#define _PLANE_AUX_DIST_2(pipe) \
>> > > +   _PIPE(pipe, PLANE_AUX_DIST_2_A,
>> PLANE_AUX_DIST_2_B)
>> > > +#define PLANE_AUX_DIST(pipe, plane) \
>> > > +   _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe),
>> > > _PLANE_AUX_DIST_2(pipe))
>> > > +
>> > > +#define PLANE_AUX_OFFSET_1_A   0x701c4
>> > > +#define PLANE_AUX_OFFSET_2_A   0x702c4
>> > > +#define PLANE_AUX_OFFSET_1_B   0x711c4
>> > > +#define PLANE_AUX_OFFSET_2_B   0x712c4
>> > > +#define _PLANE_AUX_OFFSET_1(pipe)   \
>> > > +   _PIPE(pipe, PLANE_AUX_OFFSET_1_A,
>> PLANE_AUX_OFFSET_1_B)
>> > > +#define _PLANE_AUX_OFFSET_2(pipe)   \
>> > > +   _PIPE(pipe, PLANE_AUX_OFFSET_2_A,
>> PLANE_AUX_OFFSET_2_B)
>> > > +#define PLANE_AUX_OFFSET(pipe, plane)   \
>> > > +   _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe),
>> > > _PLANE_AUX_OFFSET_2(pipe))
>> > > +
>> > >  /* legacy palette */
>> > >  #define _LGC_PALETTE_A   0x4a000
>> > >  #define _LGC_PALETTE_B   0x4a800
>> > > @@ -6433,6 +6455,7 @@ enum {
>> > >  # define CHICKEN3_DGMG_DONE_FIX_DISABLE(1 << 2)
>> > >
>> > >  #define CHICKEN_PAR1_1 _MMIO(0x42080)
>> > > +#define  SKL_RC_HASH_OUTSIDE   (1 << 15)
>> > >  #define  DPA_MASK_VBLANK_SRD   (1 << 15)
>> > >  #define  FORCE_ARB_IDLE_PLANES (1 << 14)
>> > >  #define  SKL_EDP_PSR_FIX_RDWRAP(1 << 3)
>> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
>> > > b/drivers/gpu/drm/i915/intel_display.c
>> > > index 

[PATCH v2 9/9] drm/i915: Add render decompression support

[Ville Syrjälä]

On Mon, Jan 09, 2017 at 11:20:57AM -0800, Jason Ekstrand wrote:
> On Thu, Jan 5, 2017 at 7:14 AM,  wrote:
> 
> > From: Ville Syrjälä 
> >
> > SKL+ display engine can scan out certain kinds of compressed surfaces
> > produced by the render engine. This involved telling the display engine
> > the location of the color control surfae (CCS) which describes
> > which parts of the main surface are compressed and which are not. The
> > location of CCS is provided by userspace as just another plane with its
> > own offset.
> >
> > Add the required stuff to validate the user provided AUX plane metadata
> > and convert the user provided linear offset into something the hardware
> > can consume.
> >
> > Due to hardware limitations we require that the main surface and
> > the AUX surface (CCS) be part of the same bo. The hardware also
> > makes life hard by not allowing you to provide separate x/y offsets
> > for the main and AUX surfaces (excpet with NV12), so finding suitable
> > offsets for both requires a bit of work. Assuming we still want keep
> > playing tricks with the offsets. I've just gone with a dumb "search
> > backward for suitable offsets" approach, which is far from optimal,
> > but it works.
> >
> > Also not all planes will be capable of scanning out compressed surfaces,
> > and eg. 90/270 degree rotation is not supported in combination with
> > decompression either.
> >
> > This patch may contain work from at least the following people:
> > * Vandana Kannan 
> > * Daniel Vetter 
> > * Ben Widawsky 
> >
> > v2: Deal with display workarounds 0390, 0531, 1125 (Paulo)
> >
> > Cc: Paulo Zanoni 
> > Cc: Vandana Kannan 
> > Cc: Daniel Vetter 
> > Cc: Ben Widawsky 
> > Cc: Jason Ekstrand 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |  23 
> >  drivers/gpu/drm/i915/intel_display.c | 234 ++
> > ++---
> >  drivers/gpu/drm/i915/intel_pm.c  |  29 -
> >  drivers/gpu/drm/i915/intel_sprite.c  |   5 +
> >  4 files changed, 274 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_
> > reg.h
> > index 00970aa77afa..6849ba93f1d9 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6209,6 +6209,28 @@ enum {
> > _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
> > _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
> >
> > +#define PLANE_AUX_DIST_1_A 0x701c0
> > +#define PLANE_AUX_DIST_2_A 0x702c0
> > +#define PLANE_AUX_DIST_1_B 0x711c0
> > +#define PLANE_AUX_DIST_2_B 0x712c0
> > +#define _PLANE_AUX_DIST_1(pipe) \
> > +   _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
> > +#define _PLANE_AUX_DIST_2(pipe) \
> > +   _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
> > +#define PLANE_AUX_DIST(pipe, plane) \
> > +   _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe),
> > _PLANE_AUX_DIST_2(pipe))
> > +
> > +#define PLANE_AUX_OFFSET_1_A   0x701c4
> > +#define PLANE_AUX_OFFSET_2_A   0x702c4
> > +#define PLANE_AUX_OFFSET_1_B   0x711c4
> > +#define PLANE_AUX_OFFSET_2_B   0x712c4
> > +#define _PLANE_AUX_OFFSET_1(pipe)   \
> > +   _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
> > +#define _PLANE_AUX_OFFSET_2(pipe)   \
> > +   _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
> > +#define PLANE_AUX_OFFSET(pipe, plane)   \
> > +   _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe),
> > _PLANE_AUX_OFFSET_2(pipe))
> > +
> >  /* legacy palette */
> >  #define _LGC_PALETTE_A   0x4a000
> >  #define _LGC_PALETTE_B   0x4a800
> > @@ -6433,6 +6455,7 @@ enum {
> >  # define CHICKEN3_DGMG_DONE_FIX_DISABLE(1 << 2)
> >
> >  #define CHICKEN_PAR1_1 _MMIO(0x42080)
> > +#define  SKL_RC_HASH_OUTSIDE   (1 << 15)
> >  #define  DPA_MASK_VBLANK_SRD   (1 << 15)
> >  #define  FORCE_ARB_IDLE_PLANES (1 << 14)
> >  #define  SKL_EDP_PSR_FIX_RDWRAP(1 << 3)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 38de9df0ec60..2236abebd8bc 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2064,11 +2064,19 @@ intel_tile_width_bytes(const struct
> > drm_framebuffer *fb, int plane)
> > return 128;
> > else
> > return 512;
> > +   case I915_FORMAT_MOD_Y_TILED_CCS:
> > +   if (plane == 1)
> > +   return 64;
> > +   /* fall through */
> > case I915_FORMAT_MOD_Y_TILED:
> > if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
> > return 128;
> > else
> > return 512;
> > +   case I915_FORMAT_MOD_Yf_TILED_CCS:
> > +   

[PATCH v2 9/9] drm/i915: Add render decompression support

[Jason Ekstrand]

On Thu, Jan 5, 2017 at 7:14 AM,  wrote:

> From: Ville Syrjälä 
>
> SKL+ display engine can scan out certain kinds of compressed surfaces
> produced by the render engine. This involved telling the display engine
> the location of the color control surfae (CCS) which describes
> which parts of the main surface are compressed and which are not. The
> location of CCS is provided by userspace as just another plane with its
> own offset.
>
> Add the required stuff to validate the user provided AUX plane metadata
> and convert the user provided linear offset into something the hardware
> can consume.
>
> Due to hardware limitations we require that the main surface and
> the AUX surface (CCS) be part of the same bo. The hardware also
> makes life hard by not allowing you to provide separate x/y offsets
> for the main and AUX surfaces (excpet with NV12), so finding suitable
> offsets for both requires a bit of work. Assuming we still want keep
> playing tricks with the offsets. I've just gone with a dumb "search
> backward for suitable offsets" approach, which is far from optimal,
> but it works.
>
> Also not all planes will be capable of scanning out compressed surfaces,
> and eg. 90/270 degree rotation is not supported in combination with
> decompression either.
>
> This patch may contain work from at least the following people:
> * Vandana Kannan 
> * Daniel Vetter 
> * Ben Widawsky 
>
> v2: Deal with display workarounds 0390, 0531, 1125 (Paulo)
>
> Cc: Paulo Zanoni 
> Cc: Vandana Kannan 
> Cc: Daniel Vetter 
> Cc: Ben Widawsky 
> Cc: Jason Ekstrand 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  23 
>  drivers/gpu/drm/i915/intel_display.c | 234 ++
> ++---
>  drivers/gpu/drm/i915/intel_pm.c  |  29 -
>  drivers/gpu/drm/i915/intel_sprite.c  |   5 +
>  4 files changed, 274 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_
> reg.h
> index 00970aa77afa..6849ba93f1d9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6209,6 +6209,28 @@ enum {
> _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
> _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
>
> +#define PLANE_AUX_DIST_1_A 0x701c0
> +#define PLANE_AUX_DIST_2_A 0x702c0
> +#define PLANE_AUX_DIST_1_B 0x711c0
> +#define PLANE_AUX_DIST_2_B 0x712c0
> +#define _PLANE_AUX_DIST_1(pipe) \
> +   _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
> +#define _PLANE_AUX_DIST_2(pipe) \
> +   _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
> +#define PLANE_AUX_DIST(pipe, plane) \
> +   _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe),
> _PLANE_AUX_DIST_2(pipe))
> +
> +#define PLANE_AUX_OFFSET_1_A   0x701c4
> +#define PLANE_AUX_OFFSET_2_A   0x702c4
> +#define PLANE_AUX_OFFSET_1_B   0x711c4
> +#define PLANE_AUX_OFFSET_2_B   0x712c4
> +#define _PLANE_AUX_OFFSET_1(pipe)   \
> +   _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
> +#define _PLANE_AUX_OFFSET_2(pipe)   \
> +   _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
> +#define PLANE_AUX_OFFSET(pipe, plane)   \
> +   _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe),
> _PLANE_AUX_OFFSET_2(pipe))
> +
>  /* legacy palette */
>  #define _LGC_PALETTE_A   0x4a000
>  #define _LGC_PALETTE_B   0x4a800
> @@ -6433,6 +6455,7 @@ enum {
>  # define CHICKEN3_DGMG_DONE_FIX_DISABLE(1 << 2)
>
>  #define CHICKEN_PAR1_1 _MMIO(0x42080)
> +#define  SKL_RC_HASH_OUTSIDE   (1 << 15)
>  #define  DPA_MASK_VBLANK_SRD   (1 << 15)
>  #define  FORCE_ARB_IDLE_PLANES (1 << 14)
>  #define  SKL_EDP_PSR_FIX_RDWRAP(1 << 3)
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 38de9df0ec60..2236abebd8bc 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2064,11 +2064,19 @@ intel_tile_width_bytes(const struct
> drm_framebuffer *fb, int plane)
> return 128;
> else
> return 512;
> +   case I915_FORMAT_MOD_Y_TILED_CCS:
> +   if (plane == 1)
> +   return 64;
> +   /* fall through */
> case I915_FORMAT_MOD_Y_TILED:
> if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
> return 128;
> else
> return 512;
> +   case I915_FORMAT_MOD_Yf_TILED_CCS:
> +   if (plane == 1)
> +   return 64;
>

I still think a CCS tile is 128B wide. :-)


> +   /* fall through */
> case I915_FORMAT_MOD_Yf_TILED:
> /*
>  * Bspec seems to suggest that the Yf tile width would
> @@ 

[PATCH v2 9/9] drm/i915: Add render decompression support

[ville.syrj...@linux.intel.com]

From: Ville Syrjälä 

SKL+ display engine can scan out certain kinds of compressed surfaces
produced by the render engine. This involved telling the display engine
the location of the color control surfae (CCS) which describes
which parts of the main surface are compressed and which are not. The
location of CCS is provided by userspace as just another plane with its
own offset.

Add the required stuff to validate the user provided AUX plane metadata
and convert the user provided linear offset into something the hardware
can consume.

Due to hardware limitations we require that the main surface and
the AUX surface (CCS) be part of the same bo. The hardware also
makes life hard by not allowing you to provide separate x/y offsets
for the main and AUX surfaces (excpet with NV12), so finding suitable
offsets for both requires a bit of work. Assuming we still want keep
playing tricks with the offsets. I've just gone with a dumb "search
backward for suitable offsets" approach, which is far from optimal,
but it works.

Also not all planes will be capable of scanning out compressed surfaces,
and eg. 90/270 degree rotation is not supported in combination with
decompression either.

This patch may contain work from at least the following people:
* Vandana Kannan 
* Daniel Vetter 
* Ben Widawsky 

v2: Deal with display workarounds 0390, 0531, 1125 (Paulo)

Cc: Paulo Zanoni 
Cc: Vandana Kannan 
Cc: Daniel Vetter 
Cc: Ben Widawsky 
Cc: Jason Ekstrand 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h  |  23 
 drivers/gpu/drm/i915/intel_display.c | 234 ---
 drivers/gpu/drm/i915/intel_pm.c  |  29 -
 drivers/gpu/drm/i915/intel_sprite.c  |   5 +
 4 files changed, 274 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 00970aa77afa..6849ba93f1d9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6209,6 +6209,28 @@ enum {
_ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A),   \
_ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))

+#define PLANE_AUX_DIST_1_A 0x701c0
+#define PLANE_AUX_DIST_2_A 0x702c0
+#define PLANE_AUX_DIST_1_B 0x711c0
+#define PLANE_AUX_DIST_2_B 0x712c0
+#define _PLANE_AUX_DIST_1(pipe) \
+   _PIPE(pipe, PLANE_AUX_DIST_1_A, PLANE_AUX_DIST_1_B)
+#define _PLANE_AUX_DIST_2(pipe) \
+   _PIPE(pipe, PLANE_AUX_DIST_2_A, PLANE_AUX_DIST_2_B)
+#define PLANE_AUX_DIST(pipe, plane) \
+   _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
+
+#define PLANE_AUX_OFFSET_1_A   0x701c4
+#define PLANE_AUX_OFFSET_2_A   0x702c4
+#define PLANE_AUX_OFFSET_1_B   0x711c4
+#define PLANE_AUX_OFFSET_2_B   0x712c4
+#define _PLANE_AUX_OFFSET_1(pipe)   \
+   _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
+#define _PLANE_AUX_OFFSET_2(pipe)   \
+   _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
+#define PLANE_AUX_OFFSET(pipe, plane)   \
+   _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
+
 /* legacy palette */
 #define _LGC_PALETTE_A   0x4a000
 #define _LGC_PALETTE_B   0x4a800
@@ -6433,6 +6455,7 @@ enum {
 # define CHICKEN3_DGMG_DONE_FIX_DISABLE(1 << 2)

 #define CHICKEN_PAR1_1 _MMIO(0x42080)
+#define  SKL_RC_HASH_OUTSIDE   (1 << 15)
 #define  DPA_MASK_VBLANK_SRD   (1 << 15)
 #define  FORCE_ARB_IDLE_PLANES (1 << 14)
 #define  SKL_EDP_PSR_FIX_RDWRAP(1 << 3)
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 38de9df0ec60..2236abebd8bc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2064,11 +2064,19 @@ intel_tile_width_bytes(const struct drm_framebuffer 
*fb, int plane)
return 128;
else
return 512;
+   case I915_FORMAT_MOD_Y_TILED_CCS:
+   if (plane == 1)
+   return 64;
+   /* fall through */
case I915_FORMAT_MOD_Y_TILED:
if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
return 128;
else
return 512;
+   case I915_FORMAT_MOD_Yf_TILED_CCS:
+   if (plane == 1)
+   return 64;
+   /* fall through */
case I915_FORMAT_MOD_Yf_TILED:
/*
 * Bspec seems to suggest that the Yf tile width would
@@ -2156,7 +2164,7 @@ static unsigned int intel_surf_alignment(const struct 
drm_framebuffer *fb,
struct drm_i915_private *dev_priv = to_i915(fb->dev);

/* AUX_DIST needs only 4K alignment */
-   if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
+   if (plane