Re: [PATCH v3 02/40] drm: HDMI and DP specific HDCP2.2 defines

2018-05-14 Thread Ramalingam C 



On Wednesday 09 May 2018 03:36 PM, Shankar, Uma wrote:



-Original Message-
From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
Ramalingam C
Sent: Tuesday, April 3, 2018 7:27 PM
To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
jani.nik...@linux.intel.com; Winkler, Tomas <tomas.wink...@intel.com>;
Usyskin, Alexander <alexander.usys...@intel.com>
Cc: Vivi, Rodrigo <rodrigo.v...@intel.com>
Subject: [PATCH v3 02/40] drm: HDMI and DP specific HDCP2.2 defines

In preparation for implementing HDCP2.2 in I915, this patch adds HDCP register
definitions for HDMI and DP HDCP adaptations.

I believe we can just keep this message generic at drm layer, instead of 
calling out
i915 specifically. Currently it may be enabled for i915, but it will used for 
other
drivers as well in future.

ok



HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h, where are

Make it "where as".

ok



HDCP2.2 register offsets in DPCD offsets are defined at drm_dp_helper.h.

v2:
  bit_field definitions are replaced by macros. [Tomas and Jany]

Typo in "Jani's" name.

Sorry Jani.



v3:
  No Changes.

Signed-off-by: Ramalingam C <ramalinga...@intel.com>
---
include/drm/drm_dp_helper.h | 54
+
include/drm/drm_hdcp.h  | 29 
2 files changed, 83 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
4de97e94ef9d..2185b3a88911 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -887,6 +887,60 @@
#define DP_AUX_HDCP_KSV_FIFO0x6802C
#define DP_AUX_HDCP_AINFO   0x6803B

+/**
+ * DP HDCP2.2 parameter offsets in DPCD address space  */

Rectify the comment style

ok



+#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
+#define DP_HDCP_2_2_REG_TXCAPS_OFFSET  0x69008
+#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
+#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
+#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
+#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET0x69220
+#define DP_HDCP_2_2_REG_EKH_KM_OFFSET  0x692A0
+#define DP_HDCP_2_2_REG_M_OFFSET   0x692B0
+#define DP_HDCP_2_2_REG_HPRIME_OFFSET  0x692C0
+#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET   0x692E0
+#define DP_HDCP_2_2_REG_RN_OFFSET  0x692F0
+#define DP_HDCP_2_2_REG_LPRIME_OFFSET  0x692F8
+#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET0x69318
+#defineDP_HDCP_2_2_REG_RIV_OFFSET  0x69328
+#define DP_HDCP_2_2_REG_RXINFO_OFFSET  0x69330
+#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET   0x69332
+#define DP_HDCP_2_2_REG_VPRIME_OFFSET  0x69335
+#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET0x69345
+#define DP_HDCP_2_2_REG_V_OFFSET   0x693E0
+#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET   0x693F0
+#define DP_HDCP_2_2_REG_K_OFFSET   0x693F3
+#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET  0x693F5
+#define DP_HDCP_2_2_REG_MPRIME_OFFSET  0x69473
+#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET0x69493
+#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494

This is not matching to the spec. Seems reserved in spec.

Not really. Register is defined in the DP HDCP2.2 Spec.



+#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
+
+/**
+ * DP HDCP message start offsets in DPCD address space  */

Rectify comment style


+#define DP_HDCP_2_2_AKE_INIT_OFFSET
DP_HDCP_2_2_REG_RTX_OFFSET
+#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET
DP_HDCP_2_2_REG_CERT_RX_OFFSET
+#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET
DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
+#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET
DP_HDCP_2_2_REG_EKH_KM_OFFSET
+#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET
DP_HDCP_2_2_REG_HPRIME_OFFSET
+#define DP_HDCP_2_2_AKE_SEND_PARING_INFO_OFFSET

Typo in pairing

Fixed.



DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
+#define DP_HDCP_2_2_LC_INIT_OFFSET
DP_HDCP_2_2_REG_RN_OFFSET
+#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET
DP_HDCP_2_2_REG_LPRIME_OFFSET
+#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET
DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
+#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET
DP_HDCP_2_2_REG_RXINFO_OFFSET
+#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET
DP_HDCP_2_2_REG_V_OFFSET
+#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET
DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
+#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET
DP_HDCP_2_2_REG_MPRIME_OFFSET
+
+#define HDCP_2_2_DP_RXSTATUS_LEN   1
+#define HDCP_2_2_DP_RXSTATUS_READY(x)  (x & BIT(0))
+#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x)(x & BIT(1))
+#define HDCP_2_2_DP_RXSTATUS_PAIRING(x)(x & BIT(2))
+#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) (x & BIT(

RE: [PATCH v3 02/40] drm: HDMI and DP specific HDCP2.2 defines

2018-05-09 Thread Shankar, Uma 


>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
>Ramalingam C
>Sent: Tuesday, April 3, 2018 7:27 PM
>To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
>seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
>jani.nik...@linux.intel.com; Winkler, Tomas <tomas.wink...@intel.com>;
>Usyskin, Alexander <alexander.usys...@intel.com>
>Cc: Vivi, Rodrigo <rodrigo.v...@intel.com>
>Subject: [PATCH v3 02/40] drm: HDMI and DP specific HDCP2.2 defines
>
>In preparation for implementing HDCP2.2 in I915, this patch adds HDCP register
>definitions for HDMI and DP HDCP adaptations.

I believe we can just keep this message generic at drm layer, instead of 
calling out
i915 specifically. Currently it may be enabled for i915, but it will used for 
other
drivers as well in future.

>
>HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h, where are

Make it "where as".

>HDCP2.2 register offsets in DPCD offsets are defined at drm_dp_helper.h.
>
>v2:
>  bit_field definitions are replaced by macros. [Tomas and Jany]

Typo in "Jani's" name.

>v3:
>  No Changes.
>
>Signed-off-by: Ramalingam C <ramalinga...@intel.com>
>---
> include/drm/drm_dp_helper.h | 54
>+
> include/drm/drm_hdcp.h  | 29 
> 2 files changed, 83 insertions(+)
>
>diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
>4de97e94ef9d..2185b3a88911 100644
>--- a/include/drm/drm_dp_helper.h
>+++ b/include/drm/drm_dp_helper.h
>@@ -887,6 +887,60 @@
> #define DP_AUX_HDCP_KSV_FIFO  0x6802C
> #define DP_AUX_HDCP_AINFO 0x6803B
>
>+/**
>+ * DP HDCP2.2 parameter offsets in DPCD address space  */

Rectify the comment style

>+#define DP_HDCP_2_2_REG_RTX_OFFSET0x69000
>+#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
>+#define DP_HDCP_2_2_REG_CERT_RX_OFFSET0x6900B
>+#define DP_HDCP_2_2_REG_RRX_OFFSET0x69215
>+#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET0x6921D
>+#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET   0x69220
>+#define DP_HDCP_2_2_REG_EKH_KM_OFFSET 0x692A0
>+#define DP_HDCP_2_2_REG_M_OFFSET  0x692B0
>+#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
>+#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET  0x692E0
>+#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
>+#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
>+#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET   0x69318
>+#define   DP_HDCP_2_2_REG_RIV_OFFSET  0x69328
>+#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
>+#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET  0x69332
>+#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
>+#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET   0x69345
>+#define DP_HDCP_2_2_REG_V_OFFSET  0x693E0
>+#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET  0x693F0
>+#define DP_HDCP_2_2_REG_K_OFFSET  0x693F3
>+#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
>+#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
>+#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET   0x69493
>+#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET0x69494

This is not matching to the spec. Seems reserved in spec.

>+#define DP_HDCP_2_2_REG_DBG_OFFSET0x69518
>+
>+/**
>+ * DP HDCP message start offsets in DPCD address space  */

Rectify comment style

>+#define DP_HDCP_2_2_AKE_INIT_OFFSET
>   DP_HDCP_2_2_REG_RTX_OFFSET
>+#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET
>   DP_HDCP_2_2_REG_CERT_RX_OFFSET
>+#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET
>   DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
>+#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET
>   DP_HDCP_2_2_REG_EKH_KM_OFFSET
>+#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET
>   DP_HDCP_2_2_REG_HPRIME_OFFSET
>+#define DP_HDCP_2_2_AKE_SEND_PARING_INFO_OFFSET

Typo in pairing

>   DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
>+#define DP_HDCP_2_2_LC_INIT_OFFSET
>   DP_HDCP_2_2_REG_RN_OFFSET
>+#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET
>   DP_HDCP_2_2_REG_LPRIME_OFFSET
>+#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET
>   DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
>+#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET
>   DP_HDCP_2_2_REG_RXINFO_OFFSET
>+#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET
>   DP_HDCP_2_2_REG_V_OFFSET
>+#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET
>   DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
>+#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET
>   DP_HDCP_2_2_REG_MPRIME_OFFSET
>+
>+#define HDCP_2_2_DP_RXSTATUS_LEN  1
>+#define HDCP_2_2_DP_RXSTATUS_READY(x) (x & BIT(0))
>

[PATCH v3 02/40] drm: HDMI and DP specific HDCP2.2 defines

2018-04-03 Thread Ramalingam C 
In preparation for implementing HDCP2.2 in I915, this patch adds
HDCP register definitions for HDMI and DP HDCP adaptations.

HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h,
where are HDCP2.2 register offsets in DPCD offsets are defined at
drm_dp_helper.h.

v2:
  bit_field definitions are replaced by macros. [Tomas and Jany]
v3:
  No Changes.

Signed-off-by: Ramalingam C 
---
 include/drm/drm_dp_helper.h | 54 +
 include/drm/drm_hdcp.h  | 29 
 2 files changed, 83 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 4de97e94ef9d..2185b3a88911 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -887,6 +887,60 @@
 #define DP_AUX_HDCP_KSV_FIFO   0x6802C
 #define DP_AUX_HDCP_AINFO  0x6803B
 
+/**
+ * DP HDCP2.2 parameter offsets in DPCD address space
+ */
+#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
+#define DP_HDCP_2_2_REG_TXCAPS_OFFSET  0x69008
+#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
+#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
+#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
+#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET0x69220
+#define DP_HDCP_2_2_REG_EKH_KM_OFFSET  0x692A0
+#define DP_HDCP_2_2_REG_M_OFFSET   0x692B0
+#define DP_HDCP_2_2_REG_HPRIME_OFFSET  0x692C0
+#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET   0x692E0
+#define DP_HDCP_2_2_REG_RN_OFFSET  0x692F0
+#define DP_HDCP_2_2_REG_LPRIME_OFFSET  0x692F8
+#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET0x69318
+#defineDP_HDCP_2_2_REG_RIV_OFFSET  0x69328
+#define DP_HDCP_2_2_REG_RXINFO_OFFSET  0x69330
+#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET   0x69332
+#define DP_HDCP_2_2_REG_VPRIME_OFFSET  0x69335
+#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET0x69345
+#define DP_HDCP_2_2_REG_V_OFFSET   0x693E0
+#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET   0x693F0
+#define DP_HDCP_2_2_REG_K_OFFSET   0x693F3
+#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET  0x693F5
+#define DP_HDCP_2_2_REG_MPRIME_OFFSET  0x69473
+#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET0x69493
+#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
+#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
+
+/**
+ * DP HDCP message start offsets in DPCD address space
+ */
+#define DP_HDCP_2_2_AKE_INIT_OFFSETDP_HDCP_2_2_REG_RTX_OFFSET
+#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET   DP_HDCP_2_2_REG_CERT_RX_OFFSET
+#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSETDP_HDCP_2_2_REG_EKPUB_KM_OFFSET
+#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET   DP_HDCP_2_2_REG_EKH_KM_OFFSET
+#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
+#define DP_HDCP_2_2_AKE_SEND_PARING_INFO_OFFSET
DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
+#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
+#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET  DP_HDCP_2_2_REG_LPRIME_OFFSET
+#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET
DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
+#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET
DP_HDCP_2_2_REG_RXINFO_OFFSET
+#define DP_HDCP_2_2_REP_SEND_ACK_OFFSETDP_HDCP_2_2_REG_V_OFFSET
+#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET   DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
+#define DP_HDCP_2_2_REP_STREAM_READY_OFFSETDP_HDCP_2_2_REG_MPRIME_OFFSET
+
+#define HDCP_2_2_DP_RXSTATUS_LEN   1
+#define HDCP_2_2_DP_RXSTATUS_READY(x)  (x & BIT(0))
+#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x)(x & BIT(1))
+#define HDCP_2_2_DP_RXSTATUS_PAIRING(x)(x & BIT(2))
+#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) (x & BIT(3))
+#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x)(x & BIT(4))
+
 /* DP 1.2 Sideband message defines */
 /* peer device type - DP 1.2a Table 2-92 */
 #define DP_PEER_DEVICE_NONE0x0
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 5e0a5ed1a08e..f3f28414b189 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -221,4 +221,33 @@ struct hdcp2_dp_errata_stream_type {
uint8_t stream_type;
 } __packed;
 
+/* HDCP2.2 TIMEOUTs in mSec */
+#define HDCP_2_2_CERT_TIMEOUT  100
+#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT  1000
+#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT 200
+#define HDCP_2_2_PAIRING_TIMEOUT   200
+#defineHDCP_2_2_HDMI_LPRIME_TIMEOUT20
+#define HDCP_2_2_DP_LPRIME_TIMEOUT 7
+#define HDCP_2_2_RECVID_LIST_TIMEOUT   3000
+#define HDCP_2_2_STREAM_READY_TIMEOUT  100
+
+/* HDMI HDCP2.2 Register Offsets */
+#define HDCP_2_2_HDMI_REG_VER_OFFSET   0x50
+#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET0x60
+#define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET