Re: [PATCH v3 RESEND 9/9] drm/bridge: imx: Add i.MX93 MIPI DSI support
On Mon, Aug 21, 2023 at 5:38 AM Liu Ying wrote: > > Freescale i.MX93 SoC embeds a Synopsys Designware MIPI DSI host > controller and a Synopsys Designware MIPI DPHY. Some configurations > and extensions to them are controlled by i.MX93 media blk-ctrl. > > Add a DRM bridge for i.MX93 MIPI DSI by using existing DW MIPI DSI > bridge helpers and implementing i.MX93 MIPI DSI specific extensions. > > Signed-off-by: Liu Ying > --- > v2->v3: > * Select GENERIC_PHY to fix Kconfig warning for GENERIC_PHY_MIPI_DPHY > dependency. > > v1->v2: > * Use dev_err_probe() to replace DRM_DEV_ERROR(). (Sam and Alexander) > * Use dev_*() to replace DRM_*(). (Sam) > * Fix build for arm architecture. > (Reported-by: kernel test robot ) > * Improve error messages for imx93_dsi_phy_init(). > > drivers/gpu/drm/bridge/imx/Kconfig | 11 + > drivers/gpu/drm/bridge/imx/Makefile | 1 + > drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c | 917 > 3 files changed, 929 insertions(+) > create mode 100644 drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c > > diff --git a/drivers/gpu/drm/bridge/imx/Kconfig > b/drivers/gpu/drm/bridge/imx/Kconfig > index 9fae28db6aa7..5a4f3d58501e 100644 > --- a/drivers/gpu/drm/bridge/imx/Kconfig > +++ b/drivers/gpu/drm/bridge/imx/Kconfig > @@ -49,4 +49,15 @@ config DRM_IMX8QXP_PIXEL_LINK_TO_DPI > Choose this to enable pixel link to display pixel interface(PXL2DPI) > found in Freescale i.MX8qxp processor. > > +config DRM_IMX93_MIPI_DSI > + tristate "Freescale i.MX93 specific extensions for Synopsys DW MIPI > DSI" > + depends on OF > + depends on COMMON_CLK > + select DRM_DW_MIPI_DSI > + select GENERIC_PHY > + select GENERIC_PHY_MIPI_DPHY > + help > + Choose this to enable MIPI DSI controller found in Freescale i.MX93 > + processor. > + > endif # ARCH_MXC || COMPILE_TEST > diff --git a/drivers/gpu/drm/bridge/imx/Makefile > b/drivers/gpu/drm/bridge/imx/Makefile > index 8e2ebf3399a1..2b0c2e44aa1b 100644 > --- a/drivers/gpu/drm/bridge/imx/Makefile > +++ b/drivers/gpu/drm/bridge/imx/Makefile > @@ -4,3 +4,4 @@ obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o > +obj-$(CONFIG_DRM_IMX93_MIPI_DSI) += imx93-mipi-dsi.o > diff --git a/drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c > b/drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c > new file mode 100644 > index ..3ff30ce80c5b > --- /dev/null > +++ b/drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c > @@ -0,0 +1,917 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +/* > + * Copyright 2022,2023 NXP > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > + > +/* DPHY PLL configuration registers */ > +#define DSI_REG0x4c > +#define CFGCLKFREQRANGE_MASK GENMASK(5, 0) > +#define CFGCLKFREQRANGE(x)FIELD_PREP(CFGCLKFREQRANGE_MASK, (x)) > +#define CLKSEL_MASK GENMASK(7, 6) > +#define CLKSEL_STOP FIELD_PREP(CLKSEL_MASK, 0) > +#define CLKSEL_GENFIELD_PREP(CLKSEL_MASK, 1) > +#define CLKSEL_EXTFIELD_PREP(CLKSEL_MASK, 2) > +#define HSFREQRANGE_MASK GENMASK(14, 8) > +#define HSFREQRANGE(x)FIELD_PREP(HSFREQRANGE_MASK, > (x)) > +#define UPDATE_PLLBIT(17) > +#define SHADOW_CLRBIT(18) > +#define CLK_EXT BIT(19) > + > +#define DSI_WRITE_REG0 0x50 > +#define M_MASKGENMASK(9, 0) > +#define M(x) FIELD_PREP(M_MASK, ((x) - 2)) > +#define N_MASKGENMASK(13, 10) > +#define N(x) FIELD_PREP(N_MASK, ((x) - 1)) > +#define VCO_CTRL_MASK GENMASK(19, 14) > +#define VCO_CTRL(x) FIELD_PREP(VCO_CTRL_MASK, (x)) > +#define PROP_CTRL_MASKGENMASK(25, 20) > +#define PROP_CTRL(x) FIELD_PREP(PROP_CTRL_MASK, (x)) > +#define INT_CTRL_MASK GENMASK(31, 26) > +#define INT_CTRL(x) FIELD_PREP(INT_CTRL_MASK, (x)) > + > +#define DSI_WRITE_REG1 0x54 > +#define GMP_CTRL_MASK GENMASK(1, 0) > +#define GMP_CTRL(x) FIELD_PREP(GMP_CTRL_MASK, (x)) > +#define CPBIAS_CTRL_MASK GENMASK(8, 2) > +#define CPBIAS_CTRL(x)FIELD_PREP(CPBIAS_CTRL_MASK, > (x)) > +#define PLL_SHADOW_CTRL BIT(9) > + > +/* display mux control register */ > +#define DISPLAY_MUX
[PATCH v3 RESEND 9/9] drm/bridge: imx: Add i.MX93 MIPI DSI support
Freescale i.MX93 SoC embeds a Synopsys Designware MIPI DSI host controller and a Synopsys Designware MIPI DPHY. Some configurations and extensions to them are controlled by i.MX93 media blk-ctrl. Add a DRM bridge for i.MX93 MIPI DSI by using existing DW MIPI DSI bridge helpers and implementing i.MX93 MIPI DSI specific extensions. Signed-off-by: Liu Ying --- v2->v3: * Select GENERIC_PHY to fix Kconfig warning for GENERIC_PHY_MIPI_DPHY dependency. v1->v2: * Use dev_err_probe() to replace DRM_DEV_ERROR(). (Sam and Alexander) * Use dev_*() to replace DRM_*(). (Sam) * Fix build for arm architecture. (Reported-by: kernel test robot ) * Improve error messages for imx93_dsi_phy_init(). drivers/gpu/drm/bridge/imx/Kconfig | 11 + drivers/gpu/drm/bridge/imx/Makefile | 1 + drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c | 917 3 files changed, 929 insertions(+) create mode 100644 drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig index 9fae28db6aa7..5a4f3d58501e 100644 --- a/drivers/gpu/drm/bridge/imx/Kconfig +++ b/drivers/gpu/drm/bridge/imx/Kconfig @@ -49,4 +49,15 @@ config DRM_IMX8QXP_PIXEL_LINK_TO_DPI Choose this to enable pixel link to display pixel interface(PXL2DPI) found in Freescale i.MX8qxp processor. +config DRM_IMX93_MIPI_DSI + tristate "Freescale i.MX93 specific extensions for Synopsys DW MIPI DSI" + depends on OF + depends on COMMON_CLK + select DRM_DW_MIPI_DSI + select GENERIC_PHY + select GENERIC_PHY_MIPI_DPHY + help + Choose this to enable MIPI DSI controller found in Freescale i.MX93 + processor. + endif # ARCH_MXC || COMPILE_TEST diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile index 8e2ebf3399a1..2b0c2e44aa1b 100644 --- a/drivers/gpu/drm/bridge/imx/Makefile +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o +obj-$(CONFIG_DRM_IMX93_MIPI_DSI) += imx93-mipi-dsi.o diff --git a/drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c b/drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c new file mode 100644 index ..3ff30ce80c5b --- /dev/null +++ b/drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c @@ -0,0 +1,917 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2022,2023 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/* DPHY PLL configuration registers */ +#define DSI_REG0x4c +#define CFGCLKFREQRANGE_MASK GENMASK(5, 0) +#define CFGCLKFREQRANGE(x)FIELD_PREP(CFGCLKFREQRANGE_MASK, (x)) +#define CLKSEL_MASK GENMASK(7, 6) +#define CLKSEL_STOP FIELD_PREP(CLKSEL_MASK, 0) +#define CLKSEL_GENFIELD_PREP(CLKSEL_MASK, 1) +#define CLKSEL_EXTFIELD_PREP(CLKSEL_MASK, 2) +#define HSFREQRANGE_MASK GENMASK(14, 8) +#define HSFREQRANGE(x)FIELD_PREP(HSFREQRANGE_MASK, (x)) +#define UPDATE_PLLBIT(17) +#define SHADOW_CLRBIT(18) +#define CLK_EXT BIT(19) + +#define DSI_WRITE_REG0 0x50 +#define M_MASKGENMASK(9, 0) +#define M(x) FIELD_PREP(M_MASK, ((x) - 2)) +#define N_MASKGENMASK(13, 10) +#define N(x) FIELD_PREP(N_MASK, ((x) - 1)) +#define VCO_CTRL_MASK GENMASK(19, 14) +#define VCO_CTRL(x) FIELD_PREP(VCO_CTRL_MASK, (x)) +#define PROP_CTRL_MASKGENMASK(25, 20) +#define PROP_CTRL(x) FIELD_PREP(PROP_CTRL_MASK, (x)) +#define INT_CTRL_MASK GENMASK(31, 26) +#define INT_CTRL(x) FIELD_PREP(INT_CTRL_MASK, (x)) + +#define DSI_WRITE_REG1 0x54 +#define GMP_CTRL_MASK GENMASK(1, 0) +#define GMP_CTRL(x) FIELD_PREP(GMP_CTRL_MASK, (x)) +#define CPBIAS_CTRL_MASK GENMASK(8, 2) +#define CPBIAS_CTRL(x)FIELD_PREP(CPBIAS_CTRL_MASK, (x)) +#define PLL_SHADOW_CTRL BIT(9) + +/* display mux control register */ +#define DISPLAY_MUX0x60 +#define MIPI_DSI_RGB666_MAP_CFG GENMASK(7, 6) +#define RGB666_CONFIG1 FIELD_PREP(MIPI_DSI_RGB666_MAP_CFG, 0) +#define RGB666_CONFIG2 FIELD_PREP(MIPI_DSI_RGB666_MAP_CFG, 1) +#define MIPI_DSI_RGB565_MAP_CFG GENMASK(5,
