Re: [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function

2021-01-29 Thread Matthias Brugger 



On 21/01/2021 01:56, Yongqiang Niu wrote:
> On Wed, 2021-01-20 at 20:38 +0100, Matthias Brugger wrote:
>> On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
>>> move register operation into mmsys path select function
>>
>> Why do you want to do that. It seems the register access pattern is the
>> same for all SoCs so far supported, so I don't see the need to duplicate
>> the code in every SoC.
>>
>> Regards,
>> Matthias
> 
> mt2701 and mt8173 ovl mout en already different.
> mt2701 ovl mout en register offset is 0x30
> mt8173 olv mout en register offset is 0x40
> 
> only the use case is different;
> mt2701 ovl->color0
> mt8173 ovl->rmda0
> there make different define for this different.
> 
> #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
> 
> #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN  0x030
> 
> for the future mt8183, ovl mout en register offset will change to
> 0xf00
> 
> this is only one different sample, there will be more and more
> different, so we add this patch for different soc
> 
> 

That does not explain why you want to put the read and write calls in a per SoC
part, they are the same for all supported SoCs.

Anyway after having a second thought, I don't like this approach at all. I think
splitting up the code in several SoCs to not bloat the driver is a good thing,
but not as it is done in this series.

I'd prefer to use a lookup table as Enric did in his first approach [1]. We
could then add this table in a per SoC header file.

Regards,
Matthias


https://patchwork.kernel.org/project/linux-mediatek/patch/20201006193320.405529-5-enric.balle...@collabora.com/

>>
>>>
>>> Signed-off-by: Yongqiang Niu 
>>> ---
>>>  drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 
>>> +
>>>  1 file changed, 71 insertions(+), 69 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c 
>>> b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>>> index 6c03282..64c8030 100644
>>> --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
>>> @@ -106,141 +106,161 @@ struct mtk_mmsys {
>>> .clk_driver = "clk-mt8183-mm",
>>>  };
>>>  
>>> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
>>> - enum mtk_ddp_comp_id next,
>>> - unsigned int *addr)
>>> +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
>>> + enum mtk_ddp_comp_id cur,
>>> + enum mtk_ddp_comp_id next,
>>> + bool enable)
>>>  {
>>> -   unsigned int value;
>>> +   unsigned int addr, value, reg;
>>>  
>>> if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> -   *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>>> +   addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>>> value = OVL0_MOUT_EN_COLOR0;
>>> } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>>> -   *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>>> +   addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>>> value = OVL_MOUT_EN_RDMA;
>>> } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>>> -   *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> +   addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> value = OD_MOUT_EN_RDMA0;
>>> } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>>> -   *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>>> +   addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>>> value = UFOE_MOUT_EN_DSI0;
>>> } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> -   *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>>> +   addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>>> value = OVL1_MOUT_EN_COLOR1;
>>> } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>>> -   *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>>> +   addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>>> value = GAMMA_MOUT_EN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>>> -   *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> +   addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> value = OD1_MOUT_EN_RDMA1;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>>> -   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> +   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DPI0;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>>> -   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> +   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> value = RDMA0_SOUT_DPI1;
>>> } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>>> -   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> +   addr =

Re: [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function

2021-01-21 Thread Yongqiang Niu 
On Wed, 2021-01-20 at 20:38 +0100, Matthias Brugger wrote:
> On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
> > move register operation into mmsys path select function
> 
> Why do you want to do that. It seems the register access pattern is the
> same for all SoCs so far supported, so I don't see the need to duplicate
> the code in every SoC.
> 
> Regards,
> Matthias

mt2701 and mt8173 ovl mout en already different.
mt2701 ovl mout en register offset is 0x30
mt8173 olv mout en register offset is 0x40

only the use case is different;
mt2701 ovl->color0
mt8173 ovl->rmda0
there make different define for this different.

#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN   0x040

#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN0x030

for the future mt8183, ovl mout en register offset will change to
0xf00

this is only one different sample, there will be more and more
different, so we add this patch for different soc


> 
> > 
> > Signed-off-by: Yongqiang Niu 
> > ---
> >  drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 
> > +
> >  1 file changed, 71 insertions(+), 69 deletions(-)
> > 
> > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c 
> > b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > index 6c03282..64c8030 100644
> > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > @@ -106,141 +106,161 @@ struct mtk_mmsys {
> > .clk_driver = "clk-mt8183-mm",
> >  };
> >  
> > -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > - enum mtk_ddp_comp_id next,
> > - unsigned int *addr)
> > +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
> > + enum mtk_ddp_comp_id cur,
> > + enum mtk_ddp_comp_id next,
> > + bool enable)
> >  {
> > -   unsigned int value;
> > +   unsigned int addr, value, reg;
> >  
> > if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > -   *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> > value = OVL0_MOUT_EN_COLOR0;
> > } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> > -   *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> > value = OVL_MOUT_EN_RDMA;
> > } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> > -   *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > value = OD_MOUT_EN_RDMA0;
> > } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> > -   *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> > value = UFOE_MOUT_EN_DSI0;
> > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > -   *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> > value = OVL1_MOUT_EN_COLOR1;
> > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> > -   *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > value = GAMMA_MOUT_EN_RDMA1;
> > } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> > -   *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > value = OD1_MOUT_EN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> > -   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DPI0;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> > -   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DPI1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> > -   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DSI1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> > -   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DSI2;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> > -   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DSI3;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> > -   *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > +

Re: [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function

2021-01-20 Thread Matthias Brugger 
On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
> move register operation into mmsys path select function

Why do you want to do that. It seems the register access pattern is the
same for all SoCs so far supported, so I don't see the need to duplicate
the code in every SoC.

Regards,
Matthias

> 
> Signed-off-by: Yongqiang Niu 
> ---
>  drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 
> +
>  1 file changed, 71 insertions(+), 69 deletions(-)
> 
> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c 
> b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> index 6c03282..64c8030 100644
> --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> @@ -106,141 +106,161 @@ struct mtk_mmsys {
>   .clk_driver = "clk-mt8183-mm",
>  };
>  
> -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> -   enum mtk_ddp_comp_id next,
> -   unsigned int *addr)
> +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
> +   enum mtk_ddp_comp_id cur,
> +   enum mtk_ddp_comp_id next,
> +   bool enable)
>  {
> - unsigned int value;
> + unsigned int addr, value, reg;
>  
>   if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>   value = OVL0_MOUT_EN_COLOR0;
>   } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>   value = OVL_MOUT_EN_RDMA;
>   } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>   value = OD_MOUT_EN_RDMA0;
>   } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> - *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>   value = UFOE_MOUT_EN_DSI0;
>   } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> - *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>   value = OVL1_MOUT_EN_COLOR1;
>   } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>   value = GAMMA_MOUT_EN_RDMA1;
>   } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> - *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>   value = OD1_MOUT_EN_RDMA1;
>   } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>   value = RDMA0_SOUT_DPI0;
>   } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>   value = RDMA0_SOUT_DPI1;
>   } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>   value = RDMA0_SOUT_DSI1;
>   } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>   value = RDMA0_SOUT_DSI2;
>   } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>   value = RDMA0_SOUT_DSI3;
>   } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>   value = RDMA1_SOUT_DSI1;
>   } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>   value = RDMA1_SOUT_DSI2;
>   } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> - *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> + addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>   value = RDMA1_SOUT_DSI3;
>   } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> - *addr =

[PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function

2021-01-05 Thread Yongqiang Niu 
move register operation into mmsys path select function

Signed-off-by: Yongqiang Niu 
---
 drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +
 1 file changed, 71 insertions(+), 69 deletions(-)

diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c 
b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 6c03282..64c8030 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -106,141 +106,161 @@ struct mtk_mmsys {
.clk_driver = "clk-mt8183-mm",
 };
 
-static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
 {
-   unsigned int value;
+   unsigned int addr, value, reg;
 
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
-   *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
value = OVL0_MOUT_EN_COLOR0;
} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
-   *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
value = OVL_MOUT_EN_RDMA;
} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
-   *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD_MOUT_EN_RDMA0;
} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
-   *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
value = UFOE_MOUT_EN_DSI0;
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
-   *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
value = OVL1_MOUT_EN_COLOR1;
} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
-   *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
value = GAMMA_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
-   *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD1_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI3;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI3;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+