Re: [PATCH v4 10/19] drm/msm/dpu: inline SSPP_BLK macros

2023-07-03 Thread Abhinav Kumar 




On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:

To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.

Tested-by: Marijn Suijten 
Signed-off-by: Dmitry Baryshkov 
---


I checked a few of the entries to make sure there are no copy-paste 
errors but not all of them.


I am going to rely on Marijn's checksum method results that there were 
no differences in the checksum and go ahead with my,


Reviewed-by: Abhinav Kumar

Re: [PATCH v4 10/19] drm/msm/dpu: inline SSPP_BLK macros

2023-06-27 Thread Marijn Suijten 
On 2023-06-20 00:25:10, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
> 
> Tested-by: Marijn Suijten 
> Signed-off-by: Dmitry Baryshkov 

Validated that this incurs no changes by checksumming a stripped
dpu_hw_catalog.o.

Reviewed-by: Marijn Suijten 

> ---
>  .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h   |  81 +++---
>  .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h|  81 +++---
>  .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h|  81 +++---
>  .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h   |  81 +++---
>  .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h|  81 +++---
>  .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h|  41 +--
>  .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h|  21 +++-
>  .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h|  41 +--
>  .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h   |  21 +++-
>  .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h|  21 +++-
>  .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h|  81 +++---
>  .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h|  41 +--
>  .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  81 +++---
>  .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h|  81 +++---
>  .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h| 101 ++
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c|  12 ---
>  16 files changed, 751 insertions(+), 196 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h 
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index 6660a55909e7..fd0081469a82 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -71,22 +71,71 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = {
>  };
>  
>  static const struct dpu_sspp_cfg msm8998_sspp[] = {
> - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1ac, VIG_MSM8998_MASK,
> - msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
> - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1ac, VIG_MSM8998_MASK,
> - msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
> - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1ac, VIG_MSM8998_MASK,
> - msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
> - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1ac, VIG_MSM8998_MASK,
> - msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
> - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1ac, DMA_MSM8998_MASK,
> - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
> - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK,
> - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
> - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
> - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
> - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
> - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
> + {
> + .name = "sspp_0", .id = SSPP_VIG0,
> + .base = 0x4000, .len = 0x1ac,
> + .features = VIG_MSM8998_MASK,
> + .sblk = _vig_sblk_0,
> + .xin_id = 0,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG0,
> + }, {
> + .name = "sspp_1", .id = SSPP_VIG1,
> + .base = 0x6000, .len = 0x1ac,
> + .features = VIG_MSM8998_MASK,
> + .sblk = _vig_sblk_1,
> + .xin_id = 4,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG1,
> + }, {
> + .name = "sspp_2", .id = SSPP_VIG2,
> + .base = 0x8000, .len = 0x1ac,
> + .features = VIG_MSM8998_MASK,
> + .sblk = _vig_sblk_2,
> + .xin_id = 8,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG2,
> + }, {
> + .name = "sspp_3", .id = SSPP_VIG3,
> + .base = 0xa000, .len = 0x1ac,
> + .features = VIG_MSM8998_MASK,
> + .sblk = _vig_sblk_3,
> + .xin_id = 12,
> + .type = SSPP_TYPE_VIG,
> + .clk_ctrl = DPU_CLK_CTRL_VIG3,
> + }, {
> + .name = "sspp_8", .id = SSPP_DMA0,
> + .base = 0x24000, .len = 0x1ac,
> + .features = DMA_MSM8998_MASK,
> + .sblk = _dma_sblk_0,
> + .xin_id = 1,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl = DPU_CLK_CTRL_DMA0,
> + }, {
> + .name = "sspp_9", .id = SSPP_DMA1,
> + .base = 0x26000, .len = 0x1ac,
> + .features = DMA_MSM8998_MASK,
> + .sblk = _dma_sblk_1,
> + .xin_id = 5,
> + .type = SSPP_TYPE_DMA,
> + .clk_ctrl =

[PATCH v4 10/19] drm/msm/dpu: inline SSPP_BLK macros

2023-06-19 Thread Dmitry Baryshkov 
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.

Tested-by: Marijn Suijten 
Signed-off-by: Dmitry Baryshkov 
---
 .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h   |  81 +++---
 .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h|  81 +++---
 .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h|  81 +++---
 .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h   |  81 +++---
 .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h|  81 +++---
 .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h|  41 +--
 .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h|  21 +++-
 .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h|  41 +--
 .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h   |  21 +++-
 .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h|  21 +++-
 .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h|  81 +++---
 .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h|  41 +--
 .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  81 +++---
 .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h|  81 +++---
 .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h| 101 ++
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c|  12 ---
 16 files changed, 751 insertions(+), 196 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 6660a55909e7..fd0081469a82 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -71,22 +71,71 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = {
 };
 
 static const struct dpu_sspp_cfg msm8998_sspp[] = {
-   SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1ac, VIG_MSM8998_MASK,
-   msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
-   SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1ac, VIG_MSM8998_MASK,
-   msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
-   SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1ac, VIG_MSM8998_MASK,
-   msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
-   SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1ac, VIG_MSM8998_MASK,
-   msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
-   SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1ac, DMA_MSM8998_MASK,
-   sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
-   SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK,
-   sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
-   SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
-   sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
-   SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK,
-   sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
+   {
+   .name = "sspp_0", .id = SSPP_VIG0,
+   .base = 0x4000, .len = 0x1ac,
+   .features = VIG_MSM8998_MASK,
+   .sblk = _vig_sblk_0,
+   .xin_id = 0,
+   .type = SSPP_TYPE_VIG,
+   .clk_ctrl = DPU_CLK_CTRL_VIG0,
+   }, {
+   .name = "sspp_1", .id = SSPP_VIG1,
+   .base = 0x6000, .len = 0x1ac,
+   .features = VIG_MSM8998_MASK,
+   .sblk = _vig_sblk_1,
+   .xin_id = 4,
+   .type = SSPP_TYPE_VIG,
+   .clk_ctrl = DPU_CLK_CTRL_VIG1,
+   }, {
+   .name = "sspp_2", .id = SSPP_VIG2,
+   .base = 0x8000, .len = 0x1ac,
+   .features = VIG_MSM8998_MASK,
+   .sblk = _vig_sblk_2,
+   .xin_id = 8,
+   .type = SSPP_TYPE_VIG,
+   .clk_ctrl = DPU_CLK_CTRL_VIG2,
+   }, {
+   .name = "sspp_3", .id = SSPP_VIG3,
+   .base = 0xa000, .len = 0x1ac,
+   .features = VIG_MSM8998_MASK,
+   .sblk = _vig_sblk_3,
+   .xin_id = 12,
+   .type = SSPP_TYPE_VIG,
+   .clk_ctrl = DPU_CLK_CTRL_VIG3,
+   }, {
+   .name = "sspp_8", .id = SSPP_DMA0,
+   .base = 0x24000, .len = 0x1ac,
+   .features = DMA_MSM8998_MASK,
+   .sblk = _dma_sblk_0,
+   .xin_id = 1,
+   .type = SSPP_TYPE_DMA,
+   .clk_ctrl = DPU_CLK_CTRL_DMA0,
+   }, {
+   .name = "sspp_9", .id = SSPP_DMA1,
+   .base = 0x26000, .len = 0x1ac,
+   .features = DMA_MSM8998_MASK,
+   .sblk = _dma_sblk_1,
+   .xin_id = 5,
+   .type = SSPP_TYPE_DMA,
+   .clk_ctrl = DPU_CLK_CTRL_DMA1,
+   }, {
+   .name = "sspp_10", .id = SSPP_DMA2,
+   .base = 0x28000, .len = 0x1ac,
+   .features = DMA_CURSOR_MSM8998_MASK,
+   .sblk = _dma_sblk_2,
+   .xin_id =