Re: [PATCH v4 17/19] drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros

2023-07-03 Thread Abhinav Kumar 




On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:

To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.

Tested-by: Marijn Suijten 
Signed-off-by: Dmitry Baryshkov 
---


Reviewed-by: Abhinav Kumar

Re: [PATCH v4 17/19] drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros

2023-06-27 Thread Marijn Suijten 
On 2023-06-20 00:25:17, Dmitry Baryshkov wrote:
> To simplify making changes to the hardware block definitions, expand
> corresponding macros. This way making all the changes are more obvious
> and visible in the source files.
> 
> Tested-by: Marijn Suijten 
> Signed-off-by: Dmitry Baryshkov 

Validated that this incurs no changes by checksumming a stripped
dpu_hw_catalog.o.

Reviewed-by: Marijn Suijten 

> ---
>  .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h   |  52 ++--
>  .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h|  53 ++--
>  .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h|  55 ++--
>  .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h   |  82 +---
>  .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h|  55 ++--
>  .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h|  28 +++-
>  .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h|  15 ++-
>  .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h|  28 +++-
>  .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h   |  15 ++-
>  .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h|  15 ++-
>  .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h|  55 ++--
>  .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h|  41 --
>  .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  | 120 +-
>  .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h|  55 ++--
>  .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h|  55 ++--
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c|  30 -
>  16 files changed, 545 insertions(+), 209 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h 
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index 9181d3ef8013..4ce25ed4e36f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -241,18 +241,46 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = {
>  };
>  
>  static const struct dpu_intf_cfg msm8998_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 
> MSM_DP_CONTROLLER_0, 21, INTF_SDM845_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
> - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 
> MSM_DSI_CONTROLLER_0, 21, INTF_SDM845_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
> - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 
> MSM_DSI_CONTROLLER_1, 21, INTF_SDM845_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
> - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, 
> INTF_SDM845_MASK,
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> + {
> + .name = "intf_0", .id = INTF_0,
> + .base = 0x6a000, .len = 0x280,
> + .features = INTF_SDM845_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 21,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_1", .id = INTF_1,
> + .base = 0x6a800, .len = 0x280,
> + .features = INTF_SDM845_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_0,
> + .prog_fetch_lines_worst_case = 21,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_2", .id = INTF_2,
> + .base = 0x6b000, .len = 0x280,
> + .features = INTF_SDM845_MASK,
> + .type = INTF_DSI,
> + .controller_id = MSM_DSI_CONTROLLER_1,
> + .prog_fetch_lines_worst_case = 21,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> + .intr_tear_rd_ptr = -1,
> + }, {
> + .name = "intf_3", .id = INTF_3,
> + .base = 0x6b800, .len = 0x280,
> + .features = INTF_SDM845_MASK,
> + .type = INTF_HDMI,
> + .prog_fetch_lines_worst_case = 21,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> + .intr_tear_rd_ptr = -1,
> + },
>  };
>  
>  static const struct dpu_perf_cfg msm8998_perf_data = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h 
> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 8119a81ff260..5ad82b109ebb 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/

[PATCH v4 17/19] drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros

2023-06-19 Thread Dmitry Baryshkov 
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.

Tested-by: Marijn Suijten 
Signed-off-by: Dmitry Baryshkov 
---
 .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h   |  52 ++--
 .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h|  53 ++--
 .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h|  55 ++--
 .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h   |  82 +---
 .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h|  55 ++--
 .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h|  28 +++-
 .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h|  15 ++-
 .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h|  28 +++-
 .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h   |  15 ++-
 .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h|  15 ++-
 .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h|  55 ++--
 .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h|  41 --
 .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  | 120 +-
 .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h|  55 ++--
 .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h|  55 ++--
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c|  30 -
 16 files changed, 545 insertions(+), 209 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 9181d3ef8013..4ce25ed4e36f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -241,18 +241,46 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = {
 };
 
 static const struct dpu_intf_cfg msm8998_intf[] = {
-   INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 
MSM_DP_CONTROLLER_0, 21, INTF_SDM845_MASK,
-   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
-   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-   INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 
MSM_DSI_CONTROLLER_0, 21, INTF_SDM845_MASK,
-   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
-   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
-   INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 
MSM_DSI_CONTROLLER_1, 21, INTF_SDM845_MASK,
-   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
-   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
-   INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, 
INTF_SDM845_MASK,
-   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
-   DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
+   {
+   .name = "intf_0", .id = INTF_0,
+   .base = 0x6a000, .len = 0x280,
+   .features = INTF_SDM845_MASK,
+   .type = INTF_DP,
+   .controller_id = MSM_DP_CONTROLLER_0,
+   .prog_fetch_lines_worst_case = 21,
+   .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+   .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+   .intr_tear_rd_ptr = -1,
+   }, {
+   .name = "intf_1", .id = INTF_1,
+   .base = 0x6a800, .len = 0x280,
+   .features = INTF_SDM845_MASK,
+   .type = INTF_DSI,
+   .controller_id = MSM_DSI_CONTROLLER_0,
+   .prog_fetch_lines_worst_case = 21,
+   .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+   .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+   .intr_tear_rd_ptr = -1,
+   }, {
+   .name = "intf_2", .id = INTF_2,
+   .base = 0x6b000, .len = 0x280,
+   .features = INTF_SDM845_MASK,
+   .type = INTF_DSI,
+   .controller_id = MSM_DSI_CONTROLLER_1,
+   .prog_fetch_lines_worst_case = 21,
+   .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
+   .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
+   .intr_tear_rd_ptr = -1,
+   }, {
+   .name = "intf_3", .id = INTF_3,
+   .base = 0x6b800, .len = 0x280,
+   .features = INTF_SDM845_MASK,
+   .type = INTF_HDMI,
+   .prog_fetch_lines_worst_case = 21,
+   .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+   .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+   .intr_tear_rd_ptr = -1,
+   },
 };
 
 static const struct dpu_perf_cfg msm8998_perf_data = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h 
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 8119a81ff260..5ad82b109ebb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -257,18 +257,47 @@ static const struct dpu_dsc_cfg sdm845_dsc[] = {
 };
 
 static const struct dpu_intf_cfg sdm845_intf[] = {
-   INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 
MSM_DP_CONTROLLER_0, 24, INTF_