Re: [PATCH v5 01/17] clk: meson: g12a: prefix private CLK IDs defines with PRIV
On Tue 30 May 2023 at 17:56, Neil Armstrong wrote:
> On 30/05/2023 10:08, Jerome Brunet wrote:
>> On Tue 30 May 2023 at 09:38, Neil Armstrong
>> wrote:
>>
>>> Exposing should not be done in a single commit anymore due to
>>> dt-bindings enforced rules.
>>>
>>> Prepend PRIV to the private CLK IDs so we can add new clock to
>>> the bindings header and in a separate commit remove such private
>>> define and switch to the public CLK IDs identifier.
>>>
>>> This refers to a discussion at [1] with Arnd and Krzysztof.
>>>
>>> [1]
>>> https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba1...@app.fastmail.com/
>>>
>>> Signed-off-by: Neil Armstrong
>> I understand the discussion reported but I don't really like this
>> CLKID_PRIV_
>> It adds another layer of IDs.
>> I'd much prefer if we just expose all the IDs. That would comply with DT
>> new policy and be much simpler in the long run.
>
> While it would solve everything at long term, we'll still need to do the move
> in 3 steps (add PRIV, add to bindings, remove PRIV defined), and we should
> still
It would certainly be a lot simpler if we could expose the IDs like we used
to one last time to comply with this new requirement.
If it is really not possible, then yes, we will have no choice but to
bounce using this namespace trick. If there is no other choice, then I'd
prefer if it was done for all the IDs of the different SoCs, once and for all.
> decide how to handle NR_CLKS.
>
Can't this stay in the driver header ? This needs to be updated only the
actually adding the clock, isn't it ?
Maybe I'm missing something ...
> Neil
>
>>
>>> ---
>>> drivers/clk/meson/g12a.c | 628
>>> +++
>>> drivers/clk/meson/g12a.h | 260 ++--
>>> 2 files changed, 444 insertions(+), 444 deletions(-)
>>>
>>> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
>>> index 310accf94830..d2e481ae2429 100644
>>> --- a/drivers/clk/meson/g12a.c
>>> +++ b/drivers/clk/meson/g12a.c
>>> @@ -4255,8 +4255,8 @@ static struct clk_hw_onecell_data
>>> g12a_hw_onecell_data = {
>>> [CLKID_FCLK_DIV7] = _fclk_div7.hw,
>>> [CLKID_FCLK_DIV2P5] = _fclk_div2p5.hw,
>>> [CLKID_GP0_PLL] = _gp0_pll.hw,
>>> - [CLKID_MPEG_SEL]= _mpeg_clk_sel.hw,
>>> - [CLKID_MPEG_DIV]= _mpeg_clk_div.hw,
>>> + [CLKID_PRIV_MPEG_SEL] = _mpeg_clk_sel.hw,
>>> + [CLKID_PRIV_MPEG_DIV] = _mpeg_clk_div.hw,
>>> [CLKID_CLK81] = _clk81.hw,
>>> [CLKID_MPLL0] = _mpll0.hw,
>>> [CLKID_MPLL1] = _mpll1.hw,
>>> @@ -4307,25 +4307,25 @@ static struct clk_hw_onecell_data
>>> g12a_hw_onecell_data = {
>>> [CLKID_UART2] = _uart2.hw,
>>> [CLKID_VPU_INTR]= _vpu_intr.hw,
>>> [CLKID_GIC] = _gic.hw,
>>> - [CLKID_SD_EMMC_A_CLK0_SEL] = _sd_emmc_a_clk0_sel.hw,
>>> - [CLKID_SD_EMMC_A_CLK0_DIV] = _sd_emmc_a_clk0_div.hw,
>>> + [CLKID_PRIV_SD_EMMC_A_CLK0_SEL] = _sd_emmc_a_clk0_sel.hw,
>>> + [CLKID_PRIV_SD_EMMC_A_CLK0_DIV] = _sd_emmc_a_clk0_div.hw,
>>> [CLKID_SD_EMMC_A_CLK0] = _sd_emmc_a_clk0.hw,
>>> - [CLKID_SD_EMMC_B_CLK0_SEL] = _sd_emmc_b_clk0_sel.hw,
>>> - [CLKID_SD_EMMC_B_CLK0_DIV] = _sd_emmc_b_clk0_div.hw,
>>> + [CLKID_PRIV_SD_EMMC_B_CLK0_SEL] = _sd_emmc_b_clk0_sel.hw,
>>> + [CLKID_PRIV_SD_EMMC_B_CLK0_DIV] = _sd_emmc_b_clk0_div.hw,
>>> [CLKID_SD_EMMC_B_CLK0] = _sd_emmc_b_clk0.hw,
>>> - [CLKID_SD_EMMC_C_CLK0_SEL] = _sd_emmc_c_clk0_sel.hw,
>>> - [CLKID_SD_EMMC_C_CLK0_DIV] = _sd_emmc_c_clk0_div.hw,
>>> + [CLKID_PRIV_SD_EMMC_C_CLK0_SEL] = _sd_emmc_c_clk0_sel.hw,
>>> + [CLKID_PRIV_SD_EMMC_C_CLK0_DIV] = _sd_emmc_c_clk0_div.hw,
>>> [CLKID_SD_EMMC_C_CLK0] = _sd_emmc_c_clk0.hw,
>>> - [CLKID_MPLL0_DIV] = _mpll0_div.hw,
>>> - [CLKID_MPLL1_DIV] = _mpll1_div.hw,
>>> - [CLKID_MPLL2_DIV] = _mpll2_div.hw,
>>> - [CLKID_MPLL3_DIV] = _mpll3_div.hw,
>>> - [CLKID_FCLK_DIV2_DIV] = _fclk_div2_div.hw,
>>> - [CLKID_FCLK_DIV3_DIV] = _fclk_div3_div.hw,
>>> - [CLKID_FCLK_DIV4_DIV] = _fclk_div4_div.hw,
>>> - [CLKID_FCLK_DIV5_DIV] = _fclk_div5_div.hw,
>>> - [CLKID_FCLK_DIV7_DIV] = _fclk_div7_div.hw,
>>> - [CLKID_FCLK_DIV2P5_DIV] = _fclk_div2p5_div.hw,
>>> + [CLKID_PRIV_MPLL0_DIV] = _mpll0_div.hw,
>>> + [CLKID_PRIV_MPLL1_DIV] = _mpll1_div.hw,
>>> + [CLKID_PRIV_MPLL2_DIV] =
Re: [PATCH v5 01/17] clk: meson: g12a: prefix private CLK IDs defines with PRIV
On 30/05/2023 10:08, Jerome Brunet wrote:
On Tue 30 May 2023 at 09:38, Neil Armstrong wrote:
Exposing should not be done in a single commit anymore due to
dt-bindings enforced rules.
Prepend PRIV to the private CLK IDs so we can add new clock to
the bindings header and in a separate commit remove such private
define and switch to the public CLK IDs identifier.
This refers to a discussion at [1] with Arnd and Krzysztof.
[1]
https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba1...@app.fastmail.com/
Signed-off-by: Neil Armstrong
I understand the discussion reported but I don't really like this CLKID_PRIV_
It adds another layer of IDs.
I'd much prefer if we just expose all the IDs. That would comply with DT
new policy and be much simpler in the long run.
While it would solve everything at long term, we'll still need to do the move
in 3 steps (add PRIV, add to bindings, remove PRIV defined), and we should still
decide how to handle NR_CLKS.
Neil
---
drivers/clk/meson/g12a.c | 628 +++
drivers/clk/meson/g12a.h | 260 ++--
2 files changed, 444 insertions(+), 444 deletions(-)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 310accf94830..d2e481ae2429 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -4255,8 +4255,8 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
[CLKID_FCLK_DIV7] = _fclk_div7.hw,
[CLKID_FCLK_DIV2P5] = _fclk_div2p5.hw,
[CLKID_GP0_PLL] = _gp0_pll.hw,
- [CLKID_MPEG_SEL]= _mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV]= _mpeg_clk_div.hw,
+ [CLKID_PRIV_MPEG_SEL] = _mpeg_clk_sel.hw,
+ [CLKID_PRIV_MPEG_DIV] = _mpeg_clk_div.hw,
[CLKID_CLK81] = _clk81.hw,
[CLKID_MPLL0] = _mpll0.hw,
[CLKID_MPLL1] = _mpll1.hw,
@@ -4307,25 +4307,25 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data
= {
[CLKID_UART2] = _uart2.hw,
[CLKID_VPU_INTR]= _vpu_intr.hw,
[CLKID_GIC] = _gic.hw,
- [CLKID_SD_EMMC_A_CLK0_SEL] = _sd_emmc_a_clk0_sel.hw,
- [CLKID_SD_EMMC_A_CLK0_DIV] = _sd_emmc_a_clk0_div.hw,
+ [CLKID_PRIV_SD_EMMC_A_CLK0_SEL] = _sd_emmc_a_clk0_sel.hw,
+ [CLKID_PRIV_SD_EMMC_A_CLK0_DIV] = _sd_emmc_a_clk0_div.hw,
[CLKID_SD_EMMC_A_CLK0] = _sd_emmc_a_clk0.hw,
- [CLKID_SD_EMMC_B_CLK0_SEL] = _sd_emmc_b_clk0_sel.hw,
- [CLKID_SD_EMMC_B_CLK0_DIV] = _sd_emmc_b_clk0_div.hw,
+ [CLKID_PRIV_SD_EMMC_B_CLK0_SEL] = _sd_emmc_b_clk0_sel.hw,
+ [CLKID_PRIV_SD_EMMC_B_CLK0_DIV] = _sd_emmc_b_clk0_div.hw,
[CLKID_SD_EMMC_B_CLK0] = _sd_emmc_b_clk0.hw,
- [CLKID_SD_EMMC_C_CLK0_SEL] = _sd_emmc_c_clk0_sel.hw,
- [CLKID_SD_EMMC_C_CLK0_DIV] = _sd_emmc_c_clk0_div.hw,
+ [CLKID_PRIV_SD_EMMC_C_CLK0_SEL] = _sd_emmc_c_clk0_sel.hw,
+ [CLKID_PRIV_SD_EMMC_C_CLK0_DIV] = _sd_emmc_c_clk0_div.hw,
[CLKID_SD_EMMC_C_CLK0] = _sd_emmc_c_clk0.hw,
- [CLKID_MPLL0_DIV] = _mpll0_div.hw,
- [CLKID_MPLL1_DIV] = _mpll1_div.hw,
- [CLKID_MPLL2_DIV] = _mpll2_div.hw,
- [CLKID_MPLL3_DIV] = _mpll3_div.hw,
- [CLKID_FCLK_DIV2_DIV] = _fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = _fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = _fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = _fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = _fclk_div7_div.hw,
- [CLKID_FCLK_DIV2P5_DIV] = _fclk_div2p5_div.hw,
+ [CLKID_PRIV_MPLL0_DIV] = _mpll0_div.hw,
+ [CLKID_PRIV_MPLL1_DIV] = _mpll1_div.hw,
+ [CLKID_PRIV_MPLL2_DIV] = _mpll2_div.hw,
+ [CLKID_PRIV_MPLL3_DIV] = _mpll3_div.hw,
+ [CLKID_PRIV_FCLK_DIV2_DIV] = _fclk_div2_div.hw,
+ [CLKID_PRIV_FCLK_DIV3_DIV] = _fclk_div3_div.hw,
+ [CLKID_PRIV_FCLK_DIV4_DIV] = _fclk_div4_div.hw,
+ [CLKID_PRIV_FCLK_DIV5_DIV] = _fclk_div5_div.hw,
+ [CLKID_PRIV_FCLK_DIV7_DIV] = _fclk_div7_div.hw,
+ [CLKID_PRIV_FCLK_DIV2P5_DIV]= _fclk_div2p5_div.hw,
[CLKID_HIFI_PLL]= _hifi_pll.hw,
[CLKID_VCLK2_VENCI0]= _vclk2_venci0.hw,
[CLKID_VCLK2_VENCI1]= _vclk2_venci1.hw,
@@
Re: [PATCH v5 01/17] clk: meson: g12a: prefix private CLK IDs defines with PRIV
On Tue 30 May 2023 at 09:38, Neil Armstrong wrote:
> Exposing should not be done in a single commit anymore due to
> dt-bindings enforced rules.
>
> Prepend PRIV to the private CLK IDs so we can add new clock to
> the bindings header and in a separate commit remove such private
> define and switch to the public CLK IDs identifier.
>
> This refers to a discussion at [1] with Arnd and Krzysztof.
>
> [1]
> https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba1...@app.fastmail.com/
>
> Signed-off-by: Neil Armstrong
I understand the discussion reported but I don't really like this CLKID_PRIV_
It adds another layer of IDs.
I'd much prefer if we just expose all the IDs. That would comply with DT
new policy and be much simpler in the long run.
> ---
> drivers/clk/meson/g12a.c | 628
> +++
> drivers/clk/meson/g12a.h | 260 ++--
> 2 files changed, 444 insertions(+), 444 deletions(-)
>
> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
> index 310accf94830..d2e481ae2429 100644
> --- a/drivers/clk/meson/g12a.c
> +++ b/drivers/clk/meson/g12a.c
> @@ -4255,8 +4255,8 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data
> = {
> [CLKID_FCLK_DIV7] = _fclk_div7.hw,
> [CLKID_FCLK_DIV2P5] = _fclk_div2p5.hw,
> [CLKID_GP0_PLL] = _gp0_pll.hw,
> - [CLKID_MPEG_SEL]= _mpeg_clk_sel.hw,
> - [CLKID_MPEG_DIV]= _mpeg_clk_div.hw,
> + [CLKID_PRIV_MPEG_SEL] = _mpeg_clk_sel.hw,
> + [CLKID_PRIV_MPEG_DIV] = _mpeg_clk_div.hw,
> [CLKID_CLK81] = _clk81.hw,
> [CLKID_MPLL0] = _mpll0.hw,
> [CLKID_MPLL1] = _mpll1.hw,
> @@ -4307,25 +4307,25 @@ static struct clk_hw_onecell_data
> g12a_hw_onecell_data = {
> [CLKID_UART2] = _uart2.hw,
> [CLKID_VPU_INTR]= _vpu_intr.hw,
> [CLKID_GIC] = _gic.hw,
> - [CLKID_SD_EMMC_A_CLK0_SEL] = _sd_emmc_a_clk0_sel.hw,
> - [CLKID_SD_EMMC_A_CLK0_DIV] = _sd_emmc_a_clk0_div.hw,
> + [CLKID_PRIV_SD_EMMC_A_CLK0_SEL] = _sd_emmc_a_clk0_sel.hw,
> + [CLKID_PRIV_SD_EMMC_A_CLK0_DIV] = _sd_emmc_a_clk0_div.hw,
> [CLKID_SD_EMMC_A_CLK0] = _sd_emmc_a_clk0.hw,
> - [CLKID_SD_EMMC_B_CLK0_SEL] = _sd_emmc_b_clk0_sel.hw,
> - [CLKID_SD_EMMC_B_CLK0_DIV] = _sd_emmc_b_clk0_div.hw,
> + [CLKID_PRIV_SD_EMMC_B_CLK0_SEL] = _sd_emmc_b_clk0_sel.hw,
> + [CLKID_PRIV_SD_EMMC_B_CLK0_DIV] = _sd_emmc_b_clk0_div.hw,
> [CLKID_SD_EMMC_B_CLK0] = _sd_emmc_b_clk0.hw,
> - [CLKID_SD_EMMC_C_CLK0_SEL] = _sd_emmc_c_clk0_sel.hw,
> - [CLKID_SD_EMMC_C_CLK0_DIV] = _sd_emmc_c_clk0_div.hw,
> + [CLKID_PRIV_SD_EMMC_C_CLK0_SEL] = _sd_emmc_c_clk0_sel.hw,
> + [CLKID_PRIV_SD_EMMC_C_CLK0_DIV] = _sd_emmc_c_clk0_div.hw,
> [CLKID_SD_EMMC_C_CLK0] = _sd_emmc_c_clk0.hw,
> - [CLKID_MPLL0_DIV] = _mpll0_div.hw,
> - [CLKID_MPLL1_DIV] = _mpll1_div.hw,
> - [CLKID_MPLL2_DIV] = _mpll2_div.hw,
> - [CLKID_MPLL3_DIV] = _mpll3_div.hw,
> - [CLKID_FCLK_DIV2_DIV] = _fclk_div2_div.hw,
> - [CLKID_FCLK_DIV3_DIV] = _fclk_div3_div.hw,
> - [CLKID_FCLK_DIV4_DIV] = _fclk_div4_div.hw,
> - [CLKID_FCLK_DIV5_DIV] = _fclk_div5_div.hw,
> - [CLKID_FCLK_DIV7_DIV] = _fclk_div7_div.hw,
> - [CLKID_FCLK_DIV2P5_DIV] = _fclk_div2p5_div.hw,
> + [CLKID_PRIV_MPLL0_DIV] = _mpll0_div.hw,
> + [CLKID_PRIV_MPLL1_DIV] = _mpll1_div.hw,
> + [CLKID_PRIV_MPLL2_DIV] = _mpll2_div.hw,
> + [CLKID_PRIV_MPLL3_DIV] = _mpll3_div.hw,
> + [CLKID_PRIV_FCLK_DIV2_DIV] = _fclk_div2_div.hw,
> + [CLKID_PRIV_FCLK_DIV3_DIV] = _fclk_div3_div.hw,
> + [CLKID_PRIV_FCLK_DIV4_DIV] = _fclk_div4_div.hw,
> + [CLKID_PRIV_FCLK_DIV5_DIV] = _fclk_div5_div.hw,
> + [CLKID_PRIV_FCLK_DIV7_DIV] = _fclk_div7_div.hw,
> + [CLKID_PRIV_FCLK_DIV2P5_DIV]= _fclk_div2p5_div.hw,
> [CLKID_HIFI_PLL]= _hifi_pll.hw,
> [CLKID_VCLK2_VENCI0]= _vclk2_venci0.hw,
> [CLKID_VCLK2_VENCI1]= _vclk2_venci1.hw,
> @@ -4346,56 +4346,56 @@ static struct clk_hw_onecell_data
> g12a_hw_onecell_data = {
> [CLKID_VCLK2_VENCLMMC] = _vclk2_venclmmc.hw,
> [CLKID_VCLK2_VENCL]
[PATCH v5 01/17] clk: meson: g12a: prefix private CLK IDs defines with PRIV
Exposing should not be done in a single commit anymore due to
dt-bindings enforced rules.
Prepend PRIV to the private CLK IDs so we can add new clock to
the bindings header and in a separate commit remove such private
define and switch to the public CLK IDs identifier.
This refers to a discussion at [1] with Arnd and Krzysztof.
[1]
https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba1...@app.fastmail.com/
Signed-off-by: Neil Armstrong
---
drivers/clk/meson/g12a.c | 628 +++
drivers/clk/meson/g12a.h | 260 ++--
2 files changed, 444 insertions(+), 444 deletions(-)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 310accf94830..d2e481ae2429 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -4255,8 +4255,8 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
[CLKID_FCLK_DIV7] = _fclk_div7.hw,
[CLKID_FCLK_DIV2P5] = _fclk_div2p5.hw,
[CLKID_GP0_PLL] = _gp0_pll.hw,
- [CLKID_MPEG_SEL]= _mpeg_clk_sel.hw,
- [CLKID_MPEG_DIV]= _mpeg_clk_div.hw,
+ [CLKID_PRIV_MPEG_SEL] = _mpeg_clk_sel.hw,
+ [CLKID_PRIV_MPEG_DIV] = _mpeg_clk_div.hw,
[CLKID_CLK81] = _clk81.hw,
[CLKID_MPLL0] = _mpll0.hw,
[CLKID_MPLL1] = _mpll1.hw,
@@ -4307,25 +4307,25 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data
= {
[CLKID_UART2] = _uart2.hw,
[CLKID_VPU_INTR]= _vpu_intr.hw,
[CLKID_GIC] = _gic.hw,
- [CLKID_SD_EMMC_A_CLK0_SEL] = _sd_emmc_a_clk0_sel.hw,
- [CLKID_SD_EMMC_A_CLK0_DIV] = _sd_emmc_a_clk0_div.hw,
+ [CLKID_PRIV_SD_EMMC_A_CLK0_SEL] = _sd_emmc_a_clk0_sel.hw,
+ [CLKID_PRIV_SD_EMMC_A_CLK0_DIV] = _sd_emmc_a_clk0_div.hw,
[CLKID_SD_EMMC_A_CLK0] = _sd_emmc_a_clk0.hw,
- [CLKID_SD_EMMC_B_CLK0_SEL] = _sd_emmc_b_clk0_sel.hw,
- [CLKID_SD_EMMC_B_CLK0_DIV] = _sd_emmc_b_clk0_div.hw,
+ [CLKID_PRIV_SD_EMMC_B_CLK0_SEL] = _sd_emmc_b_clk0_sel.hw,
+ [CLKID_PRIV_SD_EMMC_B_CLK0_DIV] = _sd_emmc_b_clk0_div.hw,
[CLKID_SD_EMMC_B_CLK0] = _sd_emmc_b_clk0.hw,
- [CLKID_SD_EMMC_C_CLK0_SEL] = _sd_emmc_c_clk0_sel.hw,
- [CLKID_SD_EMMC_C_CLK0_DIV] = _sd_emmc_c_clk0_div.hw,
+ [CLKID_PRIV_SD_EMMC_C_CLK0_SEL] = _sd_emmc_c_clk0_sel.hw,
+ [CLKID_PRIV_SD_EMMC_C_CLK0_DIV] = _sd_emmc_c_clk0_div.hw,
[CLKID_SD_EMMC_C_CLK0] = _sd_emmc_c_clk0.hw,
- [CLKID_MPLL0_DIV] = _mpll0_div.hw,
- [CLKID_MPLL1_DIV] = _mpll1_div.hw,
- [CLKID_MPLL2_DIV] = _mpll2_div.hw,
- [CLKID_MPLL3_DIV] = _mpll3_div.hw,
- [CLKID_FCLK_DIV2_DIV] = _fclk_div2_div.hw,
- [CLKID_FCLK_DIV3_DIV] = _fclk_div3_div.hw,
- [CLKID_FCLK_DIV4_DIV] = _fclk_div4_div.hw,
- [CLKID_FCLK_DIV5_DIV] = _fclk_div5_div.hw,
- [CLKID_FCLK_DIV7_DIV] = _fclk_div7_div.hw,
- [CLKID_FCLK_DIV2P5_DIV] = _fclk_div2p5_div.hw,
+ [CLKID_PRIV_MPLL0_DIV] = _mpll0_div.hw,
+ [CLKID_PRIV_MPLL1_DIV] = _mpll1_div.hw,
+ [CLKID_PRIV_MPLL2_DIV] = _mpll2_div.hw,
+ [CLKID_PRIV_MPLL3_DIV] = _mpll3_div.hw,
+ [CLKID_PRIV_FCLK_DIV2_DIV] = _fclk_div2_div.hw,
+ [CLKID_PRIV_FCLK_DIV3_DIV] = _fclk_div3_div.hw,
+ [CLKID_PRIV_FCLK_DIV4_DIV] = _fclk_div4_div.hw,
+ [CLKID_PRIV_FCLK_DIV5_DIV] = _fclk_div5_div.hw,
+ [CLKID_PRIV_FCLK_DIV7_DIV] = _fclk_div7_div.hw,
+ [CLKID_PRIV_FCLK_DIV2P5_DIV]= _fclk_div2p5_div.hw,
[CLKID_HIFI_PLL]= _hifi_pll.hw,
[CLKID_VCLK2_VENCI0]= _vclk2_venci0.hw,
[CLKID_VCLK2_VENCI1]= _vclk2_venci1.hw,
@@ -4346,56 +4346,56 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data
= {
[CLKID_VCLK2_VENCLMMC] = _vclk2_venclmmc.hw,
[CLKID_VCLK2_VENCL] = _vclk2_vencl.hw,
[CLKID_VCLK2_OTHER1]= _vclk2_other1.hw,
- [CLKID_FIXED_PLL_DCO] = _fixed_pll_dco.hw,
- [CLKID_SYS_PLL_DCO] = _sys_pll_dco.hw,
- [CLKID_GP0_PLL_DCO] = _gp0_pll_dco.hw,
- [CLKID_HIFI_PLL_DCO]
