Re: [PATCH v5 5/9] drm/bridge: tc358764: Add DSI to LVDS bridge driver
On 27.07.2018 12:30, Laurent Pinchart wrote: > Hi Andrzej, > > On Friday, 27 July 2018 10:17:50 EEST Andrzej Hajda wrote: >> On 26.07.2018 09:36, Archit Taneja wrote: >>> On Wednesday 25 July 2018 09:16 PM, Andrzej Hajda wrote: Add a drm_bridge driver for the Toshiba TC358764 DSI to LVDS bridge. Changes in v4: - removed license blob, - ordered includes, - added error handling, - fixed reset GPIO handling, - added missing calls to the panel, - custom OF graph code replaced with helpers, - removed tc358764_poweroff from remove callback. v5: - fixed supply names, - fixed broken console - added connector to fb_helper, - added detach callback - unbinding works, - fixed typo in error checking code, - removed sparse bridge->encoder check - core does it already. Signed-off-by: Andrzej Hajda Signed-off-by: Maciej Purski [ a.ha...@samsung.com: v4, v5 ] Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/bridge/Kconfig| 8 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/tc358764.c | 499 ++ 3 files changed, 508 insertions(+) create mode 100644 drivers/gpu/drm/bridge/tc358764.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index fa2c7997e2fd..f3da8a716833 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -110,6 +110,14 @@ config DRM_THINE_THC63LVD1024 ---help--- Thine THC63LVD1024 LVDS/parallel converter driver. +config DRM_TOSHIBA_TC358764 + tristate "TC358764 DSI/LVDS bridge" + depends on DRM && DRM_PANEL + depends on OF + select DRM_MIPI_DSI + help +Toshiba TC358764 DSI/LVDS bridge driver. + config DRM_TOSHIBA_TC358767 tristate "Toshiba TC358767 eDP bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 35f88d48ec20..bf7c0cecf227 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o obj-$(CONFIG_DRM_SII902X) += sii902x.o obj-$(CONFIG_DRM_SII9234) += sii9234.o obj-$(CONFIG_DRM_THINE_THC63LVD1024) += thc63lvd1024.o +obj-$(CONFIG_DRM_TOSHIBA_TC358764) += tc358764.o obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ diff --git a/drivers/gpu/drm/bridge/tc358764.c b/drivers/gpu/drm/bridge/tc358764.c new file mode 100644 index ..779bc5fce22a --- /dev/null +++ b/drivers/gpu/drm/bridge/tc358764.c @@ -0,0 +1,499 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Samsung Electronics Co., Ltd + * + * Authors: + *Andrzej Hajda + *Maciej Purski + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FLD_MASK(start, end)(((1 << ((start) - (end) + 1)) - 1) << (end)) +#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) + +/* PPI layer registers */ +#define PPI_STARTPPI 0x0104 /* START control bit */ +#define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */ +#define PPI_LANEENABLE0x0134 /* Enables each lane */ +#define PPI_TX_RX_TA 0x013C /* BTA timing parameters */ +#define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */ +#define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */ +#define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */ +#define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */ +#define PPI_START_FUNCTION1 + +/* DSI layer registers */ +#define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */ +#define DSI_LANEENABLE0x0210 /* Enables each lane */ +#define DSI_RX_START 1 + +/* Video path registers */ +#define VP_CTRL 0x0450 /* Video Path Control */ +#define VP_CTRL_MSF(v)FLD_VAL(v, 0, 0) /* Magic square in RGB666 > */ +#define VP_CTRL_VTGEN(v) FLD_VAL(v, 4, 4) /* Use chip clock for timing */ +#define VP_CTRL_EVTMODE(v)FLD_VAL(v, 5, 5) /* Event mode */ +#define VP_CTRL_RGB888(v) FLD_VAL(v, 8, 8) /* RGB888 mode */ +#define VP_CTRL_VSDELAY(v)FLD_VAL(v, 31, 20) /* VSYNC delay */ +#define VP_CTRL_HSPOL BIT(17) /* Polarity
Re: [PATCH v5 5/9] drm/bridge: tc358764: Add DSI to LVDS bridge driver
Hi Andrzej, On Friday, 27 July 2018 10:17:50 EEST Andrzej Hajda wrote: > On 26.07.2018 09:36, Archit Taneja wrote: > > On Wednesday 25 July 2018 09:16 PM, Andrzej Hajda wrote: > >> Add a drm_bridge driver for the Toshiba TC358764 DSI to LVDS bridge. > >> > >> Changes in v4: > >> - removed license blob, > >> - ordered includes, > >> - added error handling, > >> - fixed reset GPIO handling, > >> - added missing calls to the panel, > >> - custom OF graph code replaced with helpers, > >> - removed tc358764_poweroff from remove callback. > >> v5: > >> - fixed supply names, > >> - fixed broken console - added connector to fb_helper, > >> - added detach callback - unbinding works, > >> - fixed typo in error checking code, > >> - removed sparse bridge->encoder check - core does it already. > >> > >> Signed-off-by: Andrzej Hajda > >> Signed-off-by: Maciej Purski > >> [ a.ha...@samsung.com: v4, v5 ] > >> Signed-off-by: Andrzej Hajda > >> --- > >> > >> drivers/gpu/drm/bridge/Kconfig| 8 + > >> drivers/gpu/drm/bridge/Makefile | 1 + > >> drivers/gpu/drm/bridge/tc358764.c | 499 ++ > >> 3 files changed, 508 insertions(+) > >> create mode 100644 drivers/gpu/drm/bridge/tc358764.c > >> > >> diff --git a/drivers/gpu/drm/bridge/Kconfig > >> b/drivers/gpu/drm/bridge/Kconfig index fa2c7997e2fd..f3da8a716833 100644 > >> --- a/drivers/gpu/drm/bridge/Kconfig > >> +++ b/drivers/gpu/drm/bridge/Kconfig > >> @@ -110,6 +110,14 @@ config DRM_THINE_THC63LVD1024 > >> > >>---help--- > >> > >> Thine THC63LVD1024 LVDS/parallel converter driver. > >> > >> +config DRM_TOSHIBA_TC358764 > >> + tristate "TC358764 DSI/LVDS bridge" > >> + depends on DRM && DRM_PANEL > >> + depends on OF > >> + select DRM_MIPI_DSI > >> + help > >> +Toshiba TC358764 DSI/LVDS bridge driver. > >> + > >> > >> config DRM_TOSHIBA_TC358767 > >> > >>tristate "Toshiba TC358767 eDP bridge" > >>depends on OF > >> > >> diff --git a/drivers/gpu/drm/bridge/Makefile > >> b/drivers/gpu/drm/bridge/Makefile index 35f88d48ec20..bf7c0cecf227 > >> 100644 > >> --- a/drivers/gpu/drm/bridge/Makefile > >> +++ b/drivers/gpu/drm/bridge/Makefile > >> @@ -10,6 +10,7 @@ obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o > >> > >> obj-$(CONFIG_DRM_SII902X) += sii902x.o > >> obj-$(CONFIG_DRM_SII9234) += sii9234.o > >> obj-$(CONFIG_DRM_THINE_THC63LVD1024) += thc63lvd1024.o > >> > >> +obj-$(CONFIG_DRM_TOSHIBA_TC358764) += tc358764.o > >> > >> obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o > >> obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ > >> obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ > >> > >> diff --git a/drivers/gpu/drm/bridge/tc358764.c > >> b/drivers/gpu/drm/bridge/tc358764.c new file mode 100644 > >> index ..779bc5fce22a > >> --- /dev/null > >> +++ b/drivers/gpu/drm/bridge/tc358764.c > >> @@ -0,0 +1,499 @@ > >> +// SPDX-License-Identifier: GPL-2.0 > >> +/* > >> + * Copyright (C) 2018 Samsung Electronics Co., Ltd > >> + * > >> + * Authors: > >> + *Andrzej Hajda > >> + *Maciej Purski > >> + */ > >> + > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> + > >> +#define FLD_MASK(start, end)(((1 << ((start) - (end) + 1)) - 1) << > >> (end)) +#define FLD_VAL(val, start, end) (((val) << (end)) & > >> FLD_MASK(start, end)) + > >> +/* PPI layer registers */ > >> +#define PPI_STARTPPI 0x0104 /* START control bit */ > >> +#define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */ > >> +#define PPI_LANEENABLE0x0134 /* Enables each lane */ > >> +#define PPI_TX_RX_TA 0x013C /* BTA timing parameters */ > >> +#define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */ > >> +#define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */ > >> +#define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */ > >> +#define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */ > >> +#define PPI_START_FUNCTION1 > >> + > >> +/* DSI layer registers */ > >> +#define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */ > >> +#define DSI_LANEENABLE0x0210 /* Enables each lane */ > >> +#define DSI_RX_START 1 > >> + > >> +/* Video path registers */ > >> +#define VP_CTRL 0x0450 /* Video Path Control */ > >> +#define VP_CTRL_MSF(v)FLD_VAL(v, 0, 0) /* Magic square in > >> RGB666 */ > >> +#define VP_CTRL_VTGEN(v) FLD_VAL(v, 4, 4) /* Use chip clock for timing > >> */ > >> +#define VP_CTRL_EVTMODE(v)FLD_VAL(v, 5, 5) /* Event mode */ > >> +#define VP_CTRL_RGB888(v) FLD_VAL(v, 8, 8) /* RGB888 mode */ > >> +#define VP_CTRL_VSDELAY(v)FLD_VAL(v, 31, 20) /* VSYNC delay */ > >> +#define VP_CTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */ > >> +#define
Re: [PATCH v5 5/9] drm/bridge: tc358764: Add DSI to LVDS bridge driver
On 26.07.2018 09:36, Archit Taneja wrote: > > On Wednesday 25 July 2018 09:16 PM, Andrzej Hajda wrote: >> Add a drm_bridge driver for the Toshiba TC358764 DSI to LVDS bridge. >> >> Changes in v4: >> - removed license blob, >> - ordered includes, >> - added error handling, >> - fixed reset GPIO handling, >> - added missing calls to the panel, >> - custom OF graph code replaced with helpers, >> - removed tc358764_poweroff from remove callback. >> v5: >> - fixed supply names, >> - fixed broken console - added connector to fb_helper, >> - added detach callback - unbinding works, >> - fixed typo in error checking code, >> - removed sparse bridge->encoder check - core does it already. >> >> Signed-off-by: Andrzej Hajda >> Signed-off-by: Maciej Purski >> [ a.ha...@samsung.com: v4, v5 ] >> Signed-off-by: Andrzej Hajda >> --- >> drivers/gpu/drm/bridge/Kconfig| 8 + >> drivers/gpu/drm/bridge/Makefile | 1 + >> drivers/gpu/drm/bridge/tc358764.c | 499 ++ >> 3 files changed, 508 insertions(+) >> create mode 100644 drivers/gpu/drm/bridge/tc358764.c >> >> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig >> index fa2c7997e2fd..f3da8a716833 100644 >> --- a/drivers/gpu/drm/bridge/Kconfig >> +++ b/drivers/gpu/drm/bridge/Kconfig >> @@ -110,6 +110,14 @@ config DRM_THINE_THC63LVD1024 >> ---help--- >>Thine THC63LVD1024 LVDS/parallel converter driver. >> >> +config DRM_TOSHIBA_TC358764 >> +tristate "TC358764 DSI/LVDS bridge" >> +depends on DRM && DRM_PANEL >> +depends on OF >> +select DRM_MIPI_DSI >> +help >> + Toshiba TC358764 DSI/LVDS bridge driver. >> + >> config DRM_TOSHIBA_TC358767 >> tristate "Toshiba TC358767 eDP bridge" >> depends on OF >> diff --git a/drivers/gpu/drm/bridge/Makefile >> b/drivers/gpu/drm/bridge/Makefile >> index 35f88d48ec20..bf7c0cecf227 100644 >> --- a/drivers/gpu/drm/bridge/Makefile >> +++ b/drivers/gpu/drm/bridge/Makefile >> @@ -10,6 +10,7 @@ obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o >> obj-$(CONFIG_DRM_SII902X) += sii902x.o >> obj-$(CONFIG_DRM_SII9234) += sii9234.o >> obj-$(CONFIG_DRM_THINE_THC63LVD1024) += thc63lvd1024.o >> +obj-$(CONFIG_DRM_TOSHIBA_TC358764) += tc358764.o >> obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o >> obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ >> obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ >> diff --git a/drivers/gpu/drm/bridge/tc358764.c >> b/drivers/gpu/drm/bridge/tc358764.c >> new file mode 100644 >> index ..779bc5fce22a >> --- /dev/null >> +++ b/drivers/gpu/drm/bridge/tc358764.c >> @@ -0,0 +1,499 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Copyright (C) 2018 Samsung Electronics Co., Ltd >> + * >> + * Authors: >> + * Andrzej Hajda >> + * Maciej Purski >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#define FLD_MASK(start, end)(((1 << ((start) - (end) + 1)) - 1) << >> (end)) >> +#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) >> + >> +/* PPI layer registers */ >> +#define PPI_STARTPPI0x0104 /* START control bit */ >> +#define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */ >> +#define PPI_LANEENABLE 0x0134 /* Enables each lane */ >> +#define PPI_TX_RX_TA0x013C /* BTA timing parameters */ >> +#define PPI_D0S_CLRSIPOCOUNT0x0164 /* Assertion timer for Lane 0 */ >> +#define PPI_D1S_CLRSIPOCOUNT0x0168 /* Assertion timer for Lane 1 */ >> +#define PPI_D2S_CLRSIPOCOUNT0x016C /* Assertion timer for Lane 2 */ >> +#define PPI_D3S_CLRSIPOCOUNT0x0170 /* Assertion timer for Lane 3 */ >> +#define PPI_START_FUNCTION 1 >> + >> +/* DSI layer registers */ >> +#define DSI_STARTDSI0x0204 /* START control bit of DSI-TX */ >> +#define DSI_LANEENABLE 0x0210 /* Enables each lane */ >> +#define DSI_RX_START1 >> + >> +/* Video path registers */ >> +#define VP_CTRL 0x0450 /* Video Path Control */ >> +#define VP_CTRL_MSF(v) FLD_VAL(v, 0, 0) /* Magic square in >> RGB666 */ >> +#define VP_CTRL_VTGEN(v)FLD_VAL(v, 4, 4) /* Use chip clock for timing */ >> +#define VP_CTRL_EVTMODE(v) FLD_VAL(v, 5, 5) /* Event mode */ >> +#define VP_CTRL_RGB888(v) FLD_VAL(v, 8, 8) /* RGB888 mode */ >> +#define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */ >> +#define VP_CTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */ >> +#define VP_CTRL_DEPOL BIT(18) /* Polarity of DE signal */ >> +#define VP_CTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */ >> +#define VP_HTIM10x0454 /* Horizontal Timing Control 1 */ >> +#define VP_HTIM1_HBP(v) FLD_VAL(v, 24, 16) >> +#define VP_HTIM1_HSYNC(v) FLD_VAL(v, 8, 0) >> +#define VP_HTIM2
Re: [PATCH v5 5/9] drm/bridge: tc358764: Add DSI to LVDS bridge driver
On Wednesday 25 July 2018 09:16 PM, Andrzej Hajda wrote: Add a drm_bridge driver for the Toshiba TC358764 DSI to LVDS bridge. Changes in v4: - removed license blob, - ordered includes, - added error handling, - fixed reset GPIO handling, - added missing calls to the panel, - custom OF graph code replaced with helpers, - removed tc358764_poweroff from remove callback. v5: - fixed supply names, - fixed broken console - added connector to fb_helper, - added detach callback - unbinding works, - fixed typo in error checking code, - removed sparse bridge->encoder check - core does it already. Signed-off-by: Andrzej Hajda Signed-off-by: Maciej Purski [ a.ha...@samsung.com: v4, v5 ] Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/bridge/Kconfig| 8 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/tc358764.c | 499 ++ 3 files changed, 508 insertions(+) create mode 100644 drivers/gpu/drm/bridge/tc358764.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index fa2c7997e2fd..f3da8a716833 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -110,6 +110,14 @@ config DRM_THINE_THC63LVD1024 ---help--- Thine THC63LVD1024 LVDS/parallel converter driver. +config DRM_TOSHIBA_TC358764 + tristate "TC358764 DSI/LVDS bridge" + depends on DRM && DRM_PANEL + depends on OF + select DRM_MIPI_DSI + help + Toshiba TC358764 DSI/LVDS bridge driver. + config DRM_TOSHIBA_TC358767 tristate "Toshiba TC358767 eDP bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 35f88d48ec20..bf7c0cecf227 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o obj-$(CONFIG_DRM_SII902X) += sii902x.o obj-$(CONFIG_DRM_SII9234) += sii9234.o obj-$(CONFIG_DRM_THINE_THC63LVD1024) += thc63lvd1024.o +obj-$(CONFIG_DRM_TOSHIBA_TC358764) += tc358764.o obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ diff --git a/drivers/gpu/drm/bridge/tc358764.c b/drivers/gpu/drm/bridge/tc358764.c new file mode 100644 index ..779bc5fce22a --- /dev/null +++ b/drivers/gpu/drm/bridge/tc358764.c @@ -0,0 +1,499 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Samsung Electronics Co., Ltd + * + * Authors: + * Andrzej Hajda + * Maciej Purski + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FLD_MASK(start, end)(((1 << ((start) - (end) + 1)) - 1) << (end)) +#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) + +/* PPI layer registers */ +#define PPI_STARTPPI 0x0104 /* START control bit */ +#define PPI_LPTXTIMECNT0x0114 /* LPTX timing signal */ +#define PPI_LANEENABLE 0x0134 /* Enables each lane */ +#define PPI_TX_RX_TA 0x013C /* BTA timing parameters */ +#define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */ +#define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */ +#define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */ +#define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */ +#define PPI_START_FUNCTION 1 + +/* DSI layer registers */ +#define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */ +#define DSI_LANEENABLE 0x0210 /* Enables each lane */ +#define DSI_RX_START 1 + +/* Video path registers */ +#define VP_CTRL0x0450 /* Video Path Control */ +#define VP_CTRL_MSF(v) FLD_VAL(v, 0, 0) /* Magic square in RGB666 */ +#define VP_CTRL_VTGEN(v) FLD_VAL(v, 4, 4) /* Use chip clock for timing */ +#define VP_CTRL_EVTMODE(v) FLD_VAL(v, 5, 5) /* Event mode */ +#define VP_CTRL_RGB888(v) FLD_VAL(v, 8, 8) /* RGB888 mode */ +#define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */ +#define VP_CTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */ +#define VP_CTRL_DEPOL BIT(18) /* Polarity of DE signal */ +#define VP_CTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */ +#define VP_HTIM1 0x0454 /* Horizontal Timing Control 1 */ +#define VP_HTIM1_HBP(v)FLD_VAL(v, 24, 16) +#define VP_HTIM1_HSYNC(v) FLD_VAL(v, 8, 0) +#define VP_HTIM2 0x0458 /* Horizontal Timing Control 2 */ +#define VP_HTIM2_HFP(v)FLD_VAL(v, 24, 16) +#define VP_HTIM2_HACT(v) FLD_VAL(v, 10, 0) +#define VP_VTIM1 0x045C /* Vertical Timing Control 1 */ +#define VP_VTIM1_VBP(v)FLD_VAL(v, 23, 16) +#define VP_VTIM1_VSYNC(v) FLD_VAL(v, 7, 0) +#define VP_VTIM2 0x0460 /* Vertical Timing Control 2 */ +#define
[PATCH v5 5/9] drm/bridge: tc358764: Add DSI to LVDS bridge driver
Add a drm_bridge driver for the Toshiba TC358764 DSI to LVDS bridge. Changes in v4: - removed license blob, - ordered includes, - added error handling, - fixed reset GPIO handling, - added missing calls to the panel, - custom OF graph code replaced with helpers, - removed tc358764_poweroff from remove callback. v5: - fixed supply names, - fixed broken console - added connector to fb_helper, - added detach callback - unbinding works, - fixed typo in error checking code, - removed sparse bridge->encoder check - core does it already. Signed-off-by: Andrzej Hajda Signed-off-by: Maciej Purski [ a.ha...@samsung.com: v4, v5 ] Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/bridge/Kconfig| 8 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/tc358764.c | 499 ++ 3 files changed, 508 insertions(+) create mode 100644 drivers/gpu/drm/bridge/tc358764.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index fa2c7997e2fd..f3da8a716833 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -110,6 +110,14 @@ config DRM_THINE_THC63LVD1024 ---help--- Thine THC63LVD1024 LVDS/parallel converter driver. +config DRM_TOSHIBA_TC358764 + tristate "TC358764 DSI/LVDS bridge" + depends on DRM && DRM_PANEL + depends on OF + select DRM_MIPI_DSI + help + Toshiba TC358764 DSI/LVDS bridge driver. + config DRM_TOSHIBA_TC358767 tristate "Toshiba TC358767 eDP bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 35f88d48ec20..bf7c0cecf227 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o obj-$(CONFIG_DRM_SII902X) += sii902x.o obj-$(CONFIG_DRM_SII9234) += sii9234.o obj-$(CONFIG_DRM_THINE_THC63LVD1024) += thc63lvd1024.o +obj-$(CONFIG_DRM_TOSHIBA_TC358764) += tc358764.o obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/ obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/ diff --git a/drivers/gpu/drm/bridge/tc358764.c b/drivers/gpu/drm/bridge/tc358764.c new file mode 100644 index ..779bc5fce22a --- /dev/null +++ b/drivers/gpu/drm/bridge/tc358764.c @@ -0,0 +1,499 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Samsung Electronics Co., Ltd + * + * Authors: + * Andrzej Hajda + * Maciej Purski + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FLD_MASK(start, end)(((1 << ((start) - (end) + 1)) - 1) << (end)) +#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) + +/* PPI layer registers */ +#define PPI_STARTPPI 0x0104 /* START control bit */ +#define PPI_LPTXTIMECNT0x0114 /* LPTX timing signal */ +#define PPI_LANEENABLE 0x0134 /* Enables each lane */ +#define PPI_TX_RX_TA 0x013C /* BTA timing parameters */ +#define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */ +#define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */ +#define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */ +#define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */ +#define PPI_START_FUNCTION 1 + +/* DSI layer registers */ +#define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */ +#define DSI_LANEENABLE 0x0210 /* Enables each lane */ +#define DSI_RX_START 1 + +/* Video path registers */ +#define VP_CTRL0x0450 /* Video Path Control */ +#define VP_CTRL_MSF(v) FLD_VAL(v, 0, 0) /* Magic square in RGB666 */ +#define VP_CTRL_VTGEN(v) FLD_VAL(v, 4, 4) /* Use chip clock for timing */ +#define VP_CTRL_EVTMODE(v) FLD_VAL(v, 5, 5) /* Event mode */ +#define VP_CTRL_RGB888(v) FLD_VAL(v, 8, 8) /* RGB888 mode */ +#define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */ +#define VP_CTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */ +#define VP_CTRL_DEPOL BIT(18) /* Polarity of DE signal */ +#define VP_CTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */ +#define VP_HTIM1 0x0454 /* Horizontal Timing Control 1 */ +#define VP_HTIM1_HBP(v)FLD_VAL(v, 24, 16) +#define VP_HTIM1_HSYNC(v) FLD_VAL(v, 8, 0) +#define VP_HTIM2 0x0458 /* Horizontal Timing Control 2 */ +#define VP_HTIM2_HFP(v)FLD_VAL(v, 24, 16) +#define VP_HTIM2_HACT(v) FLD_VAL(v, 10, 0) +#define VP_VTIM1 0x045C /* Vertical Timing Control 1 */ +#define VP_VTIM1_VBP(v)FLD_VAL(v, 23, 16) +#define VP_VTIM1_VSYNC(v) FLD_VAL(v, 7, 0) +#define VP_VTIM2 0x0460 /* Vertical Timing Control 2 */ +#define VP_VTIM2_VFP(v)FLD_VAL(v, 23, 16) +#define VP_VTIM2_VACT(v)
