Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK

2021-02-09 Thread Guenter Roeck 
On Tue, Feb 02, 2021 at 04:12:31PM +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu 
> 
> This patch add component POSTMASK.
> 
> Signed-off-by: Yongqiang Niu 
> Signed-off-by: Hsin-Yi Wang 
> Reviewed-by: CK Hu 
> ---
[ ... ]
>  
> +void mtk_postmask_config(struct device *dev, unsigned int w,

static

> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, priv->regs,
> +   DISP_POSTMASK_SIZE);
> + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, >cmdq_reg,
> +   priv->regs, DISP_POSTMASK_CFG);
> +}
> +
> +void mtk_postmask_start(struct device *dev)

static

> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN);
> +}
> +
> +void mtk_postmask_stop(struct device *dev)

static

> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN);
> +}
> +
>  static void mtk_aal_config(struct device *dev, unsigned int w,
>  unsigned int h, unsigned int vrefresh,
>  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
>   .bgclr_in_off = mtk_ovl_bgclr_in_off,
>  };
>  
> +static const struct mtk_ddp_comp_funcs ddp_postmask = {
> + .clk_enable = mtk_ddp_clk_enable,
> + .clk_disable = mtk_ddp_clk_disable,
> + .config = mtk_postmask_config,
> + .start = mtk_postmask_start,
> + .stop = mtk_postmask_stop,
> +};
> +
>  static const struct mtk_ddp_comp_funcs ddp_rdma = {
>   .clk_enable = mtk_rdma_clk_enable,
>   .clk_disable = mtk_rdma_clk_disable,
> @@ -448,6 +488,7 @@ static const char * const 
> mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
>   [MTK_DISP_MUTEX] = "mutex",
>   [MTK_DISP_OD] = "od",
>   [MTK_DISP_BLS] = "bls",
> + [MTK_DISP_POSTMASK] = "postmask",
>  };
>  
>  struct mtk_ddp_comp_match {
> @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match {
>  };
>  
>  static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] 
> = {
> - [DDP_COMPONENT_AAL0]= { MTK_DISP_AAL,   0, _aal },
> - [DDP_COMPONENT_AAL1]= { MTK_DISP_AAL,   1, _aal },
> - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS,   0, NULL },
> - [DDP_COMPONENT_CCORR]   = { MTK_DISP_CCORR, 0, _ccorr },
> - [DDP_COMPONENT_COLOR0]  = { MTK_DISP_COLOR, 0, _color },
> - [DDP_COMPONENT_COLOR1]  = { MTK_DISP_COLOR, 1, _color },
> - [DDP_COMPONENT_DITHER]  = { MTK_DISP_DITHER,0, _dither },
> - [DDP_COMPONENT_DPI0]= { MTK_DPI,0, _dpi },
> - [DDP_COMPONENT_DPI1]= { MTK_DPI,1, _dpi },
> - [DDP_COMPONENT_DSI0]= { MTK_DSI,0, _dsi },
> - [DDP_COMPONENT_DSI1]= { MTK_DSI,1, _dsi },
> - [DDP_COMPONENT_DSI2]= { MTK_DSI,2, _dsi },
> - [DDP_COMPONENT_DSI3]= { MTK_DSI,3, _dsi },
> - [DDP_COMPONENT_GAMMA]   = { MTK_DISP_GAMMA, 0, _gamma },
> - [DDP_COMPONENT_OD0] = { MTK_DISP_OD,0, _od },
> - [DDP_COMPONENT_OD1] = { MTK_DISP_OD,1, _od },
> - [DDP_COMPONENT_OVL0]= { MTK_DISP_OVL,   0, _ovl },
> - [DDP_COMPONENT_OVL1]= { MTK_DISP_OVL,   1, _ovl },
> - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L,0, _ovl },
> - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L,1, _ovl },
> - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L,2, _ovl },
> - [DDP_COMPONENT_PWM0]= { MTK_DISP_PWM,   0, NULL },
> - [DDP_COMPONENT_PWM1]= { MTK_DISP_PWM,   1, NULL },
> - [DDP_COMPONENT_PWM2]= { MTK_DISP_PWM,   2, NULL },
> - [DDP_COMPONENT_RDMA0]   = { MTK_DISP_RDMA,  0, _rdma },
> - [DDP_COMPONENT_RDMA1]   = { MTK_DISP_RDMA,  1, _rdma },
> - [DDP_COMPONENT_RDMA2]   = { MTK_DISP_RDMA,  2, _rdma },
> - [DDP_COMPONENT_UFOE]= { MTK_DISP_UFOE,  0, _ufoe },
> - [DDP_COMPONENT_WDMA0]   = { MTK_DISP_WDMA,  0, NULL },
> - [DDP_COMPONENT_WDMA1]   = { MTK_DISP_WDMA,  1, NULL },
> + [DDP_COMPONENT_AAL0]= { MTK_DISP_AAL,   0, _aal },
> + [DDP_COMPONENT_AAL1]= { MTK_DISP_AAL,   1, _aal },
> + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS,   0, NULL },
> + [DDP_COMPONENT_CCORR]   = { MTK_DISP_CCORR, 0, _ccorr },
> + [DDP_COMPONENT_COLOR0]  = { MTK_DISP_COLOR, 0, _color },
> + [DDP_COMPONENT_COLOR1]  = { MTK_DISP_COLOR, 1, _color },
> + [DDP_COMPONENT_DITHER]  = { MTK_DISP_DITHER,0, _dither 
> },
> + [DDP_COMPONENT_DPI0]= { MTK_DPI,0, _dpi },
> + [DDP_COMPONENT_DPI1]= { MTK_DPI,

Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK

2021-02-02 Thread CK Hu 
Hi, Hsin-Yi:

On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote:
> From: Yongqiang Niu 
> 
> This patch add component POSTMASK.

Reviewed-by: CK Hu 

> 
> Signed-off-by: Yongqiang Niu 
> Signed-off-by: Hsin-Yi Wang 
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++--
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
>  2 files changed, 73 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index b6c4e73031ca6..0a84ae53eb72a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -64,6 +64,12 @@
>  
>  #define AAL_EN   BIT(0)
>  
> +#define DISP_POSTMASK_EN 0x
> +#define POSTMASK_EN  BIT(0)
> +#define DISP_POSTMASK_CFG0x0020
> +#define POSTMASK_RELAY_MODE  BIT(0)
> +#define DISP_POSTMASK_SIZE   0x0030
> +
>  #define DISP_DITHERING   BIT(2)
>  #define DITHER_LSB_ERR_SHIFT_R(x)(((x) & 0x7) << 28)
>  #define DITHER_OVFLW_BIT_R(x)(((x) & 0x7) << 24)
> @@ -204,6 +210,32 @@ static void mtk_ufoe_start(struct device *dev)
>   writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
>  }
>  
> +void mtk_postmask_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, priv->regs,
> +   DISP_POSTMASK_SIZE);
> + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, >cmdq_reg,
> +   priv->regs, DISP_POSTMASK_CFG);
> +}
> +
> +void mtk_postmask_start(struct device *dev)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN);
> +}
> +
> +void mtk_postmask_stop(struct device *dev)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN);
> +}
> +
>  static void mtk_aal_config(struct device *dev, unsigned int w,
>  unsigned int h, unsigned int vrefresh,
>  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
>   .bgclr_in_off = mtk_ovl_bgclr_in_off,
>  };
>  
> +static const struct mtk_ddp_comp_funcs ddp_postmask = {
> + .clk_enable = mtk_ddp_clk_enable,
> + .clk_disable = mtk_ddp_clk_disable,
> + .config = mtk_postmask_config,
> + .start = mtk_postmask_start,
> + .stop = mtk_postmask_stop,
> +};
> +
>  static const struct mtk_ddp_comp_funcs ddp_rdma = {
>   .clk_enable = mtk_rdma_clk_enable,
>   .clk_disable = mtk_rdma_clk_disable,
> @@ -448,6 +488,7 @@ static const char * const 
> mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
>   [MTK_DISP_MUTEX] = "mutex",
>   [MTK_DISP_OD] = "od",
>   [MTK_DISP_BLS] = "bls",
> + [MTK_DISP_POSTMASK] = "postmask",
>  };
>  
>  struct mtk_ddp_comp_match {
> @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match {
>  };
>  
>  static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] 
> = {
> - [DDP_COMPONENT_AAL0]= { MTK_DISP_AAL,   0, _aal },
> - [DDP_COMPONENT_AAL1]= { MTK_DISP_AAL,   1, _aal },
> - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS,   0, NULL },
> - [DDP_COMPONENT_CCORR]   = { MTK_DISP_CCORR, 0, _ccorr },
> - [DDP_COMPONENT_COLOR0]  = { MTK_DISP_COLOR, 0, _color },
> - [DDP_COMPONENT_COLOR1]  = { MTK_DISP_COLOR, 1, _color },
> - [DDP_COMPONENT_DITHER]  = { MTK_DISP_DITHER,0, _dither },
> - [DDP_COMPONENT_DPI0]= { MTK_DPI,0, _dpi },
> - [DDP_COMPONENT_DPI1]= { MTK_DPI,1, _dpi },
> - [DDP_COMPONENT_DSI0]= { MTK_DSI,0, _dsi },
> - [DDP_COMPONENT_DSI1]= { MTK_DSI,1, _dsi },
> - [DDP_COMPONENT_DSI2]= { MTK_DSI,2, _dsi },
> - [DDP_COMPONENT_DSI3]= { MTK_DSI,3, _dsi },
> - [DDP_COMPONENT_GAMMA]   = { MTK_DISP_GAMMA, 0, _gamma },
> - [DDP_COMPONENT_OD0] = { MTK_DISP_OD,0, _od },
> - [DDP_COMPONENT_OD1] = { MTK_DISP_OD,1, _od },
> - [DDP_COMPONENT_OVL0]= { MTK_DISP_OVL,   0, _ovl },
> - [DDP_COMPONENT_OVL1]= { MTK_DISP_OVL,   1, _ovl },
> - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L,0, _ovl },
> - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L,1, _ovl },
> - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L,2, _ovl },
> - [DDP_COMPONENT_PWM0]= { MTK_DISP_PWM,   0, NULL },
> - [DDP_COMPONENT_PWM1]= { MTK_DISP_PWM,   1, NULL },
> -

[PATCH v6 2/8] drm/mediatek: add component POSTMASK

2021-02-02 Thread Hsin-Yi Wang 
From: Yongqiang Niu 

This patch add component POSTMASK.

Signed-off-by: Yongqiang Niu 
Signed-off-by: Hsin-Yi Wang 
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++--
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 2 files changed, 73 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index b6c4e73031ca6..0a84ae53eb72a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -64,6 +64,12 @@
 
 #define AAL_EN BIT(0)
 
+#define DISP_POSTMASK_EN   0x
+#define POSTMASK_ENBIT(0)
+#define DISP_POSTMASK_CFG  0x0020
+#define POSTMASK_RELAY_MODEBIT(0)
+#define DISP_POSTMASK_SIZE 0x0030
+
 #define DISP_DITHERING BIT(2)
 #define DITHER_LSB_ERR_SHIFT_R(x)  (((x) & 0x7) << 28)
 #define DITHER_OVFLW_BIT_R(x)  (((x) & 0x7) << 24)
@@ -204,6 +210,32 @@ static void mtk_ufoe_start(struct device *dev)
writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
 }
 
+void mtk_postmask_config(struct device *dev, unsigned int w,
+   unsigned int h, unsigned int vrefresh,
+   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+   struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+   mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, priv->regs,
+ DISP_POSTMASK_SIZE);
+   mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, >cmdq_reg,
+ priv->regs, DISP_POSTMASK_CFG);
+}
+
+void mtk_postmask_start(struct device *dev)
+{
+   struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+   writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN);
+}
+
+void mtk_postmask_stop(struct device *dev)
+{
+   struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+   writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN);
+}
+
 static void mtk_aal_config(struct device *dev, unsigned int w,
   unsigned int h, unsigned int vrefresh,
   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
.bgclr_in_off = mtk_ovl_bgclr_in_off,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_postmask = {
+   .clk_enable = mtk_ddp_clk_enable,
+   .clk_disable = mtk_ddp_clk_disable,
+   .config = mtk_postmask_config,
+   .start = mtk_postmask_start,
+   .stop = mtk_postmask_stop,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_rdma = {
.clk_enable = mtk_rdma_clk_enable,
.clk_disable = mtk_rdma_clk_disable,
@@ -448,6 +488,7 @@ static const char * const 
mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
[MTK_DISP_BLS] = "bls",
+   [MTK_DISP_POSTMASK] = "postmask",
 };
 
 struct mtk_ddp_comp_match {
@@ -457,36 +498,37 @@ struct mtk_ddp_comp_match {
 };
 
 static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = 
{
-   [DDP_COMPONENT_AAL0]= { MTK_DISP_AAL,   0, _aal },
-   [DDP_COMPONENT_AAL1]= { MTK_DISP_AAL,   1, _aal },
-   [DDP_COMPONENT_BLS] = { MTK_DISP_BLS,   0, NULL },
-   [DDP_COMPONENT_CCORR]   = { MTK_DISP_CCORR, 0, _ccorr },
-   [DDP_COMPONENT_COLOR0]  = { MTK_DISP_COLOR, 0, _color },
-   [DDP_COMPONENT_COLOR1]  = { MTK_DISP_COLOR, 1, _color },
-   [DDP_COMPONENT_DITHER]  = { MTK_DISP_DITHER,0, _dither },
-   [DDP_COMPONENT_DPI0]= { MTK_DPI,0, _dpi },
-   [DDP_COMPONENT_DPI1]= { MTK_DPI,1, _dpi },
-   [DDP_COMPONENT_DSI0]= { MTK_DSI,0, _dsi },
-   [DDP_COMPONENT_DSI1]= { MTK_DSI,1, _dsi },
-   [DDP_COMPONENT_DSI2]= { MTK_DSI,2, _dsi },
-   [DDP_COMPONENT_DSI3]= { MTK_DSI,3, _dsi },
-   [DDP_COMPONENT_GAMMA]   = { MTK_DISP_GAMMA, 0, _gamma },
-   [DDP_COMPONENT_OD0] = { MTK_DISP_OD,0, _od },
-   [DDP_COMPONENT_OD1] = { MTK_DISP_OD,1, _od },
-   [DDP_COMPONENT_OVL0]= { MTK_DISP_OVL,   0, _ovl },
-   [DDP_COMPONENT_OVL1]= { MTK_DISP_OVL,   1, _ovl },
-   [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L,0, _ovl },
-   [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L,1, _ovl },
-   [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L,2, _ovl },
-   [DDP_COMPONENT_PWM0]= { MTK_DISP_PWM,   0, NULL },
-   [DDP_COMPONENT_PWM1]= { MTK_DISP_PWM,   1, NULL },
-   [DDP_COMPONENT_PWM2]= { MTK_DISP_PWM,   2, NULL },
-   [DDP_COMPONENT_RDMA0]   = { MTK_DISP_RDMA,  0, _rdma },
-   [DDP_COMPONENT_RDMA1]   = { MTK_DISP_RDMA,  1, _rdma },
-   [DDP_COMPONENT_RDMA2]   = {