Re: [PATCH v6 5/5] arm64: dts: qcom: sm8450: add dp controller
Hi,
On 23/03/2023 15:38, Bjorn Andersson wrote:
On Tue, Mar 21, 2023 at 09:51:34PM +0100, Konrad Dybcio wrote:
On 17.03.2023 16:06, Neil Armstrong wrote:
@@ -2783,6 +2790,78 @@ opp-5 {
};
};
+ mdss_dp0: displayport-controller@ae9 {
+ compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
+ reg = <0 0xae9 0 0x200>,
+ <0 0xae90200 0 0x200>,
+ <0 0xae90400 0 0xc00>,
+ <0 0xae91000 0 0x400>,
+ <0 0xae91400 0 0x400>;
+ interrupt-parent = <>;
+ interrupts = <12>;
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_DPTX0_AUX_CLK>,
+< DISP_CC_MDSS_DPTX0_LINK_CLK>,
+<
DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+<
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
I applied this locally and noticed line has 2x 8 spaces.. Bjorn, could
you please take care of that when applying?
Thanks for pointing it out. I did correct it, and I had to do the same
in sm8350.dtsi.
@Neil, please run checkpatch --strict, it will highlight these errors.
Thx, sorry... usually I don't miss such errors, won't happen again.
Neil
Thanks,
Bjorn
Re: [PATCH v6 5/5] arm64: dts: qcom: sm8450: add dp controller
On Tue, Mar 21, 2023 at 09:51:34PM +0100, Konrad Dybcio wrote:
> On 17.03.2023 16:06, Neil Armstrong wrote:
> > @@ -2783,6 +2790,78 @@ opp-5 {
> > };
> > };
> >
> > + mdss_dp0: displayport-controller@ae9 {
> > + compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
> > + reg = <0 0xae9 0 0x200>,
> > + <0 0xae90200 0 0x200>,
> > + <0 0xae90400 0 0xc00>,
> > + <0 0xae91000 0 0x400>,
> > + <0 0xae91400 0 0x400>;
> > + interrupt-parent = <>;
> > + interrupts = <12>;
> > + clocks = < DISP_CC_MDSS_AHB_CLK>,
> > +< DISP_CC_MDSS_DPTX0_AUX_CLK>,
> > +< DISP_CC_MDSS_DPTX0_LINK_CLK>,
> > +<
> > DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> > +<
> > DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> > + clock-names = "core_iface",
> > + "core_aux",
> > + "ctrl_link",
> > + "ctrl_link_iface",
> I applied this locally and noticed line has 2x 8 spaces.. Bjorn, could
> you please take care of that when applying?
>
Thanks for pointing it out. I did correct it, and I had to do the same
in sm8350.dtsi.
@Neil, please run checkpatch --strict, it will highlight these errors.
Thanks,
Bjorn
Re: [PATCH v6 5/5] arm64: dts: qcom: sm8450: add dp controller
On 17.03.2023 16:06, Neil Armstrong wrote:
> Add the Display Port controller subnode to the MDSS node.
>
> Signed-off-by: Neil Armstrong
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 79
>
> 1 file changed, 79 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 97ce5fe0e9b0..da6d1881ef60 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -2751,6 +2751,13 @@ dpu_intf2_out: endpoint {
> };
> };
>
> + port@2 {
> + reg = <2>;
> + dpu_intf0_out: endpoint {
> + remote-endpoint =
> <_dp0_in>;
> + };
> + };
> +
> };
>
> mdp_opp_table: opp-table {
> @@ -2783,6 +2790,78 @@ opp-5 {
> };
> };
>
> + mdss_dp0: displayport-controller@ae9 {
> + compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
> + reg = <0 0xae9 0 0x200>,
> + <0 0xae90200 0 0x200>,
> + <0 0xae90400 0 0xc00>,
> + <0 0xae91000 0 0x400>,
> + <0 0xae91400 0 0x400>;
> + interrupt-parent = <>;
> + interrupts = <12>;
> + clocks = < DISP_CC_MDSS_AHB_CLK>,
> + < DISP_CC_MDSS_DPTX0_AUX_CLK>,
> + < DISP_CC_MDSS_DPTX0_LINK_CLK>,
> + <
> DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> + <
> DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + clock-names = "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
I applied this locally and noticed line has 2x 8 spaces.. Bjorn, could
you please take care of that when applying?
Konrad
> + "stream_pixel";
> +
> + assigned-clocks = <
> DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> + <
> DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <_1_qmpphy
> QMP_USB43DP_DP_LINK_CLK>,
> + <_1_qmpphy
> QMP_USB43DP_DP_VCO_DIV_CLK>;
> +
> + phys = <_1_qmpphy QMP_USB43DP_DP_PHY>;
> + phy-names = "dp";
> +
> + #sound-dai-cells = <0>;
> +
> + operating-points-v2 = <_opp_table>;
> + power-domains = < SM8450_MMCX>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss_dp0_in: endpoint {
> + remote-endpoint =
> <_intf0_out>;
> + };
> + };
> + };
> +
> + dp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-16000 {
> + opp-hz = /bits/ 64 <16000>;
> + required-opps =
> <_opp_low_svs>;
> + };
> +
> + opp-27000 {
> + opp-hz = /bits/ 64 <27000>;
> + required-opps =
> <_opp_svs>;
> + };
> +
> + opp-54000 {
> + opp-hz = /bits/ 64 <54000>;
> + required-opps =
> <_opp_svs_l1>;
> + };
> +
> + opp-81000 {
> + opp-hz = /bits/ 64 <81000>;
> +
Re: [PATCH v6 5/5] arm64: dts: qcom: sm8450: add dp controller
On 17.03.2023 16:06, Neil Armstrong wrote:
> Add the Display Port controller subnode to the MDSS node.
>
> Signed-off-by: Neil Armstrong
> ---
Reviewed-by: Konrad Dybcio
Konrad
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 79
>
> 1 file changed, 79 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 97ce5fe0e9b0..da6d1881ef60 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -2751,6 +2751,13 @@ dpu_intf2_out: endpoint {
> };
> };
>
> + port@2 {
> + reg = <2>;
> + dpu_intf0_out: endpoint {
> + remote-endpoint =
> <_dp0_in>;
> + };
> + };
> +
> };
>
> mdp_opp_table: opp-table {
> @@ -2783,6 +2790,78 @@ opp-5 {
> };
> };
>
> + mdss_dp0: displayport-controller@ae9 {
> + compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
> + reg = <0 0xae9 0 0x200>,
> + <0 0xae90200 0 0x200>,
> + <0 0xae90400 0 0xc00>,
> + <0 0xae91000 0 0x400>,
> + <0 0xae91400 0 0x400>;
> + interrupt-parent = <>;
> + interrupts = <12>;
> + clocks = < DISP_CC_MDSS_AHB_CLK>,
> + < DISP_CC_MDSS_DPTX0_AUX_CLK>,
> + < DISP_CC_MDSS_DPTX0_LINK_CLK>,
> + <
> DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> + <
> DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + clock-names = "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
> + "stream_pixel";
> +
> + assigned-clocks = <
> DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> + <
> DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <_1_qmpphy
> QMP_USB43DP_DP_LINK_CLK>,
> + <_1_qmpphy
> QMP_USB43DP_DP_VCO_DIV_CLK>;
> +
> + phys = <_1_qmpphy QMP_USB43DP_DP_PHY>;
> + phy-names = "dp";
> +
> + #sound-dai-cells = <0>;
> +
> + operating-points-v2 = <_opp_table>;
> + power-domains = < SM8450_MMCX>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss_dp0_in: endpoint {
> + remote-endpoint =
> <_intf0_out>;
> + };
> + };
> + };
> +
> + dp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-16000 {
> + opp-hz = /bits/ 64 <16000>;
> + required-opps =
> <_opp_low_svs>;
> + };
> +
> + opp-27000 {
> + opp-hz = /bits/ 64 <27000>;
> + required-opps =
> <_opp_svs>;
> + };
> +
> + opp-54000 {
> + opp-hz = /bits/ 64 <54000>;
> + required-opps =
> <_opp_svs_l1>;
> + };
> +
> + opp-81000 {
> + opp-hz = /bits/ 64 <81000>;
> + required-opps =
> <_opp_nom>;
> +
[PATCH v6 5/5] arm64: dts: qcom: sm8450: add dp controller
Add the Display Port controller subnode to the MDSS node.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 79
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi
b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 97ce5fe0e9b0..da6d1881ef60 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -2751,6 +2751,13 @@ dpu_intf2_out: endpoint {
};
};
+ port@2 {
+ reg = <2>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint =
<_dp0_in>;
+ };
+ };
+
};
mdp_opp_table: opp-table {
@@ -2783,6 +2790,78 @@ opp-5 {
};
};
+ mdss_dp0: displayport-controller@ae9 {
+ compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
+ reg = <0 0xae9 0 0x200>,
+ <0 0xae90200 0 0x200>,
+ <0 0xae90400 0 0xc00>,
+ <0 0xae91000 0 0x400>,
+ <0 0xae91400 0 0x400>;
+ interrupt-parent = <>;
+ interrupts = <12>;
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_DPTX0_AUX_CLK>,
+< DISP_CC_MDSS_DPTX0_LINK_CLK>,
+<
DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+<
DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <
DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <
DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <_1_qmpphy
QMP_USB43DP_DP_LINK_CLK>,
+<_1_qmpphy
QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ phys = <_1_qmpphy QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ operating-points-v2 = <_opp_table>;
+ power-domains = < SM8450_MMCX>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dp0_in: endpoint {
+ remote-endpoint =
<_intf0_out>;
+ };
+ };
+ };
+
+ dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-16000 {
+ opp-hz = /bits/ 64 <16000>;
+ required-opps =
<_opp_low_svs>;
+ };
+
+ opp-27000 {
+ opp-hz = /bits/ 64 <27000>;
+ required-opps =
<_opp_svs>;
+ };
+
+ opp-54000 {
+ opp-hz = /bits/ 64 <54000>;
+ required-opps =
<_opp_svs_l1>;
+ };
+
+ opp-81000 {
+ opp-hz = /bits/ 64 <81000>;
+ required-opps =
<_opp_nom>;
+ };
+ };
+ };
+
mdss_dsi0: dsi@ae94000 {
compatible =
