RE: [EXT] Re: [PATCH v6 7/8] phy: freescale: Add DisplayPort PHY driver for i.MX8MQ
Hi Vinod, Thanks for your comments, > -Original Message- > From: Vinod Koul > Sent: 2023年6月21日 19:24 > To: Sandor Yu > Cc: andrzej.ha...@intel.com; neil.armstr...@linaro.org; > robert.f...@linaro.org; laurent.pinch...@ideasonboard.com; > jo...@kwiboo.se; jernej.skra...@gmail.com; airl...@gmail.com; > dan...@ffwll.ch; robh...@kernel.org; krzysztof.kozlowski...@linaro.org; > shawn...@kernel.org; s.ha...@pengutronix.de; feste...@gmail.com; > dri-devel@lists.freedesktop.org; devicet...@vger.kernel.org; > linux-arm-ker...@lists.infradead.org; linux-ker...@vger.kernel.org; > linux-...@lists.infradead.org; ker...@pengutronix.de; dl-linux-imx > ; Oliver Brown > Subject: [EXT] Re: [PATCH v6 7/8] phy: freescale: Add DisplayPort PHY driver > for i.MX8MQ > > Caution: This is an external email. Please take care when clicking links or > opening attachments. When in doubt, report the message using the 'Report > this email' button > > > On 15-06-23, 09:38, Sandor Yu wrote: > > Add Cadence HDP-TX DisplayPort PHY driver for i.MX8MQ > > > > Cadence HDP-TX PHY could be put in either DP mode or HDMI mode base > on > > the configuration chosen. > > DisplayPort PHY mode is configurated in the driver. > > > > Signed-off-by: Sandor Yu > > --- > > drivers/phy/freescale/Kconfig | 9 + > > drivers/phy/freescale/Makefile| 1 + > > drivers/phy/freescale/phy-fsl-imx8mq-dp.c | 697 > > ++ > > 3 files changed, 707 insertions(+) > > create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-dp.c > > > > diff --git a/drivers/phy/freescale/Kconfig > > b/drivers/phy/freescale/Kconfig index 853958fb2c06..a99ee370eda6 > > 100644 > > --- a/drivers/phy/freescale/Kconfig > > +++ b/drivers/phy/freescale/Kconfig > > @@ -35,6 +35,15 @@ config PHY_FSL_IMX8M_PCIE > > Enable this to add support for the PCIE PHY as found on > > i.MX8M family of SOCs. > > > > +config PHY_CADENCE_DP_PHY > > + tristate "Cadence HDPTX DP PHY support" > > + depends on OF && HAS_IOMEM > > + depends on COMMON_CLK > > + select GENERIC_PHY > > + help > > + Enable this to support the Cadence HDPTX DP PHY driver > > + on NXP's i.MX8MQ SOC. > > + > > endif > > > > config PHY_FSL_LYNX_28G > > diff --git a/drivers/phy/freescale/Makefile > > b/drivers/phy/freescale/Makefile index cedb328bc4d2..c3bdf3fa2e72 > > 100644 > > --- a/drivers/phy/freescale/Makefile > > +++ b/drivers/phy/freescale/Makefile > > @@ -4,3 +4,4 @@ obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += > phy-fsl-imx8qm-lvds-phy.o > > obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY)+= phy-fsl-imx8-mipi-dphy.o > > obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o > > obj-$(CONFIG_PHY_FSL_LYNX_28G) += > phy-fsl-lynx-28g.o > > +obj-$(CONFIG_PHY_CADENCE_DP_PHY) += phy-fsl-imx8mq-dp.o > > diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-dp.c > > b/drivers/phy/freescale/phy-fsl-imx8mq-dp.c > > new file mode 100644 > > index ..2bd6772a5d3b > > --- /dev/null > > +++ b/drivers/phy/freescale/phy-fsl-imx8mq-dp.c > > @@ -0,0 +1,697 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > +/* > > + * Cadence HDP-TX Display Port Interface (DP) PHY driver > > + * > > + * Copyright (C) 2022 NXP Semiconductor, Inc. > > + */ > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include > > + > > +#define ADDR_PHY_AFE 0x8 > > Is this always fixed for every phy generation? Yes, the offset is fixed for every cdns hdmi/dp external phy. > > + > > +/* PHY registers */ > > +#define CMN_SSM_BIAS_TMR0x0022 > > +#define CMN_PLLSM0_PLLEN_TMR0x0029 > > +#define CMN_PLLSM0_PLLPRE_TMR 0x002A > > +#define CMN_PLLSM0_PLLVREF_TMR 0x002B > > +#define CMN_PLLSM0_PLLLOCK_TMR 0x002C > > +#define CMN_PLLSM0_USER_DEF_CTRL0x002F > > +#define CMN_PSM_CLK_CTRL0x0061 > > +#define CMN_PLL0_VCOCAL_START 0x0081 > > +#define CMN_PLL0_VCOCAL_INIT_TMR0x0084 > > +#define CMN_PLL0_VCOCAL_ITER_TMR0x0085 > > +#define CMN_PLL0_INTDIV 0x0094 > > +#define CMN_PLL0_FRACDIV0x0095 > > +#define CMN_PLL0_HIGH_THR 0x0096 > > +#define CMN_PLL0_DSM_DIAG 0x0097 > > +#define CMN_PLL0_SS_CTRL2
Re: [PATCH v6 7/8] phy: freescale: Add DisplayPort PHY driver for i.MX8MQ
On 15-06-23, 09:38, Sandor Yu wrote: > Add Cadence HDP-TX DisplayPort PHY driver for i.MX8MQ > > Cadence HDP-TX PHY could be put in either DP mode or > HDMI mode base on the configuration chosen. > DisplayPort PHY mode is configurated in the driver. > > Signed-off-by: Sandor Yu > --- > drivers/phy/freescale/Kconfig | 9 + > drivers/phy/freescale/Makefile| 1 + > drivers/phy/freescale/phy-fsl-imx8mq-dp.c | 697 ++ > 3 files changed, 707 insertions(+) > create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-dp.c > > diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig > index 853958fb2c06..a99ee370eda6 100644 > --- a/drivers/phy/freescale/Kconfig > +++ b/drivers/phy/freescale/Kconfig > @@ -35,6 +35,15 @@ config PHY_FSL_IMX8M_PCIE > Enable this to add support for the PCIE PHY as found on > i.MX8M family of SOCs. > > +config PHY_CADENCE_DP_PHY > + tristate "Cadence HDPTX DP PHY support" > + depends on OF && HAS_IOMEM > + depends on COMMON_CLK > + select GENERIC_PHY > + help > + Enable this to support the Cadence HDPTX DP PHY driver > + on NXP's i.MX8MQ SOC. > + > endif > > config PHY_FSL_LYNX_28G > diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile > index cedb328bc4d2..c3bdf3fa2e72 100644 > --- a/drivers/phy/freescale/Makefile > +++ b/drivers/phy/freescale/Makefile > @@ -4,3 +4,4 @@ obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += > phy-fsl-imx8qm-lvds-phy.o > obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY)+= phy-fsl-imx8-mipi-dphy.o > obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o > obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o > +obj-$(CONFIG_PHY_CADENCE_DP_PHY) += phy-fsl-imx8mq-dp.o > diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-dp.c > b/drivers/phy/freescale/phy-fsl-imx8mq-dp.c > new file mode 100644 > index ..2bd6772a5d3b > --- /dev/null > +++ b/drivers/phy/freescale/phy-fsl-imx8mq-dp.c > @@ -0,0 +1,697 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Cadence HDP-TX Display Port Interface (DP) PHY driver > + * > + * Copyright (C) 2022 NXP Semiconductor, Inc. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#define ADDR_PHY_AFE 0x8 Is this always fixed for every phy generation? > + > +/* PHY registers */ > +#define CMN_SSM_BIAS_TMR0x0022 > +#define CMN_PLLSM0_PLLEN_TMR0x0029 > +#define CMN_PLLSM0_PLLPRE_TMR 0x002A > +#define CMN_PLLSM0_PLLVREF_TMR 0x002B > +#define CMN_PLLSM0_PLLLOCK_TMR 0x002C > +#define CMN_PLLSM0_USER_DEF_CTRL0x002F > +#define CMN_PSM_CLK_CTRL0x0061 > +#define CMN_PLL0_VCOCAL_START 0x0081 > +#define CMN_PLL0_VCOCAL_INIT_TMR0x0084 > +#define CMN_PLL0_VCOCAL_ITER_TMR0x0085 > +#define CMN_PLL0_INTDIV 0x0094 > +#define CMN_PLL0_FRACDIV0x0095 > +#define CMN_PLL0_HIGH_THR 0x0096 > +#define CMN_PLL0_DSM_DIAG 0x0097 > +#define CMN_PLL0_SS_CTRL2 0x0099 > +#define CMN_ICAL_INIT_TMR 0x00C4 > +#define CMN_ICAL_ITER_TMR 0x00C5 > +#define CMN_RXCAL_INIT_TMR 0x00D4 > +#define CMN_RXCAL_ITER_TMR 0x00D5 > +#define CMN_TXPUCAL_INIT_TMR0x00E4 > +#define CMN_TXPUCAL_ITER_TMR0x00E5 > +#define CMN_TXPDCAL_INIT_TMR0x00F4 > +#define CMN_TXPDCAL_ITER_TMR0x00F5 > +#define CMN_ICAL_ADJ_INIT_TMR 0x0102 > +#define CMN_ICAL_ADJ_ITER_TMR 0x0103 > +#define CMN_RX_ADJ_INIT_TMR 0x0106 > +#define CMN_RX_ADJ_ITER_TMR 0x0107 > +#define CMN_TXPU_ADJ_INIT_TMR 0x010A > +#define CMN_TXPU_ADJ_ITER_TMR 0x010B > +#define CMN_TXPD_ADJ_INIT_TMR 0x010E > +#define CMN_TXPD_ADJ_ITER_TMR 0x010F > +#define CMN_DIAG_PLL0_FBH_OVRD 0x01C0 > +#define CMN_DIAG_PLL0_FBL_OVRD 0x01C1 > +#define CMN_DIAG_PLL0_OVRD 0x01C2 > +#define CMN_DIAG_PLL0_TEST_MODE 0x01C4 > +#define CMN_DIAG_PLL0_V2I_TUNE 0x01C5 > +#define CMN_DIAG_PLL0_CP_TUNE 0x01C6 > +#define CMN_DIAG_PLL0_LF_PROG 0x01C7 > +#define CMN_DIAG_PLL0_PTATIS_TUNE1 0x01C8 > +#define CMN_DIAG_PLL0_PTATIS_TUNE2 0x01C9 > +#define CMN_DIAG_HSCLK_SEL 0x01E0 > +#define CMN_DIAG_PER_CAL_ADJ0x01EC > +#define CMN_DIAG_CAL_CTRL 0x01ED > +#define CMN_DIAG_ACYA 0x01FF > +#define XCVR_PSM_RCTRL 0x4001 > +#define XCVR_PSM_CAL_TMR0x4002 > +#define XCVR_PSM_A0IN_TMR 0x4003 > +#define TX_TXCC_CAL_SCLR_MULT_0 0x4047 > +#define TX_TXCC_CPOST_MULT_00_0 0x404C > +#define XCVR_DIAG_PLLDRC_CTRL 0x40E0 > +#define XCVR_DIAG_PLLDRC_CTRL 0x40E0 > +#define XCVR_D
[PATCH v6 7/8] phy: freescale: Add DisplayPort PHY driver for i.MX8MQ
Add Cadence HDP-TX DisplayPort PHY driver for i.MX8MQ Cadence HDP-TX PHY could be put in either DP mode or HDMI mode base on the configuration chosen. DisplayPort PHY mode is configurated in the driver. Signed-off-by: Sandor Yu --- drivers/phy/freescale/Kconfig | 9 + drivers/phy/freescale/Makefile| 1 + drivers/phy/freescale/phy-fsl-imx8mq-dp.c | 697 ++ 3 files changed, 707 insertions(+) create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-dp.c diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig index 853958fb2c06..a99ee370eda6 100644 --- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig @@ -35,6 +35,15 @@ config PHY_FSL_IMX8M_PCIE Enable this to add support for the PCIE PHY as found on i.MX8M family of SOCs. +config PHY_CADENCE_DP_PHY + tristate "Cadence HDPTX DP PHY support" + depends on OF && HAS_IOMEM + depends on COMMON_CLK + select GENERIC_PHY + help + Enable this to support the Cadence HDPTX DP PHY driver + on NXP's i.MX8MQ SOC. + endif config PHY_FSL_LYNX_28G diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile index cedb328bc4d2..c3bdf3fa2e72 100644 --- a/drivers/phy/freescale/Makefile +++ b/drivers/phy/freescale/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PHY_MIXEL_LVDS_PHY)+= phy-fsl-imx8qm-lvds-phy.o obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o obj-$(CONFIG_PHY_FSL_LYNX_28G) += phy-fsl-lynx-28g.o +obj-$(CONFIG_PHY_CADENCE_DP_PHY) += phy-fsl-imx8mq-dp.o diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-dp.c b/drivers/phy/freescale/phy-fsl-imx8mq-dp.c new file mode 100644 index ..2bd6772a5d3b --- /dev/null +++ b/drivers/phy/freescale/phy-fsl-imx8mq-dp.c @@ -0,0 +1,697 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cadence HDP-TX Display Port Interface (DP) PHY driver + * + * Copyright (C) 2022 NXP Semiconductor, Inc. + */ +#include +#include +#include +#include +#include +#include +#include + +#include + +#define ADDR_PHY_AFE 0x8 + +/* PHY registers */ +#define CMN_SSM_BIAS_TMR0x0022 +#define CMN_PLLSM0_PLLEN_TMR0x0029 +#define CMN_PLLSM0_PLLPRE_TMR 0x002A +#define CMN_PLLSM0_PLLVREF_TMR 0x002B +#define CMN_PLLSM0_PLLLOCK_TMR 0x002C +#define CMN_PLLSM0_USER_DEF_CTRL0x002F +#define CMN_PSM_CLK_CTRL0x0061 +#define CMN_PLL0_VCOCAL_START 0x0081 +#define CMN_PLL0_VCOCAL_INIT_TMR0x0084 +#define CMN_PLL0_VCOCAL_ITER_TMR0x0085 +#define CMN_PLL0_INTDIV 0x0094 +#define CMN_PLL0_FRACDIV0x0095 +#define CMN_PLL0_HIGH_THR 0x0096 +#define CMN_PLL0_DSM_DIAG 0x0097 +#define CMN_PLL0_SS_CTRL2 0x0099 +#define CMN_ICAL_INIT_TMR 0x00C4 +#define CMN_ICAL_ITER_TMR 0x00C5 +#define CMN_RXCAL_INIT_TMR 0x00D4 +#define CMN_RXCAL_ITER_TMR 0x00D5 +#define CMN_TXPUCAL_INIT_TMR0x00E4 +#define CMN_TXPUCAL_ITER_TMR0x00E5 +#define CMN_TXPDCAL_INIT_TMR0x00F4 +#define CMN_TXPDCAL_ITER_TMR0x00F5 +#define CMN_ICAL_ADJ_INIT_TMR 0x0102 +#define CMN_ICAL_ADJ_ITER_TMR 0x0103 +#define CMN_RX_ADJ_INIT_TMR 0x0106 +#define CMN_RX_ADJ_ITER_TMR 0x0107 +#define CMN_TXPU_ADJ_INIT_TMR 0x010A +#define CMN_TXPU_ADJ_ITER_TMR 0x010B +#define CMN_TXPD_ADJ_INIT_TMR 0x010E +#define CMN_TXPD_ADJ_ITER_TMR 0x010F +#define CMN_DIAG_PLL0_FBH_OVRD 0x01C0 +#define CMN_DIAG_PLL0_FBL_OVRD 0x01C1 +#define CMN_DIAG_PLL0_OVRD 0x01C2 +#define CMN_DIAG_PLL0_TEST_MODE 0x01C4 +#define CMN_DIAG_PLL0_V2I_TUNE 0x01C5 +#define CMN_DIAG_PLL0_CP_TUNE 0x01C6 +#define CMN_DIAG_PLL0_LF_PROG 0x01C7 +#define CMN_DIAG_PLL0_PTATIS_TUNE1 0x01C8 +#define CMN_DIAG_PLL0_PTATIS_TUNE2 0x01C9 +#define CMN_DIAG_HSCLK_SEL 0x01E0 +#define CMN_DIAG_PER_CAL_ADJ0x01EC +#define CMN_DIAG_CAL_CTRL 0x01ED +#define CMN_DIAG_ACYA 0x01FF +#define XCVR_PSM_RCTRL 0x4001 +#define XCVR_PSM_CAL_TMR0x4002 +#define XCVR_PSM_A0IN_TMR 0x4003 +#define TX_TXCC_CAL_SCLR_MULT_0 0x4047 +#define TX_TXCC_CPOST_MULT_00_0 0x404C +#define XCVR_DIAG_PLLDRC_CTRL 0x40E0 +#define XCVR_DIAG_PLLDRC_CTRL 0x40E0 +#define XCVR_DIAG_HSCLK_SEL 0x40E1 +#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR 0x40F2 +#define TX_PSC_A0 0x4100 +#define TX_PSC_A1 0x4101 +#define TX_PSC_A2 0x4102 +#define TX_PSC_A3 0x4103 +#define TX_RCVDET_EN_TMR
