Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
This patch is dependent on the patch ("drm/msm/disp/dpu1: set mdp clk
to the maximum frequency in opp table during probe") [1].
[1]
https://lore.kernel.org/r/1647269217-14064-2-git-send-email-quic_vpoli...@quicinc.com/
Signed-off-by: Vinod Polimera <quic_vpoli...@quicinc.com>
Reviewed-by: Stephen Boyd <swb...@chromium.org>
Reviewed-by: Douglas Anderson <diand...@chromium.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 41f4e46..c0771d2 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4240,9 +4240,6 @@
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "core";
- assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
- assigned-clock-rates = <300000000>;
-
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
@@ -4273,10 +4270,8 @@
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "gcc-bus", "iface", "bus",
"core", "vsync";
- assigned-clocks = <&dispcc
DISP_CC_MDSS_MDP_CLK>,
- <&dispcc
DISP_CC_MDSS_VSYNC_CLK>;
- assigned-clock-rates = <300000000>,
- <19200000>;
+ assigned-clocks = <&dispcc
DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SDM845_CX>;
--
2.7.4
