Re: [PATCH v8 5/5] dt-bindings: display: imx: add bindings for DCSS
On Wed, Jul 29, 2020 at 03:27:30PM +0200, Guido Günther wrote:
> Hi,
> On Fri, Jul 24, 2020 at 12:07:34PM +0300, Laurentiu Palcu wrote:
> > From: Laurentiu Palcu
> >
> > Add bindings for iMX8MQ Display Controller Subsystem.
> >
> > Signed-off-by: Laurentiu Palcu
> > Reviewed-by: Rob Herring
> > ---
> > .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 104 ++
> > 1 file changed, 104 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> > b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> > new file mode 100644
> > index ..68e4635e4874
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> > @@ -0,0 +1,104 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +# Copyright 2019 NXP
> > +%YAML 1.2
> > +---
> > +$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#;
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#;
> > +
> > +title: iMX8MQ Display Controller Subsystem (DCSS)
> > +
> > +maintainers:
> > + - Laurentiu Palcu
> > +
> > +description:
> > +
> > + The DCSS (display controller sub system) is used to source up to three
> > + display buffers, compose them, and drive a display using HDMI 2.0a(with
> > HDCP
> > + 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays.
> > HDR10
> > + image processing capabilities are included to provide a solution capable
> > of
> > + driving next generation high dynamic range displays.
> > +
> > +properties:
> > + compatible:
> > +const: nxp,imx8mq-dcss
> > +
> > + reg:
> > +items:
> > + - description: DCSS base address and size, up to IRQ steer start
> > + - description: DCSS BLKCTL base address and size
> > +
> > + interrupts:
> > +items:
> > + - description: Context loader completion and error interrupt
> > + - description: DTG interrupt used to signal context loader trigger
> > time
> > + - description: DTG interrupt for Vblank
> > +
> > + interrupt-names:
> > +items:
> > + - const: ctxld
> > + - const: ctxld_kick
> > + - const: vblank
> > +
> > + clocks:
> > +items:
> > + - description: Display APB clock for all peripheral PIO access
> > interfaces
> > + - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
> > + - description: RTRAM clock
> > + - description: Pixel clock, can be driven either by HDMI phy clock
> > or MIPI
> > + - description: DTRC clock, needed by video decompressor
> > +
> > + clock-names:
> > +items:
> > + - const: apb
> > + - const: axi
> > + - const: rtrm
> > + - const: pix
> > + - const: dtrc
> > +
> > + assigned-clocks:
> > +items:
> > + - description: Phandle and clock specifier of
> > IMX8MQ_CLK_DISP_AXI_ROOT
> > + - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
> > + - description: Phandle and clock specifier of either
> > IMX8MQ_VIDEO2_PLL1_REF_SEL or
> > + IMX8MQ_VIDEO_PLL1_REF_SEL
> > +
> > + assigned-clock-parents:
> > +items:
> > + - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
> > + - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
> > + - description: Phandle and clock specifier of IMX8MQ_CLK_27M
> > +
> > + assigned-clock-rates:
> > +items:
> > + - description: Must be 800 MHz
> > + - description: Must be 400 MHz
> > +
> > + port:
> > +type: object
> > +description:
> > + A port node pointing to the input port of a HDMI/DP or MIPI display
> > bridge.
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
>
> it would be nice to
>
> #include
>
> here...
>
> > +dcss: display-controller@32e0 {
> > +compatible = "nxp,imx8mq-dcss";
> > +reg = <0x32e0 0x2d000>, <0x32e2f000 0x1000>;
> > +interrupts = <6>, <8>, <9>;
> > +interrupt-names = "ctxld", "ctxld_kick", "vblank";
> > +interrupt-parent = <>;
> > +clocks = < 248>, < 247>, < 249>,
> > + < 254>,< 122>;
> > +clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
> > +assigned-clocks = < 107>, < 109>, < 266>;
> > +assigned-clock-parents = < 78>, < 78>, < 3>;
>
> so that clock names like IMX8MQ_CLK_DISP_AXI could be used to make this
> even more useful.
That's a good idea. I'll add it in.
Thanks,
laurentiu
>
> Cheers,
> -- Guido
>
> > +assigned-clock-rates = <8>,
> > + <4>;
> > +port {
> > +dcss_out: endpoint {
> > +remote-endpoint = <_in>;
> > +};
> > +};
> > +};
> > +
> > --
> > 2.23.0
> >
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Re: [PATCH v8 5/5] dt-bindings: display: imx: add bindings for DCSS
Hi,
On Fri, Jul 24, 2020 at 12:07:34PM +0300, Laurentiu Palcu wrote:
> From: Laurentiu Palcu
>
> Add bindings for iMX8MQ Display Controller Subsystem.
>
> Signed-off-by: Laurentiu Palcu
> Reviewed-by: Rob Herring
> ---
> .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 104 ++
> 1 file changed, 104 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> new file mode 100644
> index ..68e4635e4874
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> @@ -0,0 +1,104 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2019 NXP
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#;
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#;
> +
> +title: iMX8MQ Display Controller Subsystem (DCSS)
> +
> +maintainers:
> + - Laurentiu Palcu
> +
> +description:
> +
> + The DCSS (display controller sub system) is used to source up to three
> + display buffers, compose them, and drive a display using HDMI 2.0a(with
> HDCP
> + 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays.
> HDR10
> + image processing capabilities are included to provide a solution capable of
> + driving next generation high dynamic range displays.
> +
> +properties:
> + compatible:
> +const: nxp,imx8mq-dcss
> +
> + reg:
> +items:
> + - description: DCSS base address and size, up to IRQ steer start
> + - description: DCSS BLKCTL base address and size
> +
> + interrupts:
> +items:
> + - description: Context loader completion and error interrupt
> + - description: DTG interrupt used to signal context loader trigger time
> + - description: DTG interrupt for Vblank
> +
> + interrupt-names:
> +items:
> + - const: ctxld
> + - const: ctxld_kick
> + - const: vblank
> +
> + clocks:
> +items:
> + - description: Display APB clock for all peripheral PIO access
> interfaces
> + - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
> + - description: RTRAM clock
> + - description: Pixel clock, can be driven either by HDMI phy clock or
> MIPI
> + - description: DTRC clock, needed by video decompressor
> +
> + clock-names:
> +items:
> + - const: apb
> + - const: axi
> + - const: rtrm
> + - const: pix
> + - const: dtrc
> +
> + assigned-clocks:
> +items:
> + - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
> + - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
> + - description: Phandle and clock specifier of either
> IMX8MQ_VIDEO2_PLL1_REF_SEL or
> + IMX8MQ_VIDEO_PLL1_REF_SEL
> +
> + assigned-clock-parents:
> +items:
> + - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
> + - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
> + - description: Phandle and clock specifier of IMX8MQ_CLK_27M
> +
> + assigned-clock-rates:
> +items:
> + - description: Must be 800 MHz
> + - description: Must be 400 MHz
> +
> + port:
> +type: object
> +description:
> + A port node pointing to the input port of a HDMI/DP or MIPI display
> bridge.
> +
> +additionalProperties: false
> +
> +examples:
> + - |
it would be nice to
#include
here...
> +dcss: display-controller@32e0 {
> +compatible = "nxp,imx8mq-dcss";
> +reg = <0x32e0 0x2d000>, <0x32e2f000 0x1000>;
> +interrupts = <6>, <8>, <9>;
> +interrupt-names = "ctxld", "ctxld_kick", "vblank";
> +interrupt-parent = <>;
> +clocks = < 248>, < 247>, < 249>,
> + < 254>,< 122>;
> +clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
> +assigned-clocks = < 107>, < 109>, < 266>;
> +assigned-clock-parents = < 78>, < 78>, < 3>;
so that clock names like IMX8MQ_CLK_DISP_AXI could be used to make this
even more useful.
Cheers,
-- Guido
> +assigned-clock-rates = <8>,
> + <4>;
> +port {
> +dcss_out: endpoint {
> +remote-endpoint = <_in>;
> +};
> +};
> +};
> +
> --
> 2.23.0
>
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[PATCH v8 5/5] dt-bindings: display: imx: add bindings for DCSS
From: Laurentiu Palcu
Add bindings for iMX8MQ Display Controller Subsystem.
Signed-off-by: Laurentiu Palcu
Reviewed-by: Rob Herring
---
.../bindings/display/imx/nxp,imx8mq-dcss.yaml | 104 ++
1 file changed, 104 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
new file mode 100644
index ..68e4635e4874
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 NXP
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: iMX8MQ Display Controller Subsystem (DCSS)
+
+maintainers:
+ - Laurentiu Palcu
+
+description:
+
+ The DCSS (display controller sub system) is used to source up to three
+ display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
+ 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
+ image processing capabilities are included to provide a solution capable of
+ driving next generation high dynamic range displays.
+
+properties:
+ compatible:
+const: nxp,imx8mq-dcss
+
+ reg:
+items:
+ - description: DCSS base address and size, up to IRQ steer start
+ - description: DCSS BLKCTL base address and size
+
+ interrupts:
+items:
+ - description: Context loader completion and error interrupt
+ - description: DTG interrupt used to signal context loader trigger time
+ - description: DTG interrupt for Vblank
+
+ interrupt-names:
+items:
+ - const: ctxld
+ - const: ctxld_kick
+ - const: vblank
+
+ clocks:
+items:
+ - description: Display APB clock for all peripheral PIO access interfaces
+ - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
+ - description: RTRAM clock
+ - description: Pixel clock, can be driven either by HDMI phy clock or
MIPI
+ - description: DTRC clock, needed by video decompressor
+
+ clock-names:
+items:
+ - const: apb
+ - const: axi
+ - const: rtrm
+ - const: pix
+ - const: dtrc
+
+ assigned-clocks:
+items:
+ - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
+ - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
+ - description: Phandle and clock specifier of either
IMX8MQ_VIDEO2_PLL1_REF_SEL or
+ IMX8MQ_VIDEO_PLL1_REF_SEL
+
+ assigned-clock-parents:
+items:
+ - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
+ - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
+ - description: Phandle and clock specifier of IMX8MQ_CLK_27M
+
+ assigned-clock-rates:
+items:
+ - description: Must be 800 MHz
+ - description: Must be 400 MHz
+
+ port:
+type: object
+description:
+ A port node pointing to the input port of a HDMI/DP or MIPI display
bridge.
+
+additionalProperties: false
+
+examples:
+ - |
+dcss: display-controller@32e0 {
+compatible = "nxp,imx8mq-dcss";
+reg = <0x32e0 0x2d000>, <0x32e2f000 0x1000>;
+interrupts = <6>, <8>, <9>;
+interrupt-names = "ctxld", "ctxld_kick", "vblank";
+interrupt-parent = <>;
+clocks = < 248>, < 247>, < 249>,
+ < 254>,< 122>;
+clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+assigned-clocks = < 107>, < 109>, < 266>;
+assigned-clock-parents = < 78>, < 78>, < 3>;
+assigned-clock-rates = <8>,
+ <4>;
+port {
+dcss_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
--
2.23.0
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