RE: [RFC 21/28] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

2022-01-22 Thread Biju Das 
Hi Rob,

Thanks for the review.

> Subject: Re: [RFC 21/28] dt-bindings: display: bridge: Document RZ/G2L
> MIPI DSI TX bindings
> 
> On Wed, Jan 12, 2022 at 05:46:05PM +, Biju Das wrote:
> > The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's.
> > It can operate in DSI mode, with up to four data lanes.
> >
> > Signed-off-by: Biju Das 
> > ---
> >  .../bindings/display/bridge/renesas,dsi.yaml  | 143
> > ++
> >  1 file changed, 143 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> > b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> > new file mode 100644
> > index ..8e56a9c53cc5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yam
> > +++ l
> > @@ -0,0 +1,143 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fschemas%2Fdisplay%2Fbridge%2Frenesas%2Cdsi.yaml%23d
> > +ata=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7C0494a54e80ad4334fbd208d9
> > +dd43393b%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637784103062464
> > +167%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBT
> > +iI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=krF2TinxFIRvSQWNMrJpAjUpkk
> > +cghJsFzWIOmh2Nwno%3Dreserved=0
> > +$schema:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23data=04%7C01%7Cbiju.das.
> > +jz%40bp.renesas.com%7C0494a54e80ad4334fbd208d9dd43393b%7C53d82571da19
> > +47e49cb4625a166a4a2a%7C0%7C0%7C637784103062464167%7CUnknown%7CTWFpbGZ
> > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > +3D%7C3000sdata=XrwV3g0Jw0%2Bsi0J5PygxWTw614a0%2FtQGDF2HeMdBVsA%3
> > +Dreserved=0
> > +
> > +title: Renesas R-Car MIPI DSI Encoder
> > +
> > +maintainers:
> > +  - Biju Das 
> > +
> > +description: |
> > +  This binding describes the MIPI DSI encoder embedded in the Renesas
> > +  RZ/G2L family of SoC's. The encoder can operate in DSI mode with up
> > +  to four data lanes.
> 
> Need a ref to dsi-controller.yaml.

Agreed. Will add this.

> 
> > +
> > +properties:
> > +  compatible:
> > +enum:
> > +  - renesas,r9a07g044-mipi-dsi# for RZ/G2L
> > +
> > +  reg:
> > +items:
> > +  - description: Link register
> > +  - description: D-PHY register
> 
> D-PHY isn't a separate block?

MIPI-DSI Tx module composed of MIPI DSI-2 Host Controller (LINK), and MIPI 
D-PHY Tx (DPHY).

Basically both D-PHY and Link are integrated inside MIPI-DSI Tx module.

Regards,
Biju

> 
> > +
> > +  clocks:
> > +items:
> > +  - description: DSI D-PHY PLL multiplied clock
> > +  - description: DSI D-PHY system clock
> > +  - description: DSI AXI bus clock
> > +  - description: DSI Register access clock
> > +  - description: DSI Video clock
> > +  - description: DSI D_PHY Escape mode Receive clock
> > +
> > +  clock-names:
> > +items:
> > +  - const: pllclk
> > +  - const: sysclk
> > +  - const: aclk
> > +  - const: pclk
> > +  - const: vclk
> > +  - const: lpclk
> > +
> > +  power-domains:
> > +maxItems: 1
> > +
> > +  resets:
> > +items:
> > +  - description: MIPI_DSI_CMN_RSTB
> > +  - description: MIPI_DSI_ARESET_N
> > +  - description: MIPI_DSI_PRESET_N
> > +
> > +  reset-names:
> > +items:
> > +  - const: rst
> > +  - const: arst
> > +  - const: prst
> > +
> > +  ports:
> > +$ref: /schemas/graph.yaml#/properties/ports
> > +
> > +properties:
> > +  port@0:
> > +$ref: /schemas/graph.yaml#/properties/port
> > +description: Parallel input port
> > +
> > +  port@1:
> > +$ref: /schemas/graph.yaml#/$defs/port-base
> > +unevaluatedProperties: false
> > +description: DSI output port
> > +
> > +properties:
> > +  endpoint:
> > +$ref: /schemas/media/video-interfaces.yaml#
> > +unevaluatedProperties: false
> > +
> > +properties:
> > +  data-lanes:
> > +

Re: [RFC 21/28] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

2022-01-21 Thread Rob Herring 
On Wed, Jan 12, 2022 at 05:46:05PM +, Biju Das wrote:
> The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It
> can operate in DSI mode, with up to four data lanes.
> 
> Signed-off-by: Biju Das 
> ---
>  .../bindings/display/bridge/renesas,dsi.yaml  | 143 ++
>  1 file changed, 143 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> 
> diff --git 
> a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml 
> b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> new file mode 100644
> index ..8e56a9c53cc5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> @@ -0,0 +1,143 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas R-Car MIPI DSI Encoder
> +
> +maintainers:
> +  - Biju Das 
> +
> +description: |
> +  This binding describes the MIPI DSI encoder embedded in the Renesas
> +  RZ/G2L family of SoC's. The encoder can operate in DSI mode with up
> +  to four data lanes.

Need a ref to dsi-controller.yaml.

> +
> +properties:
> +  compatible:
> +enum:
> +  - renesas,r9a07g044-mipi-dsi# for RZ/G2L
> +
> +  reg:
> +items:
> +  - description: Link register
> +  - description: D-PHY register

D-PHY isn't a separate block?

> +
> +  clocks:
> +items:
> +  - description: DSI D-PHY PLL multiplied clock
> +  - description: DSI D-PHY system clock
> +  - description: DSI AXI bus clock
> +  - description: DSI Register access clock
> +  - description: DSI Video clock
> +  - description: DSI D_PHY Escape mode Receive clock
> +
> +  clock-names:
> +items:
> +  - const: pllclk
> +  - const: sysclk
> +  - const: aclk
> +  - const: pclk
> +  - const: vclk
> +  - const: lpclk
> +
> +  power-domains:
> +maxItems: 1
> +
> +  resets:
> +items:
> +  - description: MIPI_DSI_CMN_RSTB
> +  - description: MIPI_DSI_ARESET_N
> +  - description: MIPI_DSI_PRESET_N
> +
> +  reset-names:
> +items:
> +  - const: rst
> +  - const: arst
> +  - const: prst
> +
> +  ports:
> +$ref: /schemas/graph.yaml#/properties/ports
> +
> +properties:
> +  port@0:
> +$ref: /schemas/graph.yaml#/properties/port
> +description: Parallel input port
> +
> +  port@1:
> +$ref: /schemas/graph.yaml#/$defs/port-base
> +unevaluatedProperties: false
> +description: DSI output port
> +
> +properties:
> +  endpoint:
> +$ref: /schemas/media/video-interfaces.yaml#
> +unevaluatedProperties: false
> +
> +properties:
> +  data-lanes:
> +minItems: 1
> +maxItems: 4
> +
> +required:
> +  - data-lanes
> +
> +required:
> +  - port@0
> +  - port@1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - power-domains
> +  - resets
> +  - reset-names
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +#include 
> +
> +dsi0: dsi@1086 {
> +compatible = "renesas,r9a07g044-mipi-dsi";
> +reg = <0x1086 0x1>,
> +  <0x1085 0x1>;
> +power-domains = <>;
> +clocks = < CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
> + < CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
> + < CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
> + < CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
> + < CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
> + < CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
> +clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
> +resets = < R9A07G044_MIPI_DSI_CMN_RSTB>,
> + < R9A07G044_MIPI_DSI_ARESET_N>,
> + < R9A07G044_MIPI_DSI_PRESET_N>;
> +reset-names = "rst", "arst", "prst";
> +
> +ports {
> +#address-cells = <1>;
> +#size-cells = <0>;
> +
> +port@0 {
> +reg = <0>;
> +dsi0_in: endpoint {
> +remote-endpoint = <_out_dsi0>;
> +};
> +};
> +
> +port@1 {
> +reg = <1>;
> +dsi0_out: endpoint {
> +data-lanes = <1 2 3 4>;
> +remote-endpoint = <_in>;
> +};
> +};
> +};
> +};
> +...
> -- 
> 2.17.1
> 
>

[RFC 21/28] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

2022-01-12 Thread Biju Das 
The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It
can operate in DSI mode, with up to four data lanes.

Signed-off-by: Biju Das 
---
 .../bindings/display/bridge/renesas,dsi.yaml  | 143 ++
 1 file changed, 143 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml

diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml 
b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
new file mode 100644
index ..8e56a9c53cc5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car MIPI DSI Encoder
+
+maintainers:
+  - Biju Das 
+
+description: |
+  This binding describes the MIPI DSI encoder embedded in the Renesas
+  RZ/G2L family of SoC's. The encoder can operate in DSI mode with up
+  to four data lanes.
+
+properties:
+  compatible:
+enum:
+  - renesas,r9a07g044-mipi-dsi# for RZ/G2L
+
+  reg:
+items:
+  - description: Link register
+  - description: D-PHY register
+
+  clocks:
+items:
+  - description: DSI D-PHY PLL multiplied clock
+  - description: DSI D-PHY system clock
+  - description: DSI AXI bus clock
+  - description: DSI Register access clock
+  - description: DSI Video clock
+  - description: DSI D_PHY Escape mode Receive clock
+
+  clock-names:
+items:
+  - const: pllclk
+  - const: sysclk
+  - const: aclk
+  - const: pclk
+  - const: vclk
+  - const: lpclk
+
+  power-domains:
+maxItems: 1
+
+  resets:
+items:
+  - description: MIPI_DSI_CMN_RSTB
+  - description: MIPI_DSI_ARESET_N
+  - description: MIPI_DSI_PRESET_N
+
+  reset-names:
+items:
+  - const: rst
+  - const: arst
+  - const: prst
+
+  ports:
+$ref: /schemas/graph.yaml#/properties/ports
+
+properties:
+  port@0:
+$ref: /schemas/graph.yaml#/properties/port
+description: Parallel input port
+
+  port@1:
+$ref: /schemas/graph.yaml#/$defs/port-base
+unevaluatedProperties: false
+description: DSI output port
+
+properties:
+  endpoint:
+$ref: /schemas/media/video-interfaces.yaml#
+unevaluatedProperties: false
+
+properties:
+  data-lanes:
+minItems: 1
+maxItems: 4
+
+required:
+  - data-lanes
+
+required:
+  - port@0
+  - port@1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - power-domains
+  - resets
+  - reset-names
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+
+dsi0: dsi@1086 {
+compatible = "renesas,r9a07g044-mipi-dsi";
+reg = <0x1086 0x1>,
+  <0x1085 0x1>;
+power-domains = <>;
+clocks = < CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
+ < CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
+ < CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
+ < CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
+ < CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
+ < CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
+clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
+resets = < R9A07G044_MIPI_DSI_CMN_RSTB>,
+ < R9A07G044_MIPI_DSI_ARESET_N>,
+ < R9A07G044_MIPI_DSI_PRESET_N>;
+reset-names = "rst", "arst", "prst";
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dsi0_in: endpoint {
+remote-endpoint = <_out_dsi0>;
+};
+};
+
+port@1 {
+reg = <1>;
+dsi0_out: endpoint {
+data-lanes = <1 2 3 4>;
+remote-endpoint = <_in>;
+};
+};
+};
+};
+...
-- 
2.17.1