Re: [RFC PATCH v2 0/5] drm/amd/display: improve DTN color state log
On 09/25, Harry Wentland wrote: > > > On 2023-09-13 12:43, Melissa Wen wrote: > > Hi, > > > > This is an update of previous RFC [0] improving the data collection of > > Gamma Correction and Blend Gamma color blocks. > > > > As I mentioned in the last version, I'm updating the color state part of > > DTN log to match DCN3.0 HW better. Currently, the DTN log considers the > > DCN10 color pipeline, which is useless for DCN3.0 because of all the > > differences in color caps between DCN versions. In addition to new color > > blocks and caps, some semantic differences made the DCN10 output not fit > > DCN30. > > > > In this RFC, the first patch adds new color state elements to DPP and > > implements the reading of registers according to HW blocks. Similarly to > > MPC, the second patch also creates a DCN3-specific function to read the > > MPC state and add the MPC color state logging to it. With DPP and MPC > > color-register reading, I detach DCN10 color state logging from the HW > > log and create a `.log_color_state` hook for logging color state > > according to HW color blocks with DCN30 as the first use case. Finally, > > the last patch adds DPP and MPC color caps output to facilitate > > understanding of the color state log. > > > > This version works well with the driver-specific color properties[1] and > > steamdeck/gamescope[2] together, where we can see color state changing > > from default values. > > > > Here is a before vs. after example: > > > > Without this series: > > === > > DPP:IGAM format IGAM modeDGAM modeRGAM mode GAMUT mode C11 > > C12 C13 C14 C21 C22 C23 C24 C31 C32 C33 C34 > > [ 0]:0h BypassFixed Bypass Bypass0 > > h h h h h h > > [ 3]:0h BypassFixed Bypass Bypass0 > > h h h h h h > > > > MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE > > [ 0]: 0h 0h 3h 3 20 0 0 > > [ 3]: 0h 3h fh 2 20 0 0 > > > > With this series (Steamdeck/Gamescope): > > == > > > > DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode 3DLUT mode 3DLUT bit > > depth 3DLUT size RGAM mode GAMUT mode C11 C12 C13 C14 C21 C22 C23 > > C24 C31 C32 C33 C34 > > [ 0]:1 sRGBBypassRAM A RAM B > > 12-bit17x17x17 RAM A 0 h h h > > h h h > > [ 1]:1 sRGBBypassRAM B RAM A > > 12-bit17x17x17 RAM A 0 h h h > > h h h > > [ 2]:1 sRGBBypassRAM B RAM A > > 12-bit17x17x17 RAM A 0 h h h > > h h h > > [ 3]:1 sRGBBypassRAM A RAM B > > 12-bit17x17x17 RAM A 0 h h h > > h h h > > > > DPP Color Caps: input_lut_shared:0 icsc:1 dgam_ram:0 dgam_rom: > > srgb:1,bt2020:1,gamma2_2:1,pq:1,hlg:1 post_csc:1 gamcor:1 > > dgam_rom_for_yuv:0 3d_lut:1 blnd_lut:1 oscs:0 > > > > MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE > > SHAPER mode 3DLUT_mode 3DLUT bit-depth 3DLUT size OGAM mode OGAM LUT > > GAMUT mode C11 C12 C33 C34 > > [ 0]: 0h 0h 2h 3 01 0 0 > > Bypass Bypass 12-bit17x17x17RAM A > > 0 h h > > [ 1]: 0h 1h fh 2 20 0 0 > > Bypass Bypass 12-bit17x17x17 Bypass A > > 0 h h > > [ 2]: 0h 2h 3h 3 01 0 0 > > Bypass Bypass 12-bit17x17x17 Bypass A > > 0 h h > > [ 3]: 0h 3h 1h 3 20 0 0 > > Bypass Bypass 12-bit17x17x17 Bypass A > > 0 h h > > > > MPC Color Caps: gamut_remap:1, 3dlut:2, ogam_ram:1, ocsc:1 > > > > With this series (Steamdeck/KDE): > > > > > > DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode 3DLUT mode 3DLUT bit > > depth 3DLUT size RGAM mode GAMUT mode C11 C12 C13 C14 C21 C22 C23 > > C24 C31 C32 C33 C34 > > [ 0]:0 sRGBBypass Bypass Bypass > > 12-bit 9x9x9 Bypass 0 h h h > > h h h > > [ 3]:0 sRGBBypass Bypass
Re: [RFC PATCH v2 0/5] drm/amd/display: improve DTN color state log
On 2023-09-13 12:43, Melissa Wen wrote: > Hi, > > This is an update of previous RFC [0] improving the data collection of > Gamma Correction and Blend Gamma color blocks. > > As I mentioned in the last version, I'm updating the color state part of > DTN log to match DCN3.0 HW better. Currently, the DTN log considers the > DCN10 color pipeline, which is useless for DCN3.0 because of all the > differences in color caps between DCN versions. In addition to new color > blocks and caps, some semantic differences made the DCN10 output not fit > DCN30. > > In this RFC, the first patch adds new color state elements to DPP and > implements the reading of registers according to HW blocks. Similarly to > MPC, the second patch also creates a DCN3-specific function to read the > MPC state and add the MPC color state logging to it. With DPP and MPC > color-register reading, I detach DCN10 color state logging from the HW > log and create a `.log_color_state` hook for logging color state > according to HW color blocks with DCN30 as the first use case. Finally, > the last patch adds DPP and MPC color caps output to facilitate > understanding of the color state log. > > This version works well with the driver-specific color properties[1] and > steamdeck/gamescope[2] together, where we can see color state changing > from default values. > > Here is a before vs. after example: > > Without this series: > === > DPP:IGAM format IGAM modeDGAM modeRGAM mode GAMUT mode C11 C12 > C13 C14 C21 C22 C23 C24 C31 C32 C33 C34 > [ 0]:0h BypassFixed Bypass Bypass0 > h h h h h h > [ 3]:0h BypassFixed Bypass Bypass0 > h h h h h h > > MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE > [ 0]: 0h 0h 3h 3 20 0 0 > [ 3]: 0h 3h fh 2 20 0 0 > > With this series (Steamdeck/Gamescope): > == > > DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode 3DLUT mode 3DLUT bit > depth 3DLUT size RGAM mode GAMUT mode C11 C12 C13 C14 C21 C22 C23 > C24 C31 C32 C33 C34 > [ 0]:1 sRGBBypassRAM A RAM B > 12-bit17x17x17 RAM A 0 h h h > h h h > [ 1]:1 sRGBBypassRAM B RAM A > 12-bit17x17x17 RAM A 0 h h h > h h h > [ 2]:1 sRGBBypassRAM B RAM A > 12-bit17x17x17 RAM A 0 h h h > h h h > [ 3]:1 sRGBBypassRAM A RAM B > 12-bit17x17x17 RAM A 0 h h h > h h h > > DPP Color Caps: input_lut_shared:0 icsc:1 dgam_ram:0 dgam_rom: > srgb:1,bt2020:1,gamma2_2:1,pq:1,hlg:1 post_csc:1 gamcor:1 > dgam_rom_for_yuv:0 3d_lut:1 blnd_lut:1 oscs:0 > > MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE > SHAPER mode 3DLUT_mode 3DLUT bit-depth 3DLUT size OGAM mode OGAM LUT > GAMUT mode C11 C12 C33 C34 > [ 0]: 0h 0h 2h 3 01 0 0 > Bypass Bypass 12-bit17x17x17RAM A > 0 h h > [ 1]: 0h 1h fh 2 20 0 0 > Bypass Bypass 12-bit17x17x17 Bypass A > 0 h h > [ 2]: 0h 2h 3h 3 01 0 0 > Bypass Bypass 12-bit17x17x17 Bypass A > 0 h h > [ 3]: 0h 3h 1h 3 20 0 0 > Bypass Bypass 12-bit17x17x17 Bypass A > 0 h h > > MPC Color Caps: gamut_remap:1, 3dlut:2, ogam_ram:1, ocsc:1 > > With this series (Steamdeck/KDE): > > > DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode 3DLUT mode 3DLUT bit > depth 3DLUT size RGAM mode GAMUT mode C11 C12 C13 C14 C21 C22 C23 > C24 C31 C32 C33 C34 > [ 0]:0 sRGBBypass Bypass Bypass > 12-bit 9x9x9 Bypass 0 h h h > h h h > [ 3]:0 sRGBBypass Bypass Bypass > 12-bit 9x9x9 Bypass 0 h h h > h h h > > DPP Color Caps: input_lut_shared:0 icsc:1 dgam_ram:0 dgam_rom: >
Re: [RFC PATCH v2 0/5] drm/amd/display: improve DTN color state log
On 9/13/23 10:43, Melissa Wen wrote: Hi, This is an update of previous RFC [0] improving the data collection of Gamma Correction and Blend Gamma color blocks. As I mentioned in the last version, I'm updating the color state part of DTN log to match DCN3.0 HW better. Currently, the DTN log considers the DCN10 color pipeline, which is useless for DCN3.0 because of all the differences in color caps between DCN versions. In addition to new color blocks and caps, some semantic differences made the DCN10 output not fit DCN30. In this RFC, the first patch adds new color state elements to DPP and implements the reading of registers according to HW blocks. Similarly to MPC, the second patch also creates a DCN3-specific function to read the MPC state and add the MPC color state logging to it. With DPP and MPC color-register reading, I detach DCN10 color state logging from the HW log and create a `.log_color_state` hook for logging color state according to HW color blocks with DCN30 as the first use case. Finally, the last patch adds DPP and MPC color caps output to facilitate understanding of the color state log. This version works well with the driver-specific color properties[1] and steamdeck/gamescope[2] together, where we can see color state changing from default values. Here is a before vs. after example: Without this series: === DPP:IGAM format IGAM modeDGAM modeRGAM mode GAMUT mode C11 C12 C13 C14 C21 C22 C23 C24 C31 C32 C33 C34 [ 0]:0h BypassFixed Bypass Bypass0h h h h h h [ 3]:0h BypassFixed Bypass Bypass0h h h h h h MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE [ 0]: 0h 0h 3h 3 20 0 0 [ 3]: 0h 3h fh 2 20 0 0 With this series (Steamdeck/Gamescope): == DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode 3DLUT mode 3DLUT bit depth 3DLUT size RGAM mode GAMUT mode C11 C12 C13 C14 C21 C22 C23 C24 C31 C32 C33 C34 [ 0]:1 sRGBBypassRAM A RAM B 12-bit17x17x17 RAM A 0 h h h h h h [ 1]:1 sRGBBypassRAM B RAM A 12-bit17x17x17 RAM A 0 h h h h h h [ 2]:1 sRGBBypassRAM B RAM A 12-bit17x17x17 RAM A 0 h h h h h h [ 3]:1 sRGBBypassRAM A RAM B 12-bit17x17x17 RAM A 0 h h h h h h DPP Color Caps: input_lut_shared:0 icsc:1 dgam_ram:0 dgam_rom: srgb:1,bt2020:1,gamma2_2:1,pq:1,hlg:1 post_csc:1 gamcor:1 dgam_rom_for_yuv:0 3d_lut:1 blnd_lut:1 oscs:0 MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE SHAPER mode 3DLUT_mode 3DLUT bit-depth 3DLUT size OGAM mode OGAM LUT GAMUT mode C11 C12 C33 C34 [ 0]: 0h 0h 2h 3 01 0 0 Bypass Bypass 12-bit17x17x17RAM A 0 h h [ 1]: 0h 1h fh 2 20 0 0 Bypass Bypass 12-bit17x17x17 Bypass A 0 h h [ 2]: 0h 2h 3h 3 01 0 0 Bypass Bypass 12-bit17x17x17 Bypass A 0 h h [ 3]: 0h 3h 1h 3 20 0 0 Bypass Bypass 12-bit17x17x17 Bypass A 0 h h MPC Color Caps: gamut_remap:1, 3dlut:2, ogam_ram:1, ocsc:1 I liked this new visualization. At some point, we need to document this information as a kernel-doc to make it easy to understand this DTN LOG. With this series (Steamdeck/KDE): DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode 3DLUT mode 3DLUT bit depth 3DLUT size RGAM mode GAMUT mode C11 C12 C13 C14 C21 C22 C23 C24 C31 C32 C33 C34 [ 0]:0 sRGBBypass Bypass Bypass 12-bit 9x9x9 Bypass 0 h h h h h h [ 3]:0 sRGBBypass Bypass Bypass 12-bit 9x9x9 Bypass 0 h h h h h h DPP Color Caps: input_lut_shared:0 icsc:1 dgam_ram:0 dgam_rom: srgb:1,bt2020:1,gamma2_2:1,pq:1,hlg:1 post_csc:1 gamcor:1
[RFC PATCH v2 0/5] drm/amd/display: improve DTN color state log
Hi, This is an update of previous RFC [0] improving the data collection of Gamma Correction and Blend Gamma color blocks. As I mentioned in the last version, I'm updating the color state part of DTN log to match DCN3.0 HW better. Currently, the DTN log considers the DCN10 color pipeline, which is useless for DCN3.0 because of all the differences in color caps between DCN versions. In addition to new color blocks and caps, some semantic differences made the DCN10 output not fit DCN30. In this RFC, the first patch adds new color state elements to DPP and implements the reading of registers according to HW blocks. Similarly to MPC, the second patch also creates a DCN3-specific function to read the MPC state and add the MPC color state logging to it. With DPP and MPC color-register reading, I detach DCN10 color state logging from the HW log and create a `.log_color_state` hook for logging color state according to HW color blocks with DCN30 as the first use case. Finally, the last patch adds DPP and MPC color caps output to facilitate understanding of the color state log. This version works well with the driver-specific color properties[1] and steamdeck/gamescope[2] together, where we can see color state changing from default values. Here is a before vs. after example: Without this series: === DPP:IGAM format IGAM modeDGAM modeRGAM mode GAMUT mode C11 C12 C13 C14 C21 C22 C23 C24 C31 C32 C33 C34 [ 0]:0h BypassFixed Bypass Bypass0h h h h h h [ 3]:0h BypassFixed Bypass Bypass0h h h h h h MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE [ 0]: 0h 0h 3h 3 20 0 0 [ 3]: 0h 3h fh 2 20 0 0 With this series (Steamdeck/Gamescope): == DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode 3DLUT mode 3DLUT bit depth 3DLUT size RGAM mode GAMUT mode C11 C12 C13 C14 C21 C22 C23 C24 C31 C32 C33 C34 [ 0]:1 sRGBBypassRAM A RAM B 12-bit17x17x17 RAM A 0 h h h h h h [ 1]:1 sRGBBypassRAM B RAM A 12-bit17x17x17 RAM A 0 h h h h h h [ 2]:1 sRGBBypassRAM B RAM A 12-bit17x17x17 RAM A 0 h h h h h h [ 3]:1 sRGBBypassRAM A RAM B 12-bit17x17x17 RAM A 0 h h h h h h DPP Color Caps: input_lut_shared:0 icsc:1 dgam_ram:0 dgam_rom: srgb:1,bt2020:1,gamma2_2:1,pq:1,hlg:1 post_csc:1 gamcor:1 dgam_rom_for_yuv:0 3d_lut:1 blnd_lut:1 oscs:0 MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE SHAPER mode 3DLUT_mode 3DLUT bit-depth 3DLUT size OGAM mode OGAM LUT GAMUT mode C11 C12 C33 C34 [ 0]: 0h 0h 2h 3 01 0 0 Bypass Bypass 12-bit17x17x17RAM A 0 h h [ 1]: 0h 1h fh 2 20 0 0 Bypass Bypass 12-bit17x17x17 Bypass A 0 h h [ 2]: 0h 2h 3h 3 01 0 0 Bypass Bypass 12-bit17x17x17 Bypass A 0 h h [ 3]: 0h 3h 1h 3 20 0 0 Bypass Bypass 12-bit17x17x17 Bypass A 0 h h MPC Color Caps: gamut_remap:1, 3dlut:2, ogam_ram:1, ocsc:1 With this series (Steamdeck/KDE): DPP: DGAM ROM DGAM ROM type DGAM LUT SHAPER mode 3DLUT mode 3DLUT bit depth 3DLUT size RGAM mode GAMUT mode C11 C12 C13 C14 C21 C22 C23 C24 C31 C32 C33 C34 [ 0]:0 sRGBBypass Bypass Bypass 12-bit 9x9x9 Bypass 0 h h h h h h [ 3]:0 sRGBBypass Bypass Bypass 12-bit 9x9x9 Bypass 0 h h h h h h DPP Color Caps: input_lut_shared:0 icsc:1 dgam_ram:0 dgam_rom: srgb:1,bt2020:1,gamma2_2:1,pq:1,hlg:1 post_csc:1 gamcor:1 dgam_rom_for_yuv:0 3d_lut:1 blnd_lut:1 oscs:0 MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE SHAPER mode 3DLUT_mode 3DLUT bit-depth 3DLUT size OGAM mode OGAM LUT
