Convert the atmel,hlcdc binding to DT schema format.
Align clocks and clock-names properties to clearly indicate that the LCD
controller expects lvds_pll_clk when interfaced with the lvds display. This
alignment with the specific hardware requirements ensures accurate device tree
configuration for systems utilizing the HLCDC IP.
Signed-off-by: Dharma Balasubiramani
---
Changelog
v4 -> v5
- Revert v3 dropping lvds_pll_clk instead add it as an optional clock.
- Update minItems to 3.
- Update commit message accordingly.
v3 -> v4
- Drop lvds_pll_clk, It can be enabled in lvds driver itself.
- Update commit message.
Note: Since there is no complexities now, I believe that specifying
maxitems in the clocks property should be sufficient.
v2 -> v3
- Rename hlcdc-display-controller and hlcdc-pwm to generic names.
- Modify the description by removing the unwanted comments and '|'.
- Modify clock-names simpler.
v1 -> v2
- Remove the explicit copyrights.
- Modify title (not include words like binding/driver).
- Modify description actually describing the hardware and not the driver.
- Add details of lvds_pll addition in commit message.
- Ref endpoint and not endpoint-base.
- Fix coding style.
...
.../devicetree/bindings/mfd/atmel,hlcdc.yaml | 99 +++
.../devicetree/bindings/mfd/atmel-hlcdc.txt | 56 ---
2 files changed, 99 insertions(+), 56 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/atmel,hlcdc.yaml
delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
diff --git a/Documentation/devicetree/bindings/mfd/atmel,hlcdc.yaml
b/Documentation/devicetree/bindings/mfd/atmel,hlcdc.yaml
new file mode 100644
index ..4aa36903e755
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/atmel,hlcdc.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/atmel,hlcdc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel's HLCD Controller
+
+maintainers:
+ - Nicolas Ferre
+ - Alexandre Belloni
+ - Claudiu Beznea
+
+description:
+ The Atmel HLCDC (HLCD Controller) IP available on Atmel SoCs exposes two
+ subdevices, a PWM chip and a Display Controller.
+
+properties:
+ compatible:
+enum:
+ - atmel,at91sam9n12-hlcdc
+ - atmel,at91sam9x5-hlcdc
+ - atmel,sama5d2-hlcdc
+ - atmel,sama5d3-hlcdc
+ - atmel,sama5d4-hlcdc
+ - microchip,sam9x60-hlcdc
+ - microchip,sam9x75-xlcdc
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+minItems: 3
+
+ clock-names:
+items:
+ - const: periph_clk
+ - const: sys_clk
+ - const: slow_clk
+ - const: lvds_pll_clk
+minItems: 3
+
+ display-controller:
+$ref: /schemas/display/atmel/atmel,hlcdc-display-controller.yaml
+
+ pwm:
+$ref: /schemas/pwm/atmel,hlcdc-pwm.yaml
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+lcd_controller: lcd-controller@f003 {
+ compatible = "atmel,sama5d3-hlcdc";
+ reg = <0xf003 0x2000>;
+ clocks = <_clk>, <>, <>;
+ clock-names = "periph_clk", "sys_clk", "slow_clk";
+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ display-controller {
+compatible = "atmel,hlcdc-display-controller";
+pinctrl-names = "default";
+pinctrl-0 = <_lcd_base _lcd_rgb888>;
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ hlcdc_panel_output: endpoint@0 {
+reg = <0>;
+remote-endpoint = <_input>;
+ };
+};
+ };
+
+ pwm {
+compatible = "atmel,hlcdc-pwm";
+pinctrl-names = "default";
+pinctrl-0 = <_lcd_pwm>;
+#pwm-cells = <3>;
+ };
+};
diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
deleted file mode 100644
index 7de696eefaed..
--- a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver
-
-Required properties:
- - compatible: value should be one of the following:
- "atmel,at91sam9n12-hlcdc"
- "atmel,at91sam9x5-hlcdc"
- "atmel,sama5d2-hlcdc"
- "atmel,sama5d3-hlcdc"
- "atmel,sama5d4-hlcdc"
- "microchip,sam9x60-hlcdc"
- "microchip,sam9x75-xlcdc"
- - reg: base address and size of the HLCDC device registers.
- - clock-names: the name of the 3 clocks requested by the HLCDC device.
- Should contain "periph_clk", "sys_clk" and "slow_clk".
- - clocks: should contain the 3 clocks requested by the HLCDC device.
- - interrupts: should contain the description of the HLCDC interrupt line
-
-The HLCDC IP exposes two
