Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data

2020-07-28 Thread Enric Balletbo Serra 
Hi Yongqiang,

Missatge de Yongqiang Niu  del dia ds., 25
de jul. 2020 a les 5:29:
>
> On Thu, 2020-07-23 at 11:32 +0200, Enric Balletbo Serra wrote:
> > Hi Yongqiang Niu,
> >
> > Thank you for your patch.
> >
> > Missatge de Yongqiang Niu  del dia dj., 23
> > de jul. 2020 a les 4:05:
> > >
> > > add mmsys private data
> > >
> >
> > I think this change requires a better explanation of what you are
> > doing. Although I'm really uncomfortable with this change, why you
> > need to create a new mt2701-mmsys file?
>
> reason:
> 1.there will more and more Mediatek Soc upstream, and the display path
> connection function mtk_mmsys_ddp_mout_en, mtk_mmsys_ddp_sel_in and
> mtk_mmsys_ddp_sout_sel will complicated more and more,
> 2. many of the connection are only used in some SoC, and useless for
> other SoC and not readable,
> 3. if we add a new SoC connection, we need check is this affect other
> Soc,
> >
> > > Feature: drm/mediatek
> >
> > Remove this.
> next version will remove this
> >
> > > Signed-off-by: Yongqiang Niu 
> > > ---
> > >  drivers/soc/mediatek/Makefile |   1 +
> > >  drivers/soc/mediatek/mmsys/Makefile   |   2 +
> > >  drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 
> > > +++
> > >  drivers/soc/mediatek/mtk-mmsys.c  | 271 
> > > +-
> > >  include/linux/soc/mediatek/mtk-mmsys.h|  15 ++
> > >  5 files changed, 314 insertions(+), 225 deletions(-)
> > >  create mode 100644 drivers/soc/mediatek/mmsys/Makefile
> > >  create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> > >
> > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> > > index 2afa7b9..b37ac2c 100644
> > > --- a/drivers/soc/mediatek/Makefile
> > > +++ b/drivers/soc/mediatek/Makefile
> > > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
> > >  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> > >  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> > >  obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> > > +obj-$(CONFIG_MTK_MMSYS) += mmsys/
> > > diff --git a/drivers/soc/mediatek/mmsys/Makefile 
> > > b/drivers/soc/mediatek/mmsys/Makefile
> > > new file mode 100644
> > > index 000..33b0dab
> > > --- /dev/null
> > > +++ b/drivers/soc/mediatek/mmsys/Makefile
> > > @@ -0,0 +1,2 @@
> > > +# SPDX-License-Identifier: GPL-2.0-only
> > > +obj-y += mt2701-mmsys.o
> > > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c 
> > > b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> > > new file mode 100644
> > > index 000..b8e53b0
> > > --- /dev/null
> > > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> > > @@ -0,0 +1,250 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +//
> > > +// Copyright (c) 2020 MediaTek Inc.
> > > +
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +
> > > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN  0x040
> > > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN  0x044
> > > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN0x048
> > > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
> > > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN  0x050
> > > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> > > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> > > +#define DISP_REG_CONFIG_DSIE_SEL_IN0x0a4
> > > +#define DISP_REG_CONFIG_DSIO_SEL_IN0x0a8
> > > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> > > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8
> > > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
> > > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
> > > +#define DISP_REG_CONFIG_MMSYS_CG_CON0  0x100
> > > +
> > > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN   0x030
> > > +#define DISP_REG_CONFIG_OUT_SEL0x04c
> > > +#define DISP_REG_CONFIG_DSI_SEL0x050
> > > +#define DISP_REG_CONFIG_DPI_SEL0x064
> > > +
> > > +#define OVL0_MOUT_EN_COLOR00x1
> > > +#define OD_MOUT_EN_RDMA0   0x1
> > > +#define OD1_MOUT_EN_RDMA1  BIT(16)
> > > +#define UFOE_MOUT_EN_DSI0  0x1
> > > +#define COLOR0_SEL_IN_OVL0 0x1
> > > +#define OVL1_MOUT_EN_COLOR10x1
> > > +#define GAMMA_MOUT_EN_RDMA10x1
> > > +#define RDMA0_SOUT_DPI00x2
> > > +#define RDMA0_SOUT_DPI10x3
> > > +#define RDMA0_SOUT_DSI10x1
> > > +#define RDMA0_SOUT_DSI20x4
> > > +#define RDMA0_SOUT_DSI30x5
> > > +#define RDMA1_SOUT_DPI00x2
> > > +#define RDMA1_SOUT_DPI10x3
> > > +#define RDMA1_SOUT_DSI10x1
> > > +#define RDMA1_SOUT_DSI20x4
> > > +#define

Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data

2020-07-26 Thread Yongqiang Niu 
On Sat, 2020-07-25 at 10:11 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
> 
> Yongqiang Niu  於 2020年7月23日 週四 上午10:05寫道：
> >
> > add mmsys private data
> >
> > Feature: drm/mediatek
> > Signed-off-by: Yongqiang Niu 
> > ---
> >  drivers/soc/mediatek/Makefile |   1 +
> >  drivers/soc/mediatek/mmsys/Makefile   |   2 +
> >  drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++
> >  drivers/soc/mediatek/mtk-mmsys.c  | 271 
> > +-
> >  include/linux/soc/mediatek/mtk-mmsys.h|  15 ++
> >  5 files changed, 314 insertions(+), 225 deletions(-)
> >  create mode 100644 drivers/soc/mediatek/mmsys/Makefile
> >  create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> >
> > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> > index 2afa7b9..b37ac2c 100644
> > --- a/drivers/soc/mediatek/Makefile
> > +++ b/drivers/soc/mediatek/Makefile
> > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
> >  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> >  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> >  obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> > +obj-$(CONFIG_MTK_MMSYS) += mmsys/
> > diff --git a/drivers/soc/mediatek/mmsys/Makefile 
> > b/drivers/soc/mediatek/mmsys/Makefile
> > new file mode 100644
> > index 000..33b0dab
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mmsys/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +obj-y += mt2701-mmsys.o
> > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c 
> > b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> > new file mode 100644
> > index 000..b8e53b0
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> > @@ -0,0 +1,250 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +//
> > +// Copyright (c) 2020 MediaTek Inc.
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN  0x040
> > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN  0x044
> > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN0x048
> > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
> > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN  0x050
> > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> > +#define DISP_REG_CONFIG_DSIE_SEL_IN0x0a4
> > +#define DISP_REG_CONFIG_DSIO_SEL_IN0x0a8
> > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8
> > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
> > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
> > +#define DISP_REG_CONFIG_MMSYS_CG_CON0  0x100
> > +
> > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN   0x030
> > +#define DISP_REG_CONFIG_OUT_SEL0x04c
> > +#define DISP_REG_CONFIG_DSI_SEL0x050
> > +#define DISP_REG_CONFIG_DPI_SEL0x064
> > +
> > +#define OVL0_MOUT_EN_COLOR00x1
> > +#define OD_MOUT_EN_RDMA0   0x1
> > +#define OD1_MOUT_EN_RDMA1  BIT(16)
> > +#define UFOE_MOUT_EN_DSI0  0x1
> > +#define COLOR0_SEL_IN_OVL0 0x1
> > +#define OVL1_MOUT_EN_COLOR10x1
> > +#define GAMMA_MOUT_EN_RDMA10x1
> > +#define RDMA0_SOUT_DPI00x2
> > +#define RDMA0_SOUT_DPI10x3
> > +#define RDMA0_SOUT_DSI10x1
> > +#define RDMA0_SOUT_DSI20x4
> > +#define RDMA0_SOUT_DSI30x5
> > +#define RDMA1_SOUT_DPI00x2
> > +#define RDMA1_SOUT_DPI10x3
> > +#define RDMA1_SOUT_DSI10x1
> > +#define RDMA1_SOUT_DSI20x4
> > +#define RDMA1_SOUT_DSI30x5
> > +#define RDMA2_SOUT_DPI00x2
> > +#define RDMA2_SOUT_DPI10x3
> > +#define RDMA2_SOUT_DSI10x1
> > +#define RDMA2_SOUT_DSI20x4
> > +#define RDMA2_SOUT_DSI30x5
> > +#define DPI0_SEL_IN_RDMA1  0x1
> > +#define DPI0_SEL_IN_RDMA2  0x3
> > +#define DPI1_SEL_IN_RDMA1  (0x1 << 8)
> > +#define DPI1_SEL_IN_RDMA2  (0x3 << 8)
> > +#define DSI0_SEL_IN_RDMA1  0x1
> > +#define DSI0_SEL_IN_RDMA2  0x4
> > +#define DSI1_SEL_IN_RDMA1  0x1
> > +#define DSI1_SEL_IN_RDMA2  0x4
> > +#define DSI2_SEL_IN_RDMA1  (0x1 << 16)
> > +#define DSI2_SEL_IN_RDMA2  (0x4 << 16)
> > +#define DSI3_SEL_IN_RDMA1

Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data

2020-07-26 Thread Yongqiang Niu 
On Thu, 2020-07-23 at 11:32 +0200, Enric Balletbo Serra wrote:
> Hi Yongqiang Niu,
> 
> Thank you for your patch.
> 
> Missatge de Yongqiang Niu  del dia dj., 23
> de jul. 2020 a les 4:05:
> >
> > add mmsys private data
> >
> 
> I think this change requires a better explanation of what you are
> doing. Although I'm really uncomfortable with this change, why you
> need to create a new mt2701-mmsys file?

reason:
1.there will more and more Mediatek Soc upstream, and the display path
connection function mtk_mmsys_ddp_mout_en, mtk_mmsys_ddp_sel_in and
mtk_mmsys_ddp_sout_sel will complicated more and more, 
2. many of the connection are only used in some SoC, and useless for
other SoC and not readable,
3. if we add a new SoC connection, we need check is this affect other
Soc,
> 
> > Feature: drm/mediatek
> 
> Remove this.
next version will remove this
> 
> > Signed-off-by: Yongqiang Niu 
> > ---
> >  drivers/soc/mediatek/Makefile |   1 +
> >  drivers/soc/mediatek/mmsys/Makefile   |   2 +
> >  drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++
> >  drivers/soc/mediatek/mtk-mmsys.c  | 271 
> > +-
> >  include/linux/soc/mediatek/mtk-mmsys.h|  15 ++
> >  5 files changed, 314 insertions(+), 225 deletions(-)
> >  create mode 100644 drivers/soc/mediatek/mmsys/Makefile
> >  create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> >
> > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> > index 2afa7b9..b37ac2c 100644
> > --- a/drivers/soc/mediatek/Makefile
> > +++ b/drivers/soc/mediatek/Makefile
> > @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
> >  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> >  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> >  obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> > +obj-$(CONFIG_MTK_MMSYS) += mmsys/
> > diff --git a/drivers/soc/mediatek/mmsys/Makefile 
> > b/drivers/soc/mediatek/mmsys/Makefile
> > new file mode 100644
> > index 000..33b0dab
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mmsys/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +obj-y += mt2701-mmsys.o
> > diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c 
> > b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> > new file mode 100644
> > index 000..b8e53b0
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> > @@ -0,0 +1,250 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +//
> > +// Copyright (c) 2020 MediaTek Inc.
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN  0x040
> > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN  0x044
> > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN0x048
> > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
> > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN  0x050
> > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> > +#define DISP_REG_CONFIG_DSIE_SEL_IN0x0a4
> > +#define DISP_REG_CONFIG_DSIO_SEL_IN0x0a8
> > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8
> > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
> > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
> > +#define DISP_REG_CONFIG_MMSYS_CG_CON0  0x100
> > +
> > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN   0x030
> > +#define DISP_REG_CONFIG_OUT_SEL0x04c
> > +#define DISP_REG_CONFIG_DSI_SEL0x050
> > +#define DISP_REG_CONFIG_DPI_SEL0x064
> > +
> > +#define OVL0_MOUT_EN_COLOR00x1
> > +#define OD_MOUT_EN_RDMA0   0x1
> > +#define OD1_MOUT_EN_RDMA1  BIT(16)
> > +#define UFOE_MOUT_EN_DSI0  0x1
> > +#define COLOR0_SEL_IN_OVL0 0x1
> > +#define OVL1_MOUT_EN_COLOR10x1
> > +#define GAMMA_MOUT_EN_RDMA10x1
> > +#define RDMA0_SOUT_DPI00x2
> > +#define RDMA0_SOUT_DPI10x3
> > +#define RDMA0_SOUT_DSI10x1
> > +#define RDMA0_SOUT_DSI20x4
> > +#define RDMA0_SOUT_DSI30x5
> > +#define RDMA1_SOUT_DPI00x2
> > +#define RDMA1_SOUT_DPI10x3
> > +#define RDMA1_SOUT_DSI10x1
> > +#define RDMA1_SOUT_DSI20x4
> > +#define RDMA1_SOUT_DSI30x5
> > +#define RDMA2_SOUT_DPI00x2
> > +#define RDMA2_SOUT_DPI10x3
> > +#define RDMA2_SOUT_DSI10x1
> > +#define RDMA2_SOUT_DSI20x4
> >

Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data

2020-07-24 Thread Chun-Kuang Hu 
Hi, Yongqiang:

Yongqiang Niu  於 2020年7月23日 週四 上午10:05寫道：
>
> add mmsys private data
>
> Feature: drm/mediatek
> Signed-off-by: Yongqiang Niu 
> ---
>  drivers/soc/mediatek/Makefile |   1 +
>  drivers/soc/mediatek/mmsys/Makefile   |   2 +
>  drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++
>  drivers/soc/mediatek/mtk-mmsys.c  | 271 
> +-
>  include/linux/soc/mediatek/mtk-mmsys.h|  15 ++
>  5 files changed, 314 insertions(+), 225 deletions(-)
>  create mode 100644 drivers/soc/mediatek/mmsys/Makefile
>  create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
>
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index 2afa7b9..b37ac2c 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
>  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
>  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
>  obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> +obj-$(CONFIG_MTK_MMSYS) += mmsys/
> diff --git a/drivers/soc/mediatek/mmsys/Makefile 
> b/drivers/soc/mediatek/mmsys/Makefile
> new file mode 100644
> index 000..33b0dab
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-y += mt2701-mmsys.o
> diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c 
> b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> new file mode 100644
> index 000..b8e53b0
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> @@ -0,0 +1,250 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2020 MediaTek Inc.
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN  0x040
> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN  0x044
> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN0x048
> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN  0x050
> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> +#define DISP_REG_CONFIG_DSIE_SEL_IN0x0a4
> +#define DISP_REG_CONFIG_DSIO_SEL_IN0x0a8
> +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8
> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
> +#define DISP_REG_CONFIG_MMSYS_CG_CON0  0x100
> +
> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN   0x030
> +#define DISP_REG_CONFIG_OUT_SEL0x04c
> +#define DISP_REG_CONFIG_DSI_SEL0x050
> +#define DISP_REG_CONFIG_DPI_SEL0x064
> +
> +#define OVL0_MOUT_EN_COLOR00x1
> +#define OD_MOUT_EN_RDMA0   0x1
> +#define OD1_MOUT_EN_RDMA1  BIT(16)
> +#define UFOE_MOUT_EN_DSI0  0x1
> +#define COLOR0_SEL_IN_OVL0 0x1
> +#define OVL1_MOUT_EN_COLOR10x1
> +#define GAMMA_MOUT_EN_RDMA10x1
> +#define RDMA0_SOUT_DPI00x2
> +#define RDMA0_SOUT_DPI10x3
> +#define RDMA0_SOUT_DSI10x1
> +#define RDMA0_SOUT_DSI20x4
> +#define RDMA0_SOUT_DSI30x5
> +#define RDMA1_SOUT_DPI00x2
> +#define RDMA1_SOUT_DPI10x3
> +#define RDMA1_SOUT_DSI10x1
> +#define RDMA1_SOUT_DSI20x4
> +#define RDMA1_SOUT_DSI30x5
> +#define RDMA2_SOUT_DPI00x2
> +#define RDMA2_SOUT_DPI10x3
> +#define RDMA2_SOUT_DSI10x1
> +#define RDMA2_SOUT_DSI20x4
> +#define RDMA2_SOUT_DSI30x5
> +#define DPI0_SEL_IN_RDMA1  0x1
> +#define DPI0_SEL_IN_RDMA2  0x3
> +#define DPI1_SEL_IN_RDMA1  (0x1 << 8)
> +#define DPI1_SEL_IN_RDMA2  (0x3 << 8)
> +#define DSI0_SEL_IN_RDMA1  0x1
> +#define DSI0_SEL_IN_RDMA2  0x4
> +#define DSI1_SEL_IN_RDMA1  0x1
> +#define DSI1_SEL_IN_RDMA2  0x4
> +#define DSI2_SEL_IN_RDMA1  (0x1 << 16)
> +#define DSI2_SEL_IN_RDMA2  (0x4 << 16)
> +#define DSI3_SEL_IN_RDMA1  (0x1 << 16)
> +#define DSI3_SEL_IN_RDMA2  (0x4 << 16)
> +#define COLOR1_SEL_IN_OVL1 0x1
> +
> +#define OVL_MOUT_EN_RDMA   0x1
> +#define BLS_TO_DSI_RDMA1_TO_DPI1   0x8
> +#define

Re: [v7, PATCH 2/7] mtk-mmsys: add mmsys private data

2020-07-23 Thread Enric Balletbo Serra 
Hi Yongqiang Niu,

Thank you for your patch.

Missatge de Yongqiang Niu  del dia dj., 23
de jul. 2020 a les 4:05:
>
> add mmsys private data
>

I think this change requires a better explanation of what you are
doing. Although I'm really uncomfortable with this change, why you
need to create a new mt2701-mmsys file?

> Feature: drm/mediatek

Remove this.

> Signed-off-by: Yongqiang Niu 
> ---
>  drivers/soc/mediatek/Makefile |   1 +
>  drivers/soc/mediatek/mmsys/Makefile   |   2 +
>  drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++
>  drivers/soc/mediatek/mtk-mmsys.c  | 271 
> +-
>  include/linux/soc/mediatek/mtk-mmsys.h|  15 ++
>  5 files changed, 314 insertions(+), 225 deletions(-)
>  create mode 100644 drivers/soc/mediatek/mmsys/Makefile
>  create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
>
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index 2afa7b9..b37ac2c 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
>  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
>  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
>  obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> +obj-$(CONFIG_MTK_MMSYS) += mmsys/
> diff --git a/drivers/soc/mediatek/mmsys/Makefile 
> b/drivers/soc/mediatek/mmsys/Makefile
> new file mode 100644
> index 000..33b0dab
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-y += mt2701-mmsys.o
> diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c 
> b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> new file mode 100644
> index 000..b8e53b0
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
> @@ -0,0 +1,250 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2020 MediaTek Inc.
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN  0x040
> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN  0x044
> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN0x048
> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN  0x050
> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> +#define DISP_REG_CONFIG_DSIE_SEL_IN0x0a4
> +#define DISP_REG_CONFIG_DSIO_SEL_IN0x0a8
> +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8
> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
> +#define DISP_REG_CONFIG_MMSYS_CG_CON0  0x100
> +
> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN   0x030
> +#define DISP_REG_CONFIG_OUT_SEL0x04c
> +#define DISP_REG_CONFIG_DSI_SEL0x050
> +#define DISP_REG_CONFIG_DPI_SEL0x064
> +
> +#define OVL0_MOUT_EN_COLOR00x1
> +#define OD_MOUT_EN_RDMA0   0x1
> +#define OD1_MOUT_EN_RDMA1  BIT(16)
> +#define UFOE_MOUT_EN_DSI0  0x1
> +#define COLOR0_SEL_IN_OVL0 0x1
> +#define OVL1_MOUT_EN_COLOR10x1
> +#define GAMMA_MOUT_EN_RDMA10x1
> +#define RDMA0_SOUT_DPI00x2
> +#define RDMA0_SOUT_DPI10x3
> +#define RDMA0_SOUT_DSI10x1
> +#define RDMA0_SOUT_DSI20x4
> +#define RDMA0_SOUT_DSI30x5
> +#define RDMA1_SOUT_DPI00x2
> +#define RDMA1_SOUT_DPI10x3
> +#define RDMA1_SOUT_DSI10x1
> +#define RDMA1_SOUT_DSI20x4
> +#define RDMA1_SOUT_DSI30x5
> +#define RDMA2_SOUT_DPI00x2
> +#define RDMA2_SOUT_DPI10x3
> +#define RDMA2_SOUT_DSI10x1
> +#define RDMA2_SOUT_DSI20x4
> +#define RDMA2_SOUT_DSI30x5
> +#define DPI0_SEL_IN_RDMA1  0x1
> +#define DPI0_SEL_IN_RDMA2  0x3
> +#define DPI1_SEL_IN_RDMA1  (0x1 << 8)
> +#define DPI1_SEL_IN_RDMA2  (0x3 << 8)
> +#define DSI0_SEL_IN_RDMA1  0x1
> +#define DSI0_SEL_IN_RDMA2  0x4
> +#define DSI1_SEL_IN_RDMA1  0x1
> +#define DSI1_SEL_IN_RDMA2  0x4
> +#define DSI2_SEL_IN_RDMA1  (0x1 << 16)
> +#define DSI2_SEL_IN_RDMA2  (0x4 << 16)
> +#define DSI3_SEL_IN_RDMA1  (0x1 <<

[v7, PATCH 2/7] mtk-mmsys: add mmsys private data

2020-07-23 Thread Yongqiang Niu 
add mmsys private data

Feature: drm/mediatek
Signed-off-by: Yongqiang Niu 
---
 drivers/soc/mediatek/Makefile |   1 +
 drivers/soc/mediatek/mmsys/Makefile   |   2 +
 drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 250 +++
 drivers/soc/mediatek/mtk-mmsys.c  | 271 +-
 include/linux/soc/mediatek/mtk-mmsys.h|  15 ++
 5 files changed, 314 insertions(+), 225 deletions(-)
 create mode 100644 drivers/soc/mediatek/mmsys/Makefile
 create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c

diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index 2afa7b9..b37ac2c 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
 obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
 obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
 obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mmsys/
diff --git a/drivers/soc/mediatek/mmsys/Makefile 
b/drivers/soc/mediatek/mmsys/Makefile
new file mode 100644
index 000..33b0dab
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-y += mt2701-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c 
b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
new file mode 100644
index 000..b8e53b0
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN  0x040
+#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN  0x044
+#define DISP_REG_CONFIG_DISP_OD_MOUT_EN0x048
+#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
+#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN  0x050
+#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
+#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
+#define DISP_REG_CONFIG_DSIE_SEL_IN0x0a4
+#define DISP_REG_CONFIG_DSIO_SEL_IN0x0a8
+#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
+#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8
+#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
+#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
+#define DISP_REG_CONFIG_MMSYS_CG_CON0  0x100
+
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN   0x030
+#define DISP_REG_CONFIG_OUT_SEL0x04c
+#define DISP_REG_CONFIG_DSI_SEL0x050
+#define DISP_REG_CONFIG_DPI_SEL0x064
+
+#define OVL0_MOUT_EN_COLOR00x1
+#define OD_MOUT_EN_RDMA0   0x1
+#define OD1_MOUT_EN_RDMA1  BIT(16)
+#define UFOE_MOUT_EN_DSI0  0x1
+#define COLOR0_SEL_IN_OVL0 0x1
+#define OVL1_MOUT_EN_COLOR10x1
+#define GAMMA_MOUT_EN_RDMA10x1
+#define RDMA0_SOUT_DPI00x2
+#define RDMA0_SOUT_DPI10x3
+#define RDMA0_SOUT_DSI10x1
+#define RDMA0_SOUT_DSI20x4
+#define RDMA0_SOUT_DSI30x5
+#define RDMA1_SOUT_DPI00x2
+#define RDMA1_SOUT_DPI10x3
+#define RDMA1_SOUT_DSI10x1
+#define RDMA1_SOUT_DSI20x4
+#define RDMA1_SOUT_DSI30x5
+#define RDMA2_SOUT_DPI00x2
+#define RDMA2_SOUT_DPI10x3
+#define RDMA2_SOUT_DSI10x1
+#define RDMA2_SOUT_DSI20x4
+#define RDMA2_SOUT_DSI30x5
+#define DPI0_SEL_IN_RDMA1  0x1
+#define DPI0_SEL_IN_RDMA2  0x3
+#define DPI1_SEL_IN_RDMA1  (0x1 << 8)
+#define DPI1_SEL_IN_RDMA2  (0x3 << 8)
+#define DSI0_SEL_IN_RDMA1  0x1
+#define DSI0_SEL_IN_RDMA2  0x4
+#define DSI1_SEL_IN_RDMA1  0x1
+#define DSI1_SEL_IN_RDMA2  0x4
+#define DSI2_SEL_IN_RDMA1  (0x1 << 16)
+#define DSI2_SEL_IN_RDMA2  (0x4 << 16)
+#define DSI3_SEL_IN_RDMA1  (0x1 << 16)
+#define DSI3_SEL_IN_RDMA2  (0x4 << 16)
+#define COLOR1_SEL_IN_OVL1 0x1
+
+#define OVL_MOUT_EN_RDMA   0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1   0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI0x2
+#define DSI_SEL_IN_BLS 0x0
+#define DPI_SEL_IN_BLS 0x0
+#define DSI_SEL_IN_RDMA0x1
+
+static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id