subject:"Re\: \[DNM RFC PATCH\] drm\/msm\: Use lowercase hex for \!defines"

Re: [DNM RFC PATCH] drm/msm: Use lowercase hex for !defines

2022-10-12 Thread Rob Clark

On Sat, Oct 8, 2022 at 10:43 AM Konrad Dybcio
 wrote:
>
> drm/msm capitalizes hex numbers rather randomly. Try to unify it.

yeah, there were some different preferences of various patch authors
for shouty HEX vs quiet hex... tbh I prefer the latter, but not really
sure it is worth the noise in git history to change it

BR,
-R

> Generated with:
>
> grep -rEl "\s0x\w*[A-Z]+*\w*" drivers/gpu/drm/msm | \
> xargs sed -i '/define/! s/\s0x\w*[A-Z]+*\w*/\L&/g'
> ---
> I could not find any strict hex capitalization rules for Linux, so
> I'm sending this very loosely, without an S-o-b and as a DNM RFC.
> Funnily enough, this patch somehow broke get_maintainer.pl
>
>  drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 138 +++
>  drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 164 +-
>  drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 126 +++---
>  drivers/gpu/drm/msm/adreno/a5xx_gpu.h |   2 +-
>  drivers/gpu/drm/msm/adreno/a5xx_power.c   | 128 +++---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c |  26 +--
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.h |   4 +-
>  drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c   |   4 +-
>  drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h   |   2 +-
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h   |  12 +-
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 162 -
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h|   4 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c|  26 +--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c |  10 +-
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c   |   8 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c   |  16 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c   |  98 +--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c   |   2 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c |   2 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c   |   6 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c |  18 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c  |   2 +-
>  drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c  |  28 +--
>  drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c |   2 +-
>  drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c  |   4 +-
>  drivers/gpu/drm/msm/dp/dp_audio.c |   8 +-
>  drivers/gpu/drm/msm/dp/dp_aux.c   |   2 +-
>  drivers/gpu/drm/msm/dp/dp_catalog.c   |  14 +-
>  drivers/gpu/drm/msm/dp/dp_ctrl.c  |   4 +-
>  drivers/gpu/drm/msm/dp/dp_display.c   |   2 +-
>  drivers/gpu/drm/msm/dp/dp_link.c  |  10 +-
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c|   4 +-
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c |   2 +-
>  drivers/gpu/drm/msm/hdmi/hdmi.c   |   4 +-
>  drivers/gpu/drm/msm/hdmi/hdmi_hdcp.c  |  20 +--
>  drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c  |  22 +--
>  36 files changed, 543 insertions(+), 543 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c 
> b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
> index 6c9a747eb4ad..f207588218c6 100644
> --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
> @@ -236,7 +236,7 @@ static int a2xx_hw_init(struct msm_gpu *gpu)
> for (i = 1; i < len; i++)
> gpu_write(gpu, REG_A2XX_CP_PFP_UCODE_DATA, ptr[i]);
>
> -   gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x000C0804);
> +   gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x000c0804);
>
> /* clear ME_HALT to start micro engine */
> gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0);
> @@ -335,90 +335,90 @@ static irqreturn_t a2xx_irq(struct msm_gpu *gpu)
>  }
>
>  static const unsigned int a200_registers[] = {
> -   0x, 0x0002, 0x0004, 0x000B, 0x003B, 0x003D, 0x0040, 0x0044,
> -   0x0046, 0x0047, 0x01C0, 0x01C1, 0x01C3, 0x01C8, 0x01D5, 0x01D9,
> -   0x01DC, 0x01DD, 0x01EA, 0x01EA, 0x01EE, 0x01F3, 0x01F6, 0x01F7,
> -   0x01FC, 0x01FF, 0x0391, 0x0392, 0x039B, 0x039E, 0x03B2, 0x03B5,
> -   0x03B7, 0x03B7, 0x03F8, 0x03FB, 0x0440, 0x0440, 0x0443, 0x0444,
> -   0x044B, 0x044B, 0x044D, 0x044F, 0x0452, 0x0452, 0x0454, 0x045B,
> -   0x047F, 0x047F, 0x0578, 0x0587, 0x05C9, 0x05C9, 0x05D0, 0x05D0,
> -   0x0601, 0x0604, 0x0606, 0x0609, 0x060B, 0x060E, 0x0613, 0x0614,
> -   0x0A29, 0x0A2B, 0x0A2F, 0x0A31, 0x0A40, 0x0A43, 0x0A45, 0x0A45,
> -   0x0A4E, 0x0A4F, 0x0C2C, 0x0C2C, 0x0C30, 0x0C30, 0x0C38, 0x0C3C,
> -   0x0C40, 0x0C40, 0x0C44, 0x0C44, 0x0C80, 0x0C86, 0x0C88, 0x0C94,
> -   0x0C99, 0x0C9A, 0x0CA4, 0x0CA5, 0x0D00, 0x0D03, 0x0D06, 0x0D06,
> -   0x0D08, 0x0D0B, 0x0D34, 0x0D35, 0x0DAE, 0x0DC1, 0x0DC8, 0x0DD4,
> -   0x0DD8, 0x0DD9, 0x0E00, 0x0E00, 0x0E02, 0x0E04, 0x0E17, 0x0E1E,
> -   0x0EC0, 0x0EC9, 0x0ECB, 0x0ECC, 0x0ED0, 0x0ED0, 0x0ED4, 0x0ED7,
> -   0x0EE0, 0x0EE2, 0x0F01, 0x0F02, 0x0F0C, 0x0F0C, 0x0F0E, 0x0F12,
> -   0x0F26, 0x0F2A, 0x0F2C, 0x0F2C, 0x2000, 0x2002, 0x2006, 0x200F,
> -   0x2080, 0x2082, 0x2100, 0x2109, 0x210C, 0x2114, 0x2180,

Re: [DNM RFC PATCH] drm/msm: Use lowercase hex for !defines

2022-10-08 Thread Konrad Dybcio




On 8.10.2022 19:43, Konrad Dybcio wrote:
> drm/msm capitalizes hex numbers rather randomly. Try to unify it.
> 
> Generated with:
> 
> grep -rEl "\s0x\w*[A-Z]+*\w*" drivers/gpu/drm/msm | \
> xargs sed -i '/define/! s/\s0x\w*[A-Z]+*\w*/\L&/g'
> ---
> I could not find any strict hex capitalization rules for Linux, so
> I'm sending this very loosely, without an S-o-b and as a DNM RFC.
> Funnily enough, this patch somehow broke get_maintainer.pl
> 

[...]
>   return msm_gem_address_space_create(mmu,
> - "gpu", 0x1ULL,
> + "gpu", 0x1ull,
Well this is an immediate issue if this patch was even to be considered.

Konrad
>   adreno_private_address_space_size(gpu));
>  }
>  
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h 
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> index ab853f61db63..6bd24c9f15e9 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> @@ -43,7 +43,7 @@ struct a6xx_gpu {
>   */
>  #define A6XX_PROTECT_NORDWR(_reg, _len) \
>   ((1 << 31) | \
> - (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3))
> + (((_len) & 0x3fff) << 18) | ((_reg) & 0x3))
>  
>  /*
>   * Same as above, but allow reads over the range. For areas of mixed use 
> (such
> @@ -51,7 +51,7 @@ struct a6xx_gpu {
>   * single register
>   */
>  #define A6XX_PROTECT_RDONLY(_reg, _len) \
> - _len) & 0x3FFF) << 18) | ((_reg) & 0x3))
> + _len) & 0x3fff) << 18) | ((_reg) & 0x3))
>  
>  static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
>  {
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> index 55f443328d8e..a0538533bf2c 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
> @@ -344,7 +344,7 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu,
>   gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3, 0);
>  
>   gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0, 0x76543210);
> - gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1, 0xFEDCBA98);
> + gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1, 0xfedcba98);
>  
>   gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0, 0);
>   gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1, 0);
> @@ -375,7 +375,7 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu,
>   cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0,
>   0x76543210);
>   cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1,
> - 0xFEDCBA98);
> + 0xfedcba98);
>  
>   cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0, 0);
>   cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1, 0);
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h 
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
> index 2fb58b7098e4..741291ebb99f 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
> @@ -308,7 +308,7 @@ static const u32 a6xx_vbif_registers[] = {
>  };
>  
>  static const u32 a6xx_gbif_registers[] = {
> - 0x3C00, 0X3C0B, 0X3C40, 0X3C47, 0X3CC0, 0X3CD1, 0xE3A, 0xE3A,
> + 0x3c00, 0X3C0B, 0X3C40, 0X3C47, 0X3CC0, 0X3CD1, 0xe3a, 0xe3a,
>  };
>  
>  static const struct a6xx_registers a6xx_ahb_reglist[] = {
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h 
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index e7adc5c632d0..ed3ac60c832e 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -354,7 +354,7 @@ static inline void
>  OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
>  {
>   adreno_wait_ring(ring, cnt+1);
> - OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
> + OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7fff));
>  }
>  
>  /* no-op packet: */
> @@ -369,7 +369,7 @@ static inline void
>  OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
>  {
>   adreno_wait_ring(ring, cnt+1);
> - OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
> + OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xff) << 8));
>  }
>  
>  static inline u32 PM4_PARITY(u32 val)
> @@ -385,7 +385,7 @@ static inline u32 PM4_PARITY(u32 val)
>  
>  #define PKT4(_reg, _cnt) \
>   (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
> -  (((_reg) & 0x3) << 8) | (PM4_PARITY((_reg)) << 27))
> +  (((_reg) & 0x3) << 8) | (PM4_PARITY((_reg)) << 27))
>  
>  static inline void
>  OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
> @@ -399,7 +399,7 @@ OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, 
> uint16_t cnt)
>  {
>   adreno_wait_ring(ring, cnt + 1);
>   OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
> - ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) <<

Re: [DNM RFC PATCH] drm/msm: Use lowercase hex for !defines

Re: [DNM RFC PATCH] drm/msm: Use lowercase hex for !defines

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