subject:"Re\: \[PATCH v3 4\/8\] drm\/msm\/dsi\: add support for DSI\-PHY on SM8350 and SM8450"

Re: [PATCH v3 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450

2022-11-14 Thread Konrad Dybcio





On 10/11/2022 23:16, Dmitry Baryshkov wrote:

On 04/11/2022 16:54, Konrad Dybcio wrote:


On 04/11/2022 14:03, Dmitry Baryshkov wrote:

SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm
variants inside the common 5+7nm driver.

Co-developed-by: Robert Foss 
Tested-by: Vinod Koul 
Reviewed-by: Vinod Koul 
Signed-off-by: Dmitry Baryshkov 
---
  drivers/gpu/drm/msm/Kconfig   |   6 +-
  drivers/gpu/drm/msm/dsi/phy/dsi_phy.c |   4 +
  drivers/gpu/drm/msm/dsi/phy/dsi_phy.h |   2 +
  drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 128 --
  4 files changed, 127 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 3c9dfdb0b328..e7b100d97f88 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY
    Choose this option if DSI PHY on SDM845 is used on the platform.
  config DRM_MSM_DSI_7NM_PHY
-    bool "Enable DSI 7nm PHY driver in MSM DRM"
+    bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
  depends on DRM_MSM_DSI
  default y
  help
-  Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on
-  the platform.
+  Choose this option if DSI PHY on 
SM8150/SM8250/SM8350/SM8450/SC7280

+  is used on the platform.
  config DRM_MSM_HDMI
  bool "Enable HDMI support in MSM DRM driver"
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

index ee6051367679..0c956fdab23e 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -569,6 +569,10 @@ static const struct of_device_id 
dsi_phy_dt_match[] = {

    .data = _phy_7nm_8150_cfgs },
  { .compatible = "qcom,sc7280-dsi-phy-7nm",
    .data = _phy_7nm_7280_cfgs },
+    { .compatible = "qcom,dsi-phy-5nm-8350",
+  .data = _phy_5nm_8350_cfgs },
+    { .compatible = "qcom,dsi-phy-5nm-8450",
+  .data = _phy_5nm_8450_cfgs },
  #endif
  {}
  };
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

index 1096afedd616..f7a907ed2b4b 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -57,6 +57,8 @@ extern const struct msm_dsi_phy_cfg 
dsi_phy_10nm_8998_cfgs;

  extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
  extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
  extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
  struct msm_dsi_dphy_timing {
  u32 clk_zero;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

index 9e7fa7d88ead..00d92fe97bc3 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -39,8 +39,14 @@
  #define VCO_REF_CLK_RATE    1920
  #define FRAC_BITS 18
+/* Hardware is pre V4.1 */
+#define DSI_PHY_7NM_QUIRK_PRE_V4_1    BIT(0)
  /* Hardware is V4.1 */
-#define DSI_PHY_7NM_QUIRK_V4_1    BIT(0)
+#define DSI_PHY_7NM_QUIRK_V4_1    BIT(1)
+/* Hardware is V4.2 */
+#define DSI_PHY_7NM_QUIRK_V4_2    BIT(2)
+/* Hardware is V4.3 */
+#define DSI_PHY_7NM_QUIRK_V4_3    BIT(3)


Quirk is quite an unfortunate name considering what we use it for.. but I

suppose it can stay, as otherwise even more renaming would have to be 
done.




  struct dsi_pll_config {
  bool enable_ssc;
@@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct 
dsi_pll_7nm *pll, struct dsi_pll_config

  dec_multiple = div_u64(pll_freq * multiplier, divider);
  dec = div_u64_rem(dec_multiple, multiplier, );
-    if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
+    if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
  config->pll_clock_inverters = 0x28;
  else if (pll_freq <= 10ULL)
  config->pll_clock_inverters = 0xa0;
@@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct 
dsi_pll_7nm *pll)

  void __iomem *base = pll->phy->pll_base;
  u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
-    if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
+    if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
  if (pll->vco_current_rate >= 31ULL)
  analog_controls_five_1 = 0x03;
+    if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
  if (pll->vco_current_rate < 152000ULL)
  vco_config_1 = 0x08;
  else if (pll->vco_current_rate < 299000ULL)
  vco_config_1 = 0x01;
  }
+    if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) ||
+    (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
+    if (pll->vco_current_rate < 152000ULL)
+    vco_config_1 = 0x08;
+    else if (pll->vco_current_rate >=

Re: [PATCH v3 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450

2022-11-10 Thread Dmitry Baryshkov


On 04/11/2022 16:54, Konrad Dybcio wrote:


On 04/11/2022 14:03, Dmitry Baryshkov wrote:

SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm
variants inside the common 5+7nm driver.

Co-developed-by: Robert Foss 
Tested-by: Vinod Koul 
Reviewed-by: Vinod Koul 
Signed-off-by: Dmitry Baryshkov 
---
  drivers/gpu/drm/msm/Kconfig   |   6 +-
  drivers/gpu/drm/msm/dsi/phy/dsi_phy.c |   4 +
  drivers/gpu/drm/msm/dsi/phy/dsi_phy.h |   2 +
  drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 128 --
  4 files changed, 127 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 3c9dfdb0b328..e7b100d97f88 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY
    Choose this option if DSI PHY on SDM845 is used on the platform.
  config DRM_MSM_DSI_7NM_PHY
-    bool "Enable DSI 7nm PHY driver in MSM DRM"
+    bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
  depends on DRM_MSM_DSI
  default y
  help
-  Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on
-  the platform.
+  Choose this option if DSI PHY on 
SM8150/SM8250/SM8350/SM8450/SC7280

+  is used on the platform.
  config DRM_MSM_HDMI
  bool "Enable HDMI support in MSM DRM driver"
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

index ee6051367679..0c956fdab23e 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -569,6 +569,10 @@ static const struct of_device_id 
dsi_phy_dt_match[] = {

    .data = _phy_7nm_8150_cfgs },
  { .compatible = "qcom,sc7280-dsi-phy-7nm",
    .data = _phy_7nm_7280_cfgs },
+    { .compatible = "qcom,dsi-phy-5nm-8350",
+  .data = _phy_5nm_8350_cfgs },
+    { .compatible = "qcom,dsi-phy-5nm-8450",
+  .data = _phy_5nm_8450_cfgs },
  #endif
  {}
  };
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

index 1096afedd616..f7a907ed2b4b 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -57,6 +57,8 @@ extern const struct msm_dsi_phy_cfg 
dsi_phy_10nm_8998_cfgs;

  extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
  extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
  extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
  struct msm_dsi_dphy_timing {
  u32 clk_zero;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

index 9e7fa7d88ead..00d92fe97bc3 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -39,8 +39,14 @@
  #define VCO_REF_CLK_RATE    1920
  #define FRAC_BITS 18
+/* Hardware is pre V4.1 */
+#define DSI_PHY_7NM_QUIRK_PRE_V4_1    BIT(0)
  /* Hardware is V4.1 */
-#define DSI_PHY_7NM_QUIRK_V4_1    BIT(0)
+#define DSI_PHY_7NM_QUIRK_V4_1    BIT(1)
+/* Hardware is V4.2 */
+#define DSI_PHY_7NM_QUIRK_V4_2    BIT(2)
+/* Hardware is V4.3 */
+#define DSI_PHY_7NM_QUIRK_V4_3    BIT(3)


Quirk is quite an unfortunate name considering what we use it for.. but I

suppose it can stay, as otherwise even more renaming would have to be done.



  struct dsi_pll_config {
  bool enable_ssc;
@@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct 
dsi_pll_7nm *pll, struct dsi_pll_config

  dec_multiple = div_u64(pll_freq * multiplier, divider);
  dec = div_u64_rem(dec_multiple, multiplier, );
-    if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
+    if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
  config->pll_clock_inverters = 0x28;
  else if (pll_freq <= 10ULL)
  config->pll_clock_inverters = 0xa0;
@@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct 
dsi_pll_7nm *pll)

  void __iomem *base = pll->phy->pll_base;
  u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
-    if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
+    if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
  if (pll->vco_current_rate >= 31ULL)
  analog_controls_five_1 = 0x03;
+    if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
  if (pll->vco_current_rate < 152000ULL)
  vco_config_1 = 0x08;
  else if (pll->vco_current_rate < 299000ULL)
  vco_config_1 = 0x01;
  }
+    if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) ||
+    (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
+    if (pll->vco_current_rate < 152000ULL)
+    vco_config_1 = 0x08;
+    else if (pll->vco_current_rate >= 299000ULL)
+    vco_config_1 = 0x01;
+

Re: [PATCH v3 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450

2022-11-04 Thread Konrad Dybcio




On 04/11/2022 14:03, Dmitry Baryshkov wrote:

SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm
variants inside the common 5+7nm driver.

Co-developed-by: Robert Foss 
Tested-by: Vinod Koul 
Reviewed-by: Vinod Koul 
Signed-off-by: Dmitry Baryshkov 
---
  drivers/gpu/drm/msm/Kconfig   |   6 +-
  drivers/gpu/drm/msm/dsi/phy/dsi_phy.c |   4 +
  drivers/gpu/drm/msm/dsi/phy/dsi_phy.h |   2 +
  drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 128 --
  4 files changed, 127 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 3c9dfdb0b328..e7b100d97f88 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -140,12 +140,12 @@ config DRM_MSM_DSI_10NM_PHY
  Choose this option if DSI PHY on SDM845 is used on the platform.
  
  config DRM_MSM_DSI_7NM_PHY

-   bool "Enable DSI 7nm PHY driver in MSM DRM"
+   bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
depends on DRM_MSM_DSI
default y
help
- Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on
- the platform.
+ Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280
+ is used on the platform.
  
  config DRM_MSM_HDMI

bool "Enable HDMI support in MSM DRM driver"
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index ee6051367679..0c956fdab23e 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -569,6 +569,10 @@ static const struct of_device_id dsi_phy_dt_match[] = {
  .data = _phy_7nm_8150_cfgs },
{ .compatible = "qcom,sc7280-dsi-phy-7nm",
  .data = _phy_7nm_7280_cfgs },
+   { .compatible = "qcom,dsi-phy-5nm-8350",
+ .data = _phy_5nm_8350_cfgs },
+   { .compatible = "qcom,dsi-phy-5nm-8450",
+ .data = _phy_5nm_8450_cfgs },
  #endif
{}
  };
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 1096afedd616..f7a907ed2b4b 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -57,6 +57,8 @@ extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
  extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
  extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
  extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
  
  struct msm_dsi_dphy_timing {

u32 clk_zero;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 9e7fa7d88ead..00d92fe97bc3 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -39,8 +39,14 @@
  #define VCO_REF_CLK_RATE  1920
  #define FRAC_BITS 18
  
+/* Hardware is pre V4.1 */

+#define DSI_PHY_7NM_QUIRK_PRE_V4_1 BIT(0)
  /* Hardware is V4.1 */
-#define DSI_PHY_7NM_QUIRK_V4_1 BIT(0)
+#define DSI_PHY_7NM_QUIRK_V4_1 BIT(1)
+/* Hardware is V4.2 */
+#define DSI_PHY_7NM_QUIRK_V4_2 BIT(2)
+/* Hardware is V4.3 */
+#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3)


Quirk is quite an unfortunate name considering what we use it for.. but I

suppose it can stay, as otherwise even more renaming would have to be done.


  
  struct dsi_pll_config {

bool enable_ssc;
@@ -116,7 +122,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, 
struct dsi_pll_config
dec_multiple = div_u64(pll_freq * multiplier, divider);
dec = div_u64_rem(dec_multiple, multiplier, );
  
-	if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))

+   if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
config->pll_clock_inverters = 0x28;
else if (pll_freq <= 10ULL)
config->pll_clock_inverters = 0xa0;
@@ -197,16 +203,25 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm 
*pll)
void __iomem *base = pll->phy->pll_base;
u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
  
-	if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {

+   if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1))
if (pll->vco_current_rate >= 31ULL)
analog_controls_five_1 = 0x03;
  
+	if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {

if (pll->vco_current_rate < 152000ULL)
vco_config_1 = 0x08;
else if (pll->vco_current_rate < 299000ULL)
vco_config_1 = 0x01;
}
  
+	if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_2) ||

+   (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
+   if (pll->vco_current_rate < 152000ULL)
+

Re: [PATCH v3 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450

Re: [PATCH v3 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450

Re: [PATCH v3 4/8] drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450

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