Re: drm/komeda: Add support for generation of CRC data per frame.
On Fri, Aug 2, 2019 at 4:50 PM Liviu Dudau wrote:
>
> On Fri, Aug 02, 2019 at 11:52:11AM +0200, Daniel Vetter wrote:
> > On Fri, Aug 2, 2019 at 11:39 AM Brian Starkey wrote:
> > >
> > > Hi Liviu,
> > >
> > > On Thu, Aug 01, 2019 at 11:42:31AM +0100, Liviu Dudau wrote:
> > > > Komeda has support to generate per-frame CRC values in the DOU
> > > > backend subsystem. Implement necessary hooks to expose the CRC
> > > > "control" and "data" file over debugfs and program the DOUx_BS
> > > > accordingly.
> > > >
> > > > This patch makes use of PL1 (programmable line 1) interrupt to
> > > > know when the CRC generation has finished.
> > > >
> > > > Patch is also dependent on the series that adds dual-link support
> > > > for komeda: https://patchwork.freedesktop.org/series/62280/
> > > >
> > > > Cc: "james qian wang (Arm Technology China)"
> > > > Signed-off-by: Liviu Dudau
> > > > ---
> > > > .../arm/display/komeda/d71/d71_component.c| 2 +-
> > > > .../gpu/drm/arm/display/komeda/d71/d71_dev.c | 29 -
> > > > .../gpu/drm/arm/display/komeda/komeda_crtc.c | 61 ++-
> > > > .../gpu/drm/arm/display/komeda/komeda_dev.h | 2 +
> > > > .../gpu/drm/arm/display/komeda/komeda_kms.h | 3 +
> > > > .../drm/arm/display/komeda/komeda_pipeline.h | 1 +
> > > > 6 files changed, 94 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > > b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > > index 55a8cc94808a1..3c45468848ee4 100644
> > > > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > > @@ -1061,7 +1061,7 @@ static void d71_timing_ctrlr_update(struct
> > > > komeda_component *c,
> > > > malidp_write32(reg, BS_PREFETCH_LINE, D71_DEFAULT_PREPRETCH_LINE);
> > > >
> > > > /* configure bs control register */
> > > > - value = BS_CTRL_EN | BS_CTRL_VM;
> > > > + value = BS_CTRL_EN | BS_CTRL_VM | BS_CTRL_CRC;
> > > > if (c->pipeline->dual_link) {
> > > > malidp_write32(reg, BS_DRIFT_TO, hfront_porch + 16);
> > > > value |= BS_CTRL_DL;
> > > > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > > b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > > index d567ab7ed314e..05bfd9891c540 100644
> > > > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > > @@ -115,6 +115,8 @@ static u64 get_dou_event(struct d71_pipeline
> > > > *d71_pipeline)
> > > > raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
> > > > if (raw_status & DOU_IRQ_PL0)
> > > > evts |= KOMEDA_EVENT_VSYNC;
> > > > + if (raw_status & DOU_IRQ_PL1)
> > > > + evts |= KOMEDA_EVENT_CRCDONE;
> > > > if (raw_status & DOU_IRQ_UND)
> > > > evts |= KOMEDA_EVENT_URUN;
> > > >
> > > > @@ -149,7 +151,7 @@ static u64 get_dou_event(struct d71_pipeline
> > > > *d71_pipeline)
> > > >
> > > > static u64 get_pipeline_event(struct d71_pipeline *d71_pipeline, u32
> > > > gcu_status)
> > > > {
> > > > - u32 evts = 0ULL;
> > > > + u64 evts = 0ULL;
> > > >
> > > > if (gcu_status & (GLB_IRQ_STATUS_LPU0 | GLB_IRQ_STATUS_LPU1))
> > > > evts |= get_lpu_event(d71_pipeline);
> > > > @@ -163,6 +165,26 @@ static u64 get_pipeline_event(struct d71_pipeline
> > > > *d71_pipeline, u32 gcu_status)
> > > > return evts;
> > > > }
> > > >
> > > > +static void get_frame_crcs(struct d71_pipeline *d71_pipeline, u32 pipe,
> > > > +struct komeda_events *evts)
> > > > +{
> > > > + if (evts->pipes[pipe] & KOMEDA_EVENT_CRCDONE) {
> > > > + struct komeda_component *c;
> > > > +
> > > > + c = komeda_pipeline_get_component(_pipeline->base,
> > > > +
> > > > KOMEDA_COMPONENT_TIMING_CTRLR);
> > > > + if (!c)
> > > > + return;
> > > > +
> > > > + evts->crcs[pipe][0] = malidp_read32(c->reg, BS_CRC0_LOW);
> > > > + evts->crcs[pipe][1] = malidp_read32(c->reg, BS_CRC0_HIGH);
> > > > + if (d71_pipeline->base.dual_link) {
> > > > + evts->crcs[pipe][2] = malidp_read32(c->reg,
> > > > BS_CRC1_LOW);
> > > > + evts->crcs[pipe][3] = malidp_read32(c->reg,
> > > > BS_CRC1_HIGH);
> > > > + }
> > > > + }
> > > > +}
> > > > +
> > > > static irqreturn_t
> > > > d71_irq_handler(struct komeda_dev *mdev, struct komeda_events *evts)
> > > > {
> > > > @@ -195,6 +217,9 @@ d71_irq_handler(struct komeda_dev *mdev, struct
> > > > komeda_events *evts)
> > > > if (gcu_status & GLB_IRQ_STATUS_PIPE1)
> > > > evts->pipes[1] |= get_pipeline_event(d71->pipes[1],
> > > > gcu_status);
> > > >
> > > > + get_frame_crcs(d71->pipes[0], 0, evts);
> > > > +
Re: drm/komeda: Add support for generation of CRC data per frame.
On Fri, Aug 02, 2019 at 11:52:11AM +0200, Daniel Vetter wrote:
> On Fri, Aug 2, 2019 at 11:39 AM Brian Starkey wrote:
> >
> > Hi Liviu,
> >
> > On Thu, Aug 01, 2019 at 11:42:31AM +0100, Liviu Dudau wrote:
> > > Komeda has support to generate per-frame CRC values in the DOU
> > > backend subsystem. Implement necessary hooks to expose the CRC
> > > "control" and "data" file over debugfs and program the DOUx_BS
> > > accordingly.
> > >
> > > This patch makes use of PL1 (programmable line 1) interrupt to
> > > know when the CRC generation has finished.
> > >
> > > Patch is also dependent on the series that adds dual-link support
> > > for komeda: https://patchwork.freedesktop.org/series/62280/
> > >
> > > Cc: "james qian wang (Arm Technology China)"
> > > Signed-off-by: Liviu Dudau
> > > ---
> > > .../arm/display/komeda/d71/d71_component.c| 2 +-
> > > .../gpu/drm/arm/display/komeda/d71/d71_dev.c | 29 -
> > > .../gpu/drm/arm/display/komeda/komeda_crtc.c | 61 ++-
> > > .../gpu/drm/arm/display/komeda/komeda_dev.h | 2 +
> > > .../gpu/drm/arm/display/komeda/komeda_kms.h | 3 +
> > > .../drm/arm/display/komeda/komeda_pipeline.h | 1 +
> > > 6 files changed, 94 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > index 55a8cc94808a1..3c45468848ee4 100644
> > > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > @@ -1061,7 +1061,7 @@ static void d71_timing_ctrlr_update(struct
> > > komeda_component *c,
> > > malidp_write32(reg, BS_PREFETCH_LINE, D71_DEFAULT_PREPRETCH_LINE);
> > >
> > > /* configure bs control register */
> > > - value = BS_CTRL_EN | BS_CTRL_VM;
> > > + value = BS_CTRL_EN | BS_CTRL_VM | BS_CTRL_CRC;
> > > if (c->pipeline->dual_link) {
> > > malidp_write32(reg, BS_DRIFT_TO, hfront_porch + 16);
> > > value |= BS_CTRL_DL;
> > > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > index d567ab7ed314e..05bfd9891c540 100644
> > > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > @@ -115,6 +115,8 @@ static u64 get_dou_event(struct d71_pipeline
> > > *d71_pipeline)
> > > raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
> > > if (raw_status & DOU_IRQ_PL0)
> > > evts |= KOMEDA_EVENT_VSYNC;
> > > + if (raw_status & DOU_IRQ_PL1)
> > > + evts |= KOMEDA_EVENT_CRCDONE;
> > > if (raw_status & DOU_IRQ_UND)
> > > evts |= KOMEDA_EVENT_URUN;
> > >
> > > @@ -149,7 +151,7 @@ static u64 get_dou_event(struct d71_pipeline
> > > *d71_pipeline)
> > >
> > > static u64 get_pipeline_event(struct d71_pipeline *d71_pipeline, u32
> > > gcu_status)
> > > {
> > > - u32 evts = 0ULL;
> > > + u64 evts = 0ULL;
> > >
> > > if (gcu_status & (GLB_IRQ_STATUS_LPU0 | GLB_IRQ_STATUS_LPU1))
> > > evts |= get_lpu_event(d71_pipeline);
> > > @@ -163,6 +165,26 @@ static u64 get_pipeline_event(struct d71_pipeline
> > > *d71_pipeline, u32 gcu_status)
> > > return evts;
> > > }
> > >
> > > +static void get_frame_crcs(struct d71_pipeline *d71_pipeline, u32 pipe,
> > > +struct komeda_events *evts)
> > > +{
> > > + if (evts->pipes[pipe] & KOMEDA_EVENT_CRCDONE) {
> > > + struct komeda_component *c;
> > > +
> > > + c = komeda_pipeline_get_component(_pipeline->base,
> > > +
> > > KOMEDA_COMPONENT_TIMING_CTRLR);
> > > + if (!c)
> > > + return;
> > > +
> > > + evts->crcs[pipe][0] = malidp_read32(c->reg, BS_CRC0_LOW);
> > > + evts->crcs[pipe][1] = malidp_read32(c->reg, BS_CRC0_HIGH);
> > > + if (d71_pipeline->base.dual_link) {
> > > + evts->crcs[pipe][2] = malidp_read32(c->reg,
> > > BS_CRC1_LOW);
> > > + evts->crcs[pipe][3] = malidp_read32(c->reg,
> > > BS_CRC1_HIGH);
> > > + }
> > > + }
> > > +}
> > > +
> > > static irqreturn_t
> > > d71_irq_handler(struct komeda_dev *mdev, struct komeda_events *evts)
> > > {
> > > @@ -195,6 +217,9 @@ d71_irq_handler(struct komeda_dev *mdev, struct
> > > komeda_events *evts)
> > > if (gcu_status & GLB_IRQ_STATUS_PIPE1)
> > > evts->pipes[1] |= get_pipeline_event(d71->pipes[1],
> > > gcu_status);
> > >
> > > + get_frame_crcs(d71->pipes[0], 0, evts);
> > > + get_frame_crcs(d71->pipes[1], 1, evts);
> > > +
> > > return gcu_status ? IRQ_HANDLED : IRQ_NONE;
> > > }
> > >
> > > @@ -202,7 +227,7 @@ d71_irq_handler(struct komeda_dev *mdev, struct
> > > komeda_events *evts)
> > >GCU_IRQ_MODE |
Re: drm/komeda: Add support for generation of CRC data per frame.
On Fri, Aug 02, 2019 at 10:13:03AM +, Brian Starkey wrote:
> Hi Daniel,
>
> On Fri, Aug 02, 2019 at 11:52:11AM +0200, Daniel Vetter wrote:
> > On Fri, Aug 2, 2019 at 11:39 AM Brian Starkey wrote:
> > >
> > > Hi Liviu,
> > >
> > > On Thu, Aug 01, 2019 at 11:42:31AM +0100, Liviu Dudau wrote:
> > > > Komeda has support to generate per-frame CRC values in the DOU
> > > > backend subsystem. Implement necessary hooks to expose the CRC
> > > > "control" and "data" file over debugfs and program the DOUx_BS
> > > > accordingly.
> > > >
> > > > This patch makes use of PL1 (programmable line 1) interrupt to
> > > > know when the CRC generation has finished.
> > > >
> > > > Patch is also dependent on the series that adds dual-link support
> > > > for komeda: https://patchwork.freedesktop.org/series/62280/
> > > >
> > > > Cc: "james qian wang (Arm Technology China)"
> > > > Signed-off-by: Liviu Dudau
> > > > ---
> > > > .../arm/display/komeda/d71/d71_component.c| 2 +-
> > > > .../gpu/drm/arm/display/komeda/d71/d71_dev.c | 29 -
> > > > .../gpu/drm/arm/display/komeda/komeda_crtc.c | 61 ++-
> > > > .../gpu/drm/arm/display/komeda/komeda_dev.h | 2 +
> > > > .../gpu/drm/arm/display/komeda/komeda_kms.h | 3 +
> > > > .../drm/arm/display/komeda/komeda_pipeline.h | 1 +
> > > > 6 files changed, 94 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > > b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > > index 55a8cc94808a1..3c45468848ee4 100644
> > > > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > > @@ -1061,7 +1061,7 @@ static void d71_timing_ctrlr_update(struct
> > > > komeda_component *c,
> > > > malidp_write32(reg, BS_PREFETCH_LINE, D71_DEFAULT_PREPRETCH_LINE);
> > > >
> > > > /* configure bs control register */
> > > > - value = BS_CTRL_EN | BS_CTRL_VM;
> > > > + value = BS_CTRL_EN | BS_CTRL_VM | BS_CTRL_CRC;
> > > > if (c->pipeline->dual_link) {
> > > > malidp_write32(reg, BS_DRIFT_TO, hfront_porch + 16);
> > > > value |= BS_CTRL_DL;
> > > > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > > b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > > index d567ab7ed314e..05bfd9891c540 100644
> > > > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > > @@ -115,6 +115,8 @@ static u64 get_dou_event(struct d71_pipeline
> > > > *d71_pipeline)
> > > > raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
> > > > if (raw_status & DOU_IRQ_PL0)
> > > > evts |= KOMEDA_EVENT_VSYNC;
> > > > + if (raw_status & DOU_IRQ_PL1)
> > > > + evts |= KOMEDA_EVENT_CRCDONE;
> > > > if (raw_status & DOU_IRQ_UND)
> > > > evts |= KOMEDA_EVENT_URUN;
> > > >
> > > > @@ -149,7 +151,7 @@ static u64 get_dou_event(struct d71_pipeline
> > > > *d71_pipeline)
> > > >
> > > > static u64 get_pipeline_event(struct d71_pipeline *d71_pipeline, u32
> > > > gcu_status)
> > > > {
> > > > - u32 evts = 0ULL;
> > > > + u64 evts = 0ULL;
> > > >
> > > > if (gcu_status & (GLB_IRQ_STATUS_LPU0 | GLB_IRQ_STATUS_LPU1))
> > > > evts |= get_lpu_event(d71_pipeline);
> > > > @@ -163,6 +165,26 @@ static u64 get_pipeline_event(struct d71_pipeline
> > > > *d71_pipeline, u32 gcu_status)
> > > > return evts;
> > > > }
> > > >
> > > > +static void get_frame_crcs(struct d71_pipeline *d71_pipeline, u32 pipe,
> > > > +struct komeda_events *evts)
> > > > +{
> > > > + if (evts->pipes[pipe] & KOMEDA_EVENT_CRCDONE) {
> > > > + struct komeda_component *c;
> > > > +
> > > > + c = komeda_pipeline_get_component(_pipeline->base,
> > > > +
> > > > KOMEDA_COMPONENT_TIMING_CTRLR);
> > > > + if (!c)
> > > > + return;
> > > > +
> > > > + evts->crcs[pipe][0] = malidp_read32(c->reg, BS_CRC0_LOW);
> > > > + evts->crcs[pipe][1] = malidp_read32(c->reg, BS_CRC0_HIGH);
> > > > + if (d71_pipeline->base.dual_link) {
> > > > + evts->crcs[pipe][2] = malidp_read32(c->reg,
> > > > BS_CRC1_LOW);
> > > > + evts->crcs[pipe][3] = malidp_read32(c->reg,
> > > > BS_CRC1_HIGH);
> > > > + }
> > > > + }
> > > > +}
> > > > +
> > > > static irqreturn_t
> > > > d71_irq_handler(struct komeda_dev *mdev, struct komeda_events *evts)
> > > > {
> > > > @@ -195,6 +217,9 @@ d71_irq_handler(struct komeda_dev *mdev, struct
> > > > komeda_events *evts)
> > > > if (gcu_status & GLB_IRQ_STATUS_PIPE1)
> > > > evts->pipes[1] |= get_pipeline_event(d71->pipes[1],
> > > > gcu_status);
> > > >
> > > > + get_frame_crcs(d71->pipes[0],
Re: drm/komeda: Add support for generation of CRC data per frame.
Hi Daniel,
On Fri, Aug 02, 2019 at 11:52:11AM +0200, Daniel Vetter wrote:
> On Fri, Aug 2, 2019 at 11:39 AM Brian Starkey wrote:
> >
> > Hi Liviu,
> >
> > On Thu, Aug 01, 2019 at 11:42:31AM +0100, Liviu Dudau wrote:
> > > Komeda has support to generate per-frame CRC values in the DOU
> > > backend subsystem. Implement necessary hooks to expose the CRC
> > > "control" and "data" file over debugfs and program the DOUx_BS
> > > accordingly.
> > >
> > > This patch makes use of PL1 (programmable line 1) interrupt to
> > > know when the CRC generation has finished.
> > >
> > > Patch is also dependent on the series that adds dual-link support
> > > for komeda: https://patchwork.freedesktop.org/series/62280/
> > >
> > > Cc: "james qian wang (Arm Technology China)"
> > > Signed-off-by: Liviu Dudau
> > > ---
> > > .../arm/display/komeda/d71/d71_component.c| 2 +-
> > > .../gpu/drm/arm/display/komeda/d71/d71_dev.c | 29 -
> > > .../gpu/drm/arm/display/komeda/komeda_crtc.c | 61 ++-
> > > .../gpu/drm/arm/display/komeda/komeda_dev.h | 2 +
> > > .../gpu/drm/arm/display/komeda/komeda_kms.h | 3 +
> > > .../drm/arm/display/komeda/komeda_pipeline.h | 1 +
> > > 6 files changed, 94 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > index 55a8cc94808a1..3c45468848ee4 100644
> > > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > > @@ -1061,7 +1061,7 @@ static void d71_timing_ctrlr_update(struct
> > > komeda_component *c,
> > > malidp_write32(reg, BS_PREFETCH_LINE, D71_DEFAULT_PREPRETCH_LINE);
> > >
> > > /* configure bs control register */
> > > - value = BS_CTRL_EN | BS_CTRL_VM;
> > > + value = BS_CTRL_EN | BS_CTRL_VM | BS_CTRL_CRC;
> > > if (c->pipeline->dual_link) {
> > > malidp_write32(reg, BS_DRIFT_TO, hfront_porch + 16);
> > > value |= BS_CTRL_DL;
> > > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > index d567ab7ed314e..05bfd9891c540 100644
> > > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > > @@ -115,6 +115,8 @@ static u64 get_dou_event(struct d71_pipeline
> > > *d71_pipeline)
> > > raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
> > > if (raw_status & DOU_IRQ_PL0)
> > > evts |= KOMEDA_EVENT_VSYNC;
> > > + if (raw_status & DOU_IRQ_PL1)
> > > + evts |= KOMEDA_EVENT_CRCDONE;
> > > if (raw_status & DOU_IRQ_UND)
> > > evts |= KOMEDA_EVENT_URUN;
> > >
> > > @@ -149,7 +151,7 @@ static u64 get_dou_event(struct d71_pipeline
> > > *d71_pipeline)
> > >
> > > static u64 get_pipeline_event(struct d71_pipeline *d71_pipeline, u32
> > > gcu_status)
> > > {
> > > - u32 evts = 0ULL;
> > > + u64 evts = 0ULL;
> > >
> > > if (gcu_status & (GLB_IRQ_STATUS_LPU0 | GLB_IRQ_STATUS_LPU1))
> > > evts |= get_lpu_event(d71_pipeline);
> > > @@ -163,6 +165,26 @@ static u64 get_pipeline_event(struct d71_pipeline
> > > *d71_pipeline, u32 gcu_status)
> > > return evts;
> > > }
> > >
> > > +static void get_frame_crcs(struct d71_pipeline *d71_pipeline, u32 pipe,
> > > +struct komeda_events *evts)
> > > +{
> > > + if (evts->pipes[pipe] & KOMEDA_EVENT_CRCDONE) {
> > > + struct komeda_component *c;
> > > +
> > > + c = komeda_pipeline_get_component(_pipeline->base,
> > > +
> > > KOMEDA_COMPONENT_TIMING_CTRLR);
> > > + if (!c)
> > > + return;
> > > +
> > > + evts->crcs[pipe][0] = malidp_read32(c->reg, BS_CRC0_LOW);
> > > + evts->crcs[pipe][1] = malidp_read32(c->reg, BS_CRC0_HIGH);
> > > + if (d71_pipeline->base.dual_link) {
> > > + evts->crcs[pipe][2] = malidp_read32(c->reg,
> > > BS_CRC1_LOW);
> > > + evts->crcs[pipe][3] = malidp_read32(c->reg,
> > > BS_CRC1_HIGH);
> > > + }
> > > + }
> > > +}
> > > +
> > > static irqreturn_t
> > > d71_irq_handler(struct komeda_dev *mdev, struct komeda_events *evts)
> > > {
> > > @@ -195,6 +217,9 @@ d71_irq_handler(struct komeda_dev *mdev, struct
> > > komeda_events *evts)
> > > if (gcu_status & GLB_IRQ_STATUS_PIPE1)
> > > evts->pipes[1] |= get_pipeline_event(d71->pipes[1],
> > > gcu_status);
> > >
> > > + get_frame_crcs(d71->pipes[0], 0, evts);
> > > + get_frame_crcs(d71->pipes[1], 1, evts);
> > > +
> > > return gcu_status ? IRQ_HANDLED : IRQ_NONE;
> > > }
> > >
> > > @@ -202,7 +227,7 @@ d71_irq_handler(struct komeda_dev *mdev, struct
> > > komeda_events *evts)
> > >
Re: drm/komeda: Add support for generation of CRC data per frame.
On Fri, Aug 2, 2019 at 11:39 AM Brian Starkey wrote:
>
> Hi Liviu,
>
> On Thu, Aug 01, 2019 at 11:42:31AM +0100, Liviu Dudau wrote:
> > Komeda has support to generate per-frame CRC values in the DOU
> > backend subsystem. Implement necessary hooks to expose the CRC
> > "control" and "data" file over debugfs and program the DOUx_BS
> > accordingly.
> >
> > This patch makes use of PL1 (programmable line 1) interrupt to
> > know when the CRC generation has finished.
> >
> > Patch is also dependent on the series that adds dual-link support
> > for komeda: https://patchwork.freedesktop.org/series/62280/
> >
> > Cc: "james qian wang (Arm Technology China)"
> > Signed-off-by: Liviu Dudau
> > ---
> > .../arm/display/komeda/d71/d71_component.c| 2 +-
> > .../gpu/drm/arm/display/komeda/d71/d71_dev.c | 29 -
> > .../gpu/drm/arm/display/komeda/komeda_crtc.c | 61 ++-
> > .../gpu/drm/arm/display/komeda/komeda_dev.h | 2 +
> > .../gpu/drm/arm/display/komeda/komeda_kms.h | 3 +
> > .../drm/arm/display/komeda/komeda_pipeline.h | 1 +
> > 6 files changed, 94 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > index 55a8cc94808a1..3c45468848ee4 100644
> > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > @@ -1061,7 +1061,7 @@ static void d71_timing_ctrlr_update(struct
> > komeda_component *c,
> > malidp_write32(reg, BS_PREFETCH_LINE, D71_DEFAULT_PREPRETCH_LINE);
> >
> > /* configure bs control register */
> > - value = BS_CTRL_EN | BS_CTRL_VM;
> > + value = BS_CTRL_EN | BS_CTRL_VM | BS_CTRL_CRC;
> > if (c->pipeline->dual_link) {
> > malidp_write32(reg, BS_DRIFT_TO, hfront_porch + 16);
> > value |= BS_CTRL_DL;
> > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > index d567ab7ed314e..05bfd9891c540 100644
> > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > @@ -115,6 +115,8 @@ static u64 get_dou_event(struct d71_pipeline
> > *d71_pipeline)
> > raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
> > if (raw_status & DOU_IRQ_PL0)
> > evts |= KOMEDA_EVENT_VSYNC;
> > + if (raw_status & DOU_IRQ_PL1)
> > + evts |= KOMEDA_EVENT_CRCDONE;
> > if (raw_status & DOU_IRQ_UND)
> > evts |= KOMEDA_EVENT_URUN;
> >
> > @@ -149,7 +151,7 @@ static u64 get_dou_event(struct d71_pipeline
> > *d71_pipeline)
> >
> > static u64 get_pipeline_event(struct d71_pipeline *d71_pipeline, u32
> > gcu_status)
> > {
> > - u32 evts = 0ULL;
> > + u64 evts = 0ULL;
> >
> > if (gcu_status & (GLB_IRQ_STATUS_LPU0 | GLB_IRQ_STATUS_LPU1))
> > evts |= get_lpu_event(d71_pipeline);
> > @@ -163,6 +165,26 @@ static u64 get_pipeline_event(struct d71_pipeline
> > *d71_pipeline, u32 gcu_status)
> > return evts;
> > }
> >
> > +static void get_frame_crcs(struct d71_pipeline *d71_pipeline, u32 pipe,
> > +struct komeda_events *evts)
> > +{
> > + if (evts->pipes[pipe] & KOMEDA_EVENT_CRCDONE) {
> > + struct komeda_component *c;
> > +
> > + c = komeda_pipeline_get_component(_pipeline->base,
> > +
> > KOMEDA_COMPONENT_TIMING_CTRLR);
> > + if (!c)
> > + return;
> > +
> > + evts->crcs[pipe][0] = malidp_read32(c->reg, BS_CRC0_LOW);
> > + evts->crcs[pipe][1] = malidp_read32(c->reg, BS_CRC0_HIGH);
> > + if (d71_pipeline->base.dual_link) {
> > + evts->crcs[pipe][2] = malidp_read32(c->reg,
> > BS_CRC1_LOW);
> > + evts->crcs[pipe][3] = malidp_read32(c->reg,
> > BS_CRC1_HIGH);
> > + }
> > + }
> > +}
> > +
> > static irqreturn_t
> > d71_irq_handler(struct komeda_dev *mdev, struct komeda_events *evts)
> > {
> > @@ -195,6 +217,9 @@ d71_irq_handler(struct komeda_dev *mdev, struct
> > komeda_events *evts)
> > if (gcu_status & GLB_IRQ_STATUS_PIPE1)
> > evts->pipes[1] |= get_pipeline_event(d71->pipes[1],
> > gcu_status);
> >
> > + get_frame_crcs(d71->pipes[0], 0, evts);
> > + get_frame_crcs(d71->pipes[1], 1, evts);
> > +
> > return gcu_status ? IRQ_HANDLED : IRQ_NONE;
> > }
> >
> > @@ -202,7 +227,7 @@ d71_irq_handler(struct komeda_dev *mdev, struct
> > komeda_events *evts)
> >GCU_IRQ_MODE | GCU_IRQ_ERR)
> > #define ENABLED_LPU_IRQS (LPU_IRQ_IBSY | LPU_IRQ_ERR | LPU_IRQ_EOW)
> > #define ENABLED_CU_IRQS (CU_IRQ_OVR | CU_IRQ_ERR)
> > -#define ENABLED_DOU_IRQS (DOU_IRQ_UND | DOU_IRQ_ERR)
> > +#define ENABLED_DOU_IRQS (DOU_IRQ_UND | DOU_IRQ_ERR |
Re: drm/komeda: Add support for generation of CRC data per frame.
Hi Liviu,
On Thu, Aug 01, 2019 at 11:42:31AM +0100, Liviu Dudau wrote:
> Komeda has support to generate per-frame CRC values in the DOU
> backend subsystem. Implement necessary hooks to expose the CRC
> "control" and "data" file over debugfs and program the DOUx_BS
> accordingly.
>
> This patch makes use of PL1 (programmable line 1) interrupt to
> know when the CRC generation has finished.
>
> Patch is also dependent on the series that adds dual-link support
> for komeda: https://patchwork.freedesktop.org/series/62280/
>
> Cc: "james qian wang (Arm Technology China)"
> Signed-off-by: Liviu Dudau
> ---
> .../arm/display/komeda/d71/d71_component.c| 2 +-
> .../gpu/drm/arm/display/komeda/d71/d71_dev.c | 29 -
> .../gpu/drm/arm/display/komeda/komeda_crtc.c | 61 ++-
> .../gpu/drm/arm/display/komeda/komeda_dev.h | 2 +
> .../gpu/drm/arm/display/komeda/komeda_kms.h | 3 +
> .../drm/arm/display/komeda/komeda_pipeline.h | 1 +
> 6 files changed, 94 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> index 55a8cc94808a1..3c45468848ee4 100644
> --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> @@ -1061,7 +1061,7 @@ static void d71_timing_ctrlr_update(struct
> komeda_component *c,
> malidp_write32(reg, BS_PREFETCH_LINE, D71_DEFAULT_PREPRETCH_LINE);
>
> /* configure bs control register */
> - value = BS_CTRL_EN | BS_CTRL_VM;
> + value = BS_CTRL_EN | BS_CTRL_VM | BS_CTRL_CRC;
> if (c->pipeline->dual_link) {
> malidp_write32(reg, BS_DRIFT_TO, hfront_porch + 16);
> value |= BS_CTRL_DL;
> diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> index d567ab7ed314e..05bfd9891c540 100644
> --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> @@ -115,6 +115,8 @@ static u64 get_dou_event(struct d71_pipeline
> *d71_pipeline)
> raw_status = malidp_read32(reg, BLK_IRQ_RAW_STATUS);
> if (raw_status & DOU_IRQ_PL0)
> evts |= KOMEDA_EVENT_VSYNC;
> + if (raw_status & DOU_IRQ_PL1)
> + evts |= KOMEDA_EVENT_CRCDONE;
> if (raw_status & DOU_IRQ_UND)
> evts |= KOMEDA_EVENT_URUN;
>
> @@ -149,7 +151,7 @@ static u64 get_dou_event(struct d71_pipeline
> *d71_pipeline)
>
> static u64 get_pipeline_event(struct d71_pipeline *d71_pipeline, u32
> gcu_status)
> {
> - u32 evts = 0ULL;
> + u64 evts = 0ULL;
>
> if (gcu_status & (GLB_IRQ_STATUS_LPU0 | GLB_IRQ_STATUS_LPU1))
> evts |= get_lpu_event(d71_pipeline);
> @@ -163,6 +165,26 @@ static u64 get_pipeline_event(struct d71_pipeline
> *d71_pipeline, u32 gcu_status)
> return evts;
> }
>
> +static void get_frame_crcs(struct d71_pipeline *d71_pipeline, u32 pipe,
> +struct komeda_events *evts)
> +{
> + if (evts->pipes[pipe] & KOMEDA_EVENT_CRCDONE) {
> + struct komeda_component *c;
> +
> + c = komeda_pipeline_get_component(_pipeline->base,
> +
> KOMEDA_COMPONENT_TIMING_CTRLR);
> + if (!c)
> + return;
> +
> + evts->crcs[pipe][0] = malidp_read32(c->reg, BS_CRC0_LOW);
> + evts->crcs[pipe][1] = malidp_read32(c->reg, BS_CRC0_HIGH);
> + if (d71_pipeline->base.dual_link) {
> + evts->crcs[pipe][2] = malidp_read32(c->reg,
> BS_CRC1_LOW);
> + evts->crcs[pipe][3] = malidp_read32(c->reg,
> BS_CRC1_HIGH);
> + }
> + }
> +}
> +
> static irqreturn_t
> d71_irq_handler(struct komeda_dev *mdev, struct komeda_events *evts)
> {
> @@ -195,6 +217,9 @@ d71_irq_handler(struct komeda_dev *mdev, struct
> komeda_events *evts)
> if (gcu_status & GLB_IRQ_STATUS_PIPE1)
> evts->pipes[1] |= get_pipeline_event(d71->pipes[1], gcu_status);
>
> + get_frame_crcs(d71->pipes[0], 0, evts);
> + get_frame_crcs(d71->pipes[1], 1, evts);
> +
> return gcu_status ? IRQ_HANDLED : IRQ_NONE;
> }
>
> @@ -202,7 +227,7 @@ d71_irq_handler(struct komeda_dev *mdev, struct
> komeda_events *evts)
>GCU_IRQ_MODE | GCU_IRQ_ERR)
> #define ENABLED_LPU_IRQS (LPU_IRQ_IBSY | LPU_IRQ_ERR | LPU_IRQ_EOW)
> #define ENABLED_CU_IRQS (CU_IRQ_OVR | CU_IRQ_ERR)
> -#define ENABLED_DOU_IRQS (DOU_IRQ_UND | DOU_IRQ_ERR)
> +#define ENABLED_DOU_IRQS (DOU_IRQ_UND | DOU_IRQ_ERR | DOU_IRQ_PL1)
>
> static int d71_enable_irq(struct komeda_dev *mdev)
> {
> diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
> b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
> index fa9a4593bb375..4b9f5d33e999d 100644
> ---
