[PATCH v2 09/10] drm/bridge: tc358775: Add support for tc358765
The tc358775 bridge is pin compatible with earlier tc358765 according to
the tc358774xbg_datasheet_en_20190118.pdf documentation. Compared to the
tc358765, the tc358775 supports a STBY GPIO and higher data rates.
The tc358765 has a register bit for video event mode vs video pulse mode.
We must set it to video event mode for the LCD output to work, and on the
tc358775, this bit no longer exists.
Looks like the registers seem to match otherwise based on a quick glance
comparing the defines to the earlier Android kernel tc358765 driver.
Signed-off-by: Tony Lindgren
---
drivers/gpu/drm/bridge/tc358775.c | 26 ++
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358775.c
b/drivers/gpu/drm/bridge/tc358775.c
--- a/drivers/gpu/drm/bridge/tc358775.c
+++ b/drivers/gpu/drm/bridge/tc358775.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
#include
#include
@@ -107,6 +108,7 @@
#define RDPKTLN 0x0404 /* Command Read Packet Length */
#define VPCTRL 0x0450 /* Video Path Control */
+#define EVTMODEBIT(5) /* Video event mode enable, tc35876x
only */
#define HTIM1 0x0454 /* Horizontal Timing Control 1 */
#define HTIM2 0x0458 /* Horizontal Timing Control 2 */
#define VTIM1 0x045C /* Vertical Timing Control 1 */
@@ -254,6 +256,11 @@ enum tc358775_ports {
TC358775_LVDS_OUT1,
};
+enum tc3587x5_type {
+ TC358765,
+ TC358775,
+};
+
struct tc_data {
struct i2c_client *i2c;
struct device *dev;
@@ -271,6 +278,8 @@ struct tc_data {
struct gpio_desc*stby_gpio;
u8 lvds_link; /* single-link or dual-link */
u8 bpc;
+
+ enum tc3587x5_type type;
};
static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
@@ -424,10 +433,16 @@ static void tc_bridge_enable(struct drm_bridge *bridge)
d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION);
d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START);
+ /* Video event mode vs pulse mode bit, does not exist for tc358775 */
+ if (tc->type == TC358765)
+ val = EVTMODE;
+ else
+ val = 0;
+
if (tc->bpc == 8)
- val = TC358775_VPCTRL_OPXLFMT(1);
+ val |= TC358775_VPCTRL_OPXLFMT(1);
else /* bpc = 6; */
- val = TC358775_VPCTRL_MSF(1);
+ val |= TC358775_VPCTRL_MSF(1);
dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000;
clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 :
DIVIDE_BY_3);
@@ -643,6 +658,7 @@ static int tc_probe(struct i2c_client *client)
tc->dev = dev;
tc->i2c = client;
+ tc->type = (enum tc3587x5_type)of_device_get_match_data(dev);
tc->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node,
TC358775_LVDS_OUT0, 0);
@@ -704,13 +720,15 @@ static void tc_remove(struct i2c_client *client)
}
static const struct i2c_device_id tc358775_i2c_ids[] = {
- { "tc358775", 0 },
+ { "tc358765", TC358765, },
+ { "tc358775", TC358775, },
{ }
};
MODULE_DEVICE_TABLE(i2c, tc358775_i2c_ids);
static const struct of_device_id tc358775_of_ids[] = {
- { .compatible = "toshiba,tc358775", },
+ { .compatible = "toshiba,tc358765", .data = (void *)TC358765, },
+ { .compatible = "toshiba,tc358775", .data = (void *)TC358775, },
{ }
};
MODULE_DEVICE_TABLE(of, tc358775_of_ids);
--
2.43.0
[PATCH v2 07/10] drm/bridge: tc358775: Add burst and low-power modes
Burst and low-power modes are supported both for tc358765 and tc358775.
Signed-off-by: Tony Lindgren
---
drivers/gpu/drm/bridge/tc358775.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/tc358775.c
b/drivers/gpu/drm/bridge/tc358775.c
--- a/drivers/gpu/drm/bridge/tc358775.c
+++ b/drivers/gpu/drm/bridge/tc358775.c
@@ -619,7 +619,8 @@ static int tc_attach_host(struct tc_data *tc)
dsi->lanes = tc->num_dsi_lanes;
dsi->format = MIPI_DSI_FMT_RGB888;
- dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+ MIPI_DSI_MODE_LPM;
ret = devm_mipi_dsi_attach(dev, dsi);
if (ret < 0) {
--
2.43.0
[PATCH v2 08/10] drm/bridge: tc358775: Enable pre_enable_prev_first flag
Set pre_enable_prev_first to ensure the previous bridge is enabled first. Signed-off-by: Tony Lindgren --- drivers/gpu/drm/bridge/tc358775.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/bridge/tc358775.c b/drivers/gpu/drm/bridge/tc358775.c --- a/drivers/gpu/drm/bridge/tc358775.c +++ b/drivers/gpu/drm/bridge/tc358775.c @@ -680,6 +680,7 @@ static int tc_probe(struct i2c_client *client) tc->bridge.funcs = _bridge_funcs; tc->bridge.of_node = dev->of_node; + tc->bridge.pre_enable_prev_first = true; drm_bridge_add(>bridge); i2c_set_clientdata(client, tc); -- 2.43.0
Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128
Hi Alex,
Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> Add power controller and qos nodes for RK3128 in order to use
> them as powerdomains.
does the power-domain controller work with the incomplete set of
pm-domains too?
What I have in mind is
- adding the power-controller node with the existing set of power-domains
- the gpu pm-domain is in there
- adding the gpu parts
And a second series with
- patch1 from here
- a dts patch adding the additional pm-domains to rk3128.dtsi
- I guess patch1 also should be split into a patch adding the binding-ids
and a separate patch for the code addition.
Heiko
> Signed-off-by: Alex Bee
> ---
> arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +
> 1 file changed, 101 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> index 4e8b38604ecd..b72905db04f7 100644
> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> @@ -8,6 +8,7 @@
> #include
> #include
> #include
> +#include
>
> / {
> compatible = "rockchip,rk3128";
> @@ -133,6 +134,106 @@ smp-sram@0 {
> pmu: syscon@100a {
> compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
> reg = <0x100a 0x1000>;
> +
> + power: power-controller {
> + compatible = "rockchip,rk3128-power-controller";
> + #power-domain-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + power-domain@RK3128_PD_VIO {
> + reg = ;
> + clocks = < ACLK_CIF>,
> + < HCLK_CIF>,
> + < DCLK_EBC>,
> + < HCLK_EBC>,
> + < ACLK_IEP>,
> + < HCLK_IEP>,
> + < ACLK_LCDC0>,
> + < HCLK_LCDC0>,
> + < PCLK_MIPI>,
> + < ACLK_RGA>,
> + < HCLK_RGA>,
> + < ACLK_VIO0>,
> + < ACLK_VIO1>,
> + < HCLK_VIO>,
> + < HCLK_VIO_H2P>,
> + < DCLK_VOP>,
> + < SCLK_VOP>;
> + pm_qos = <_ebc>,
> + <_iep>,
> + <_lcdc>,
> + <_rga>,
> + <_vip>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3128_PD_VIDEO {
> + reg = ;
> + clocks = < ACLK_VDPU>,
> + < HCLK_VDPU>,
> + < ACLK_VEPU>,
> + < HCLK_VEPU>,
> + < SCLK_HEVC_CORE>;
> + pm_qos = <_vpu>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3128_PD_GPU {
> + reg = ;
> + clocks = < ACLK_GPU>;
> + pm_qos = <_gpu>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3128_PD_CRYPTO {
> + reg = ;
> + clocks = < HCLK_CRYPTO>,
> + < SCLK_CRYPTO>;
> + pm_qos = <_crypto>;
> + #power-domain-cells = <0>;
> + };
> + };
> + };
> +
> + qos_crypto: qos@10128080 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x10128080 0x20>;
> + };
> +
> + qos_gpu: qos@1012d000 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012d000 0x20>;
> + };
> +
> + qos_vpu: qos@1012e000 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012e000 0x20>;
> + };
> +
> + qos_rga: qos@1012f000 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f000 0x20>;
> + };
> +
> + qos_ebc: qos@1012f080 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f080 0x20>;
> + };
> +
> + qos_iep: qos@1012f100 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg =
Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128
Hi Heiko,
Am 02.12.23 um 16:51 schrieb Heiko Stübner:
Hi Alex,
Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
Add power controller and qos nodes for RK3128 in order to use
them as powerdomains.
does the power-domain controller work with the incomplete set of
pm-domains too?
Yes, it does - the missing domains can request idle only and can't be
powered on/off - if no one requests idle they are just up all the time.
What I have in mind is
- adding the power-controller node with the existing set of power-domains
- the gpu pm-domain is in there
- adding the gpu parts
My main concern about adding them later was the change of the ABI after
they've been exposed in the SoC DT. If that's not an issue - sure: I can
add them in a separate series.
And a second series with
- patch1 from here
- a dts patch adding the additional pm-domains to rk3128.dtsi
- I guess patch1 also should be split into a patch adding the binding-ids
and a separate patch for the code addition.
Yeah, I noticed this also :)
Regards,
Alex
Heiko
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +
1 file changed, 101 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi
b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index 4e8b38604ecd..b72905db04f7 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
/ {
compatible = "rockchip,rk3128";
@@ -133,6 +134,106 @@ smp-sram@0 {
pmu: syscon@100a {
compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
reg = <0x100a 0x1000>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3128-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3128_PD_VIO {
+ reg = ;
+ clocks = < ACLK_CIF>,
+< HCLK_CIF>,
+< DCLK_EBC>,
+< HCLK_EBC>,
+< ACLK_IEP>,
+< HCLK_IEP>,
+< ACLK_LCDC0>,
+< HCLK_LCDC0>,
+< PCLK_MIPI>,
+< ACLK_RGA>,
+< HCLK_RGA>,
+< ACLK_VIO0>,
+< ACLK_VIO1>,
+< HCLK_VIO>,
+< HCLK_VIO_H2P>,
+< DCLK_VOP>,
+< SCLK_VOP>;
+ pm_qos = <_ebc>,
+<_iep>,
+<_lcdc>,
+<_rga>,
+<_vip>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3128_PD_VIDEO {
+ reg = ;
+ clocks = < ACLK_VDPU>,
+< HCLK_VDPU>,
+< ACLK_VEPU>,
+< HCLK_VEPU>,
+< SCLK_HEVC_CORE>;
+ pm_qos = <_vpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3128_PD_GPU {
+ reg = ;
+ clocks = < ACLK_GPU>;
+ pm_qos = <_gpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3128_PD_CRYPTO {
+ reg = ;
+ clocks = < HCLK_CRYPTO>,
+< SCLK_CRYPTO>;
+ pm_qos = <_crypto>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ qos_crypto: qos@10128080 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x10128080 0x20>;
+ };
+
+ qos_gpu: qos@1012d000 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012d000 0x20>;
+ };
+
+ qos_vpu: qos@1012e000 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012e000 0x20>;
+ };
+
+ qos_rga: qos@1012f000 {
+
Re: [Nouveau] Thinkpad P17 gen 2 kernel 6.4 and 6.6 lack of support for nvidia GA104GLM [RTX A5000 Mobile] and missing module firmware
On Sat, 2023-12-02 at 09:13 -0800, Marc MERLIN wrote: > [ 3.184525] nouveau: unknown parameter 'modset' ignored For starters, you misspelled "modeset"
Re: (subset) [PATCH v2 0/5] Add power-controller and gpu for RK3128
On Sat, 2 Dec 2023 13:51:39 +0100, Alex Bee wrote: > The first patch in this series fixes the pm-domain driver and adds > power-domains which are currently missing. This touches the ABI which is > not and was never used until now. Not all of them are used yet, but when > the power-controller is added to the DT in patch 2 the ABI should not > be changed again. > Patch 3-5 are adding the the gpu compatible to dt-bindings, adding the gpu > node and the respective operating points to SoC DT and finally enabling it > for XPI-3128 board. > > [...] Applied, thanks! [3/5] dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible commit: 5d86c15c3171c3ecebd84d53e30d9812b5591c84 Best regards, -- Heiko Stuebner
[PATCH v2 10/10] drm/bridge: tc358775: Configure hs_rate and lp_rate
The hs_rate and lp_rate may be used by the dsi host for timing
calculations. The tc358775 has a maximum bit rate of 1 Gbps/lane,
tc358765 has maximurate of 800 Mbps per lane.
Signed-off-by: Tony Lindgren
---
drivers/gpu/drm/bridge/tc358775.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/bridge/tc358775.c
b/drivers/gpu/drm/bridge/tc358775.c
--- a/drivers/gpu/drm/bridge/tc358775.c
+++ b/drivers/gpu/drm/bridge/tc358775.c
@@ -636,6 +636,11 @@ static int tc_attach_host(struct tc_data *tc)
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM;
+ if (tc->type == TC358765)
+ dsi->hs_rate = 8;
+ else
+ dsi->hs_rate = 10;
+ dsi->lp_rate = 1000;
ret = devm_mipi_dsi_attach(dev, dsi);
if (ret < 0) {
--
2.43.0
[PATCH v2 05/10] drm/bridge: tc358775: make standby GPIO optional
From: Michael Walle
The stby pin is optional. It is only needed for power-up and down
sequencing. It is not needed, if the power rails cannot by dynamically
enabled.
Because the GPIO is not optional, remove the error message.
Signed-off-by: Michael Walle
Signed-off-by: Tony Lindgren
---
drivers/gpu/drm/bridge/tc358775.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358775.c
b/drivers/gpu/drm/bridge/tc358775.c
--- a/drivers/gpu/drm/bridge/tc358775.c
+++ b/drivers/gpu/drm/bridge/tc358775.c
@@ -669,12 +669,9 @@ static int tc_probe(struct i2c_client *client)
return ret;
}
- tc->stby_gpio = devm_gpiod_get(dev, "stby", GPIOD_OUT_HIGH);
- if (IS_ERR(tc->stby_gpio)) {
- ret = PTR_ERR(tc->stby_gpio);
- dev_err(dev, "cannot get stby-gpio %d\n", ret);
- return ret;
- }
+ tc->stby_gpio = devm_gpiod_get_optional(dev, "stby", GPIOD_OUT_HIGH);
+ if (IS_ERR(tc->stby_gpio))
+ return PTR_ERR(tc->stby_gpio);
tc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(tc->reset_gpio)) {
--
2.43.0
Re: [PATCH 01/17] drm/msm: add arrays listing formats supported by MDP4/MDP5 hardware
On 02/12/2023 03:36, Abhinav Kumar wrote:
On 7/7/2023 6:03 PM, Dmitry Baryshkov wrote:
MDP4 and MDP5 drivers enumerate supported formats each time the plane is
created. As the list of supported image formats is constant, create
corresponding data arrays to be used by MDP4 and MDP5 drivers.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp_format.c | 49 +--
drivers/gpu/drm/msm/disp/mdp_kms.h | 5 +++
2 files changed, 52 insertions(+), 2 deletions(-)
After going through the patch series, as commented in patch 17 I am
totally fine with migrating to drmm-managed APIs but I dont like to
maintain 3 format arrays.
Can we keep the existing format mechanism to avoid having two more arrays?
For DPU we have exactly the same idea: single formats data array
describing and per-usecase arrays, like plane RGB arrays, plane YUV+RGB
array, WB arrays.
Anyway. formats was one of the topics where we had a lot of duplication
between mdp4/mdp5 and dpu anyway. I think I'm going to back up the
patches 1, 10, 16, 17 (plane patches depend on the format arrays), push
the rest of the patches to msm-next-lumag and send a series reworking
all the formats handling.
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c
b/drivers/gpu/drm/msm/disp/mdp_format.c
index 025595336f26..ba9abe8b3acc 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.c
+++ b/drivers/gpu/drm/msm/disp/mdp_format.c
@@ -81,8 +81,8 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
#define BPC0A 0
/*
- * Note: Keep RGB formats 1st, followed by YUV formats to avoid breaking
- * mdp_get_rgb_formats()'s implementation.
+ * Note: Keep mdp_rgb_formats and mdp_rgb_yuv_formats in sync when
adding
+ * entries to this array.
*/
static const struct mdp_format formats[] = {
/* name a r g b e0 e1 e2 e3 alpha tight cpp cnt
... */
@@ -138,6 +138,51 @@ static const struct mdp_format formats[] = {
MDP_PLANE_PLANAR, CHROMA_420, true),
};
+const uint32_t mdp_rgb_formats[] = {
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_RGBA,
+ DRM_FORMAT_BGRA,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_RGBX,
+ DRM_FORMAT_BGRX,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+};
+
+size_t mdp_rgb_num_formats = ARRAY_SIZE(mdp_rgb_formats);
+
+const uint32_t mdp_rgb_yuv_formats[] = {
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_RGBA,
+ DRM_FORMAT_BGRA,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_RGBX,
+ DRM_FORMAT_BGRX,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_NV21,
+ DRM_FORMAT_NV16,
+ DRM_FORMAT_NV61,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_YUV420,
+ DRM_FORMAT_YVU420,
+};
+
+size_t mdp_rgb_yuv_num_formats = ARRAY_SIZE(mdp_rgb_yuv_formats);
+
/*
* Note:
* @rgb_only must be set to true, when requesting
diff --git a/drivers/gpu/drm/msm/disp/mdp_kms.h
b/drivers/gpu/drm/msm/disp/mdp_kms.h
index b0286d5d5130..11402a859574 100644
--- a/drivers/gpu/drm/msm/disp/mdp_kms.h
+++ b/drivers/gpu/drm/msm/disp/mdp_kms.h
@@ -94,6 +94,11 @@ struct mdp_format {
uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats,
bool rgb_only);
const struct msm_format *mdp_get_format(struct msm_kms *kms,
uint32_t format, uint64_t modifier);
+extern const uint32_t mdp_rgb_formats[];
+extern size_t mdp_rgb_num_formats;
+extern const uint32_t mdp_rgb_yuv_formats[];
+extern size_t mdp_rgb_yuv_num_formats;
+
/* MDP capabilities */
#define MDP_CAP_SMP BIT(0) /* Shared Memory
Pool */
#define MDP_CAP_DSC BIT(1) /* VESA Display Stream
Compression */
--
With best wishes
Dmitry
Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128
Hi Alex,
Am Samstag, 2. Dezember 2023, 17:36:15 CET schrieb Alex Bee:
> Am 02.12.23 um 16:51 schrieb Heiko Stübner:
> > Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> >> Add power controller and qos nodes for RK3128 in order to use
> >> them as powerdomains.
> > does the power-domain controller work with the incomplete set of
> > pm-domains too?
>
> Yes, it does - the missing domains can request idle only and can't be
> powered on/off - if no one requests idle they are just up all the time.
>
> > What I have in mind is
> > - adding the power-controller node with the existing set of power-domains
> > - the gpu pm-domain is in there
> > - adding the gpu parts
>
> My main concern about adding them later was the change of the ABI after
> they've been exposed in the SoC DT. If that's not an issue - sure: I can
> add them in a separate series.
An ABI change would be _changing_ the domain-ids in the rk3128-power.h
I think :-) .
Right now the existing domain ids in the header are already exposed to the
world, so someone could already use them, but not the new ones.
Heiko
> > And a second series with
> > - patch1 from here
> > - a dts patch adding the additional pm-domains to rk3128.dtsi
> > - I guess patch1 also should be split into a patch adding the binding-ids
> >and a separate patch for the code addition.
>
> Yeah, I noticed this also :)
>
> Regards,
>
> Alex
>
> >
> >
> > Heiko
> >
> >> Signed-off-by: Alex Bee
> >> ---
> >> arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +
> >> 1 file changed, 101 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >> b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >> index 4e8b38604ecd..b72905db04f7 100644
> >> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> >> @@ -8,6 +8,7 @@
> >> #include
> >> #include
> >> #include
> >> +#include
> >>
> >> / {
> >>compatible = "rockchip,rk3128";
> >> @@ -133,6 +134,106 @@ smp-sram@0 {
> >>pmu: syscon@100a {
> >>compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
> >>reg = <0x100a 0x1000>;
> >> +
> >> + power: power-controller {
> >> + compatible = "rockchip,rk3128-power-controller";
> >> + #power-domain-cells = <1>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + power-domain@RK3128_PD_VIO {
> >> + reg = ;
> >> + clocks = < ACLK_CIF>,
> >> + < HCLK_CIF>,
> >> + < DCLK_EBC>,
> >> + < HCLK_EBC>,
> >> + < ACLK_IEP>,
> >> + < HCLK_IEP>,
> >> + < ACLK_LCDC0>,
> >> + < HCLK_LCDC0>,
> >> + < PCLK_MIPI>,
> >> + < ACLK_RGA>,
> >> + < HCLK_RGA>,
> >> + < ACLK_VIO0>,
> >> + < ACLK_VIO1>,
> >> + < HCLK_VIO>,
> >> + < HCLK_VIO_H2P>,
> >> + < DCLK_VOP>,
> >> + < SCLK_VOP>;
> >> + pm_qos = <_ebc>,
> >> + <_iep>,
> >> + <_lcdc>,
> >> + <_rga>,
> >> + <_vip>;
> >> + #power-domain-cells = <0>;
> >> + };
> >> +
> >> + power-domain@RK3128_PD_VIDEO {
> >> + reg = ;
> >> + clocks = < ACLK_VDPU>,
> >> + < HCLK_VDPU>,
> >> + < ACLK_VEPU>,
> >> + < HCLK_VEPU>,
> >> + < SCLK_HEVC_CORE>;
> >> + pm_qos = <_vpu>;
> >> + #power-domain-cells = <0>;
> >> + };
> >> +
> >> + power-domain@RK3128_PD_GPU {
> >> + reg = ;
> >> + clocks = < ACLK_GPU>;
> >> + pm_qos = <_gpu>;
> >> + #power-domain-cells = <0>;
> >> + };
> >> +
> >> + power-domain@RK3128_PD_CRYPTO {
> >> + reg = ;
> >> + clocks = < HCLK_CRYPTO>,
> >> + < SCLK_CRYPTO>;
> >> + pm_qos = <_crypto>;
> >> + #power-domain-cells = <0>;
> >> + };
> >> + };
> >> +
[PATCH v2 06/10] drm/bridge: tc358775: Get bridge data lanes instead of the DSI host lanes
The current code assumes the data-lanes property is configured on the
DSI host side instead of the bridge side, and assumes DSI host endpoint 1.
Let's standardize on what the other bridge drivers are doing and parse the
data-lanes property for the bridge. Only if data-lanes property is not found,
let's be nice and also check the DSI host for old dtb in use and warn.
Signed-off-by: Tony Lindgren
---
drivers/gpu/drm/bridge/tc358775.c | 25 +++--
1 file changed, 11 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358775.c
b/drivers/gpu/drm/bridge/tc358775.c
--- a/drivers/gpu/drm/bridge/tc358775.c
+++ b/drivers/gpu/drm/bridge/tc358775.c
@@ -525,27 +525,24 @@ tc_mode_valid(struct drm_bridge *bridge,
static int tc358775_parse_dt(struct device_node *np, struct tc_data *tc)
{
struct device_node *endpoint;
- struct device_node *parent;
struct device_node *remote;
int dsi_lanes = -1;
- /*
-* To get the data-lanes of dsi, we need to access the dsi0_out of port1
-* of dsi0 endpoint from bridge port0 of d2l_in
-*/
endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
TC358775_DSI_IN, -1);
- if (endpoint) {
- /* dsi0_out node */
- parent = of_graph_get_remote_port_parent(endpoint);
- of_node_put(endpoint);
- if (parent) {
- /* dsi0 port 1 */
- dsi_lanes = drm_of_get_data_lanes_count_ep(parent, 1,
-1, 1, 4);
- of_node_put(parent);
- }
+ dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4);
+
+ /* Quirk old dtb: Use data lanes from the DSI host side instead of
bridge */
+ if (dsi_lanes == -EINVAL || dsi_lanes == -ENODEV) {
+ remote = of_graph_get_remote_endpoint(endpoint);
+ dsi_lanes = drm_of_get_data_lanes_count(remote, 1, 4);
+ of_node_put(remote);
+ if (dsi_lanes >= 1)
+ dev_warn(tc->dev, "missing dsi-lanes property for the
bridge\n");
}
+ of_node_put(endpoint);
+
if (dsi_lanes < 0)
return dsi_lanes;
--
2.43.0
[PATCH 1/2] dt-bindings: display: simple: Add boe, bp082wx1-100 8.2" panel
This panel is found on Motorola mapphone tablets mz607 to mz609. Signed-off-by: Tony Lindgren --- .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -73,6 +73,8 @@ properties: - auo,t215hvn01 # Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel - avic,tm070ddh03 +# BOE BP082WX1-100 8.2" WXGA (1280x800) LVDS panel + - boe,bp082wx1-100 # BOE BP101WX1-100 10.1" WXGA (1280x800) LVDS panel - boe,bp101wx1-100 # BOE EV121WXM-N10-1850 12.1" WXGA (1280x800) TFT LCD panel -- 2.43.0
[PATCH 2/2] drm/panel: simple: Add BOE BP082WX1-100 8.2" panel
The BOE BP082WX1-100 is a 8.2" panel similar to the 10.1" panel
BP101WX1-100. Both panels use the same timings.
Signed-off-by: Tony Lindgren
---
drivers/gpu/drm/panel/panel-simple.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1336,6 +1336,23 @@ static const struct drm_display_mode
boe_bp101wx1_100_mode = {
.vtotal = 800 + 6 + 8 + 2,
};
+static const struct panel_desc boe_bp082wx1_100 = {
+ .modes = _bp101wx1_100_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 180,
+ .height = 114,
+ },
+ .delay = {
+ .enable = 50,
+ .disable = 50,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH,
+ .connector_type = DRM_MODE_CONNECTOR_LVDS,
+};
+
static const struct panel_desc boe_bp101wx1_100 = {
.modes = _bp101wx1_100_mode,
.num_modes = 1,
@@ -4281,6 +4298,9 @@ static const struct of_device_id platform_of_match[] = {
}, {
.compatible = "bananapi,s070wv20-ct16",
.data = _s070wv20_ct16,
+ }, {
+ .compatible = "boe,bp082wx1-100",
+ .data = _bp082wx1_100,
}, {
.compatible = "boe,bp101wx1-100",
.data = _bp101wx1_100,
--
2.43.0
[PATCH v2 0/5] Add power-controller and gpu for RK3128
The first patch in this series fixes the pm-domain driver and adds power-domains which are currently missing. This touches the ABI which is not and was never used until now. Not all of them are used yet, but when the power-controller is added to the DT in patch 2 the ABI should not be changed again. Patch 3-5 are adding the the gpu compatible to dt-bindings, adding the gpu node and the respective operating points to SoC DT and finally enabling it for XPI-3128 board. Note: DT patches are based on maintainer's repo. Alex Bee (5): pmdomain: rockchip: Add missing powerdomains for RK3128 ARM: dts: rockchip: Add power-controller for RK3128 dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible ARM: dts: rockchip: Add GPU node for RK3128 ARM: dts: rockchip: Enable GPU for XPI-3128 .../bindings/gpu/arm,mali-utgard.yaml | 1 + .../arm/boot/dts/rockchip/rk3128-xpi-3128.dts | 5 + arch/arm/boot/dts/rockchip/rk3128.dtsi| 145 ++ drivers/pmdomain/rockchip/pm-domains.c| 13 +- include/dt-bindings/power/rk3128-power.h | 3 + 5 files changed, 162 insertions(+), 5 deletions(-) base-commit: fd610e604837936440ef7c64ab6998b004631647 -- 2.43.0
[PATCH v2 5/5] ARM: dts: rockchip: Enable GPU for XPI-3128
Add the supply and enable gpu node for XPI-3128 board.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
b/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
index 61b9f069c8a2..0a8ead0bfe09 100644
--- a/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
+++ b/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts
@@ -315,6 +315,11 @@ {
"", "", "", "";
};
+ {
+ mali-supply = <_log>;
+ status = "okay";
+};
+
{
dp83848c {
dp83848c_rst: dp83848c-rst {
--
2.43.0
[PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128
Add power controller and qos nodes for RK3128 in order to use
them as powerdomains.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +
1 file changed, 101 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi
b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index 4e8b38604ecd..b72905db04f7 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
/ {
compatible = "rockchip,rk3128";
@@ -133,6 +134,106 @@ smp-sram@0 {
pmu: syscon@100a {
compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
reg = <0x100a 0x1000>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3128-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3128_PD_VIO {
+ reg = ;
+ clocks = < ACLK_CIF>,
+< HCLK_CIF>,
+< DCLK_EBC>,
+< HCLK_EBC>,
+< ACLK_IEP>,
+< HCLK_IEP>,
+< ACLK_LCDC0>,
+< HCLK_LCDC0>,
+< PCLK_MIPI>,
+< ACLK_RGA>,
+< HCLK_RGA>,
+< ACLK_VIO0>,
+< ACLK_VIO1>,
+< HCLK_VIO>,
+< HCLK_VIO_H2P>,
+< DCLK_VOP>,
+< SCLK_VOP>;
+ pm_qos = <_ebc>,
+<_iep>,
+<_lcdc>,
+<_rga>,
+<_vip>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3128_PD_VIDEO {
+ reg = ;
+ clocks = < ACLK_VDPU>,
+< HCLK_VDPU>,
+< ACLK_VEPU>,
+< HCLK_VEPU>,
+< SCLK_HEVC_CORE>;
+ pm_qos = <_vpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3128_PD_GPU {
+ reg = ;
+ clocks = < ACLK_GPU>;
+ pm_qos = <_gpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3128_PD_CRYPTO {
+ reg = ;
+ clocks = < HCLK_CRYPTO>,
+< SCLK_CRYPTO>;
+ pm_qos = <_crypto>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ qos_crypto: qos@10128080 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x10128080 0x20>;
+ };
+
+ qos_gpu: qos@1012d000 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012d000 0x20>;
+ };
+
+ qos_vpu: qos@1012e000 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012e000 0x20>;
+ };
+
+ qos_rga: qos@1012f000 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012f000 0x20>;
+ };
+
+ qos_ebc: qos@1012f080 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012f080 0x20>;
+ };
+
+ qos_iep: qos@1012f100 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012f100 0x20>;
+ };
+
+ qos_lcdc: qos@1012f180 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012f180 0x20>;
+ };
+
+ qos_vip: qos@1012f200 {
+ compatible = "rockchip,rk3128-qos", "syscon";
+ reg = <0x1012f200 0x20>;
};
gic: interrupt-controller@10139000 {
--
2.43.0
[PATCH v2 1/5] pmdomain: rockchip: Add missing powerdomains for RK3128
For RK3128 the powerdomains PD_PERI, PD_SYS and PD_CRYPTO are currently
missing.
Add them.
Signed-off-by: Alex Bee
---
drivers/pmdomain/rockchip/pm-domains.c | 13 -
include/dt-bindings/power/rk3128-power.h | 3 +++
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/pmdomain/rockchip/pm-domains.c
b/drivers/pmdomain/rockchip/pm-domains.c
index 9b76b62869d0..62ba4129f6bb 100644
--- a/drivers/pmdomain/rockchip/pm-domains.c
+++ b/drivers/pmdomain/rockchip/pm-domains.c
@@ -998,11 +998,14 @@ static const struct rockchip_domain_info
rk3066_pm_domains[] = {
};
static const struct rockchip_domain_info rk3128_pm_domains[] = {
- [RK3128_PD_CORE]= DOMAIN_RK3288("core", BIT(0), BIT(0),
BIT(4), false),
- [RK3128_PD_MSCH]= DOMAIN_RK3288("msch", 0, 0,
BIT(6), true),
- [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3),
BIT(2), false),
- [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2),
BIT(1), false),
- [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1),
BIT(3), false),
+ [RK3128_PD_CORE]= DOMAIN_RK3288("core", BIT(0), BIT(0),
BIT(4), false),
+ [RK3128_PD_MSCH]= DOMAIN_RK3288("msch", 0, 0,
BIT(6), true),
+ [RK3128_PD_VIO] = DOMAIN_RK3288("vio",BIT(3), BIT(3),
BIT(2), false),
+ [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2),
BIT(1), false),
+ [RK3128_PD_GPU] = DOMAIN_RK3288("gpu",BIT(1), BIT(1),
BIT(3), false),
+ [RK3128_PD_PERI]= DOMAIN_RK3288("peri", 0, 0,
BIT(0), false),
+ [RK3128_PD_SYS] = DOMAIN_RK3288("sys",0, 0,
BIT(5), true),
+ [RK3128_PD_CRYPTO] = DOMAIN_RK3288("crypto", 0, 0,
BIT(7), false),
};
static const struct rockchip_domain_info rk3188_pm_domains[] = {
diff --git a/include/dt-bindings/power/rk3128-power.h
b/include/dt-bindings/power/rk3128-power.h
index c051dc3108db..68af6c68c272 100644
--- a/include/dt-bindings/power/rk3128-power.h
+++ b/include/dt-bindings/power/rk3128-power.h
@@ -10,5 +10,8 @@
#define RK3128_PD_VIDEO2
#define RK3128_PD_GPU 3
#define RK3128_PD_MSCH 4
+#define RK3128_PD_PERI 5
+#define RK3128_PD_SYS 6
+#define RK3128_PD_CRYPTO 7
#endif
--
2.43.0
[PATCH v2 3/5] dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible
Rockchip RK312x SoC family has a Mali400 MP2. Add a compatible for it. Signed-off-by: Alex Bee Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml index 0fae1ef013be..abd4aa335fbc 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml @@ -29,6 +29,7 @@ properties: - allwinner,sun50i-a64-mali - rockchip,rk3036-mali - rockchip,rk3066-mali + - rockchip,rk3128-mali - rockchip,rk3188-mali - rockchip,rk3228-mali - samsung,exynos4210-mali -- 2.43.0
[PATCH v2 4/5] ARM: dts: rockchip: Add GPU node for RK3128
RK3128 SoCs have Mali400 MP2 GPU.
Add the respective device tree node and the correspondending opp-table.
The frequencies and voltages of the opp-table have been taken from
downstream kernel.
Signed-off-by: Alex Bee
---
arch/arm/boot/dts/rockchip/rk3128.dtsi | 44 ++
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi
b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index b72905db04f7..b05ee3d926aa 100644
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -101,6 +101,27 @@ opp-12 {
};
};
+ gpu_opp_table: opp-table-1 {
+ compatible = "operating-points-v2";
+
+ opp-2 {
+ opp-hz = /bits/ 64 <2>;
+ opp-microvolt = <975000 975000 125>;
+ };
+ opp-3 {
+ opp-hz = /bits/ 64 <3>;
+ opp-microvolt = <105 105 125>;
+ };
+ opp-4 {
+ opp-hz = /bits/ 64 <4>;
+ opp-microvolt = <115 115 125>;
+ };
+ opp-48000 {
+ opp-hz = /bits/ 64 <48000>;
+ opp-microvolt = <125 125 125>;
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = ,
@@ -131,6 +152,29 @@ smp-sram@0 {
};
};
+ gpu: gpu@1009 {
+ compatible = "rockchip,rk3128-mali", "arm,mali-400";
+ reg = <0x1009 0x1>;
+ interrupts = ,
+,
+,
+,
+,
+;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1";
+ clocks = < ACLK_GPU>, < ACLK_GPU>;
+ clock-names = "bus", "core";
+ power-domains = < RK3128_PD_GPU>;
+ resets = < SRST_GPU>;
+ operating-points-v2 = <_opp_table>;
+ status = "disabled";
+ };
+
pmu: syscon@100a {
compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
reg = <0x100a 0x1000>;
--
2.43.0
Re: Kernel problem with multiseat on one card
On Thu, Nov 30, 2023 at 11:48:24AM +0100, Gert Vanhaerents wrote: > Hi Kernel list, > I'm the IT person of a school, earlier we used multiseatcomputers for the > school, i have maded with a XGL implementation and it works fine but not so > fantastic. The school wants that i build new computers but the XGL project > is too outdated so i can't use it anymore. > > How can i make a multiseatcomputer with more then one user on one card with > systemd? I have asked already to the makers of systemd but they said it's a > kernel problem. > > With Systemd loginctl and the nouveau drivers you have this: > > ─/sys/devices/pci:00/:00:03.1/:08:00.0/drm/card0 > │ [MASTER] drm:card0 > │ > ├─/sys/devices/pci:00/:00:03.1/:08:00.0/drm/card0/card0-DVI-D-1 > │ │ [MASTER] drm:card0-DVI-D-1 > │ > ├─/sys/devices/pci:00/:00:03.1/:08:00.0/drm/card0/card0-HDMI-A-1 > │ │ [MASTER] drm:card0-HDMI-A-1 > │ > └─/sys/devices/pci:00/:00:03.1/:08:00.0/drm/card0/card0-VGA-1 > │ [MASTER] drm:card0-VGA-1 > ├─/sys/devices/pci:00/:00:03.1/:08:00.0/drm/renderD128 > │ drm:renderD128 > ├─/sys/devices/pci:00/:00:03.1/:08:00.0/graphics/fb0 > │ graphics:fb0 "nouveaudrmfb" > > So it will be: > > loginctl attach seat1 > /sys/devices/pci:00/:00:03.1/:08:00.0/drm/card0/card0-VGA-1 > > For the seat1 (the VGA d-sub output for seat1 and the other HDMI output for > seat0) and of course the mouse and keyboard. > > When you do this, all the graphics outputs are on the second seat (seat1) > and not anymore on the first seat. So i need to move only the VGA output to > seat1 and not all the outputs. Do you expect that GUI output is on both seats? > > > When i install the proprietary Nvidia drivers, i have the following: > > [MASTER] pci::08:00.0 > │ ├─/sys/devices/pci:00/:00:03.1/:08:00.0/drm/card0 > │ │ [MASTER] drm:card0 > │ > └─/sys/devices/pci:00/:00:03.1/:08:00.0/drm/renderD128 > │ drm:renderD128 > > ─/sys/devices/platform/efi-framebuffer.0/graphics/fb0 > │ graphics:fb0 "EFI VGA" > > So no VGA, DVI or HDMI items. Then report to the GitHub tracker [1]. Thanks. [1]: https://github.com/NVIDIA/open-gpu-kernel-modules/issues -- An old man doll... just what I always wanted! - Clara signature.asc Description: PGP signature
[PATCH v2 04/10] drm/bridge: tc358775: fix support for jeida-18 and jeida-24
From: Michael Walle
The bridge always uses 24bpp internally. Therefore, for jeida-18
mapping we need to discard the lowest two bits for each channel and thus
starting with LV_[RGB]2. jeida-24 has the same mapping but uses four
lanes instead of three, with the forth pair transmitting the lowest two
bits of each channel. Thus, the mapping between jeida-18 and jeida-24
is actually the same, except that one channel is turned off (by
selecting the RGB666 format in VPCTRL).
While at it, remove the bogus comment about the hardware default because
the default is overwritten in any case.
Tested with a jeida-18 display (Evervision VGG644804).
Fixes: b26975593b17 ("display/drm/bridge: TC358775 DSI/LVDS driver")
Signed-off-by: Michael Walle
Signed-off-by: Tony Lindgren
---
drivers/gpu/drm/bridge/tc358775.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358775.c
b/drivers/gpu/drm/bridge/tc358775.c
--- a/drivers/gpu/drm/bridge/tc358775.c
+++ b/drivers/gpu/drm/bridge/tc358775.c
@@ -454,10 +454,6 @@ static void tc_bridge_enable(struct drm_bridge *bridge)
dev_dbg(tc->dev, "bus_formats %04x bpc %d\n",
connector->display_info.bus_formats[0],
tc->bpc);
- /*
-* Default hardware register settings of tc358775 configured
-* with MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA jeida-24 format
-*/
if (connector->display_info.bus_formats[0] ==
MEDIA_BUS_FMT_RGB888_1X7X4_SPWG) {
/* VESA-24 */
@@ -468,14 +464,15 @@ static void tc_bridge_enable(struct drm_bridge *bridge)
d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1,
LVI_B2));
d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5,
LVI_L0));
d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE,
LVI_R6));
- } else { /* MEDIA_BUS_FMT_RGB666_1X7X3_SPWG - JEIDA-18 */
- d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2,
LVI_R3));
- d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_L0, LVI_R5,
LVI_G0));
- d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_L0,
LVI_L0));
- d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5,
LVI_B0));
- d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_L0, LVI_L0, LVI_B1,
LVI_B2));
- d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5,
LVI_L0));
- d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE,
LVI_L0));
+ } else {
+ /* JEIDA-18 and JEIDA-24 */
+ d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R2, LVI_R3, LVI_R4,
LVI_R5));
+ d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R6, LVI_R1, LVI_R7,
LVI_G2));
+ d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G3, LVI_G4, LVI_G0,
LVI_G1));
+ d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G5, LVI_G6, LVI_G7,
LVI_B2));
+ d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B0, LVI_B1, LVI_B3,
LVI_B4));
+ d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B5, LVI_B6, LVI_B7,
LVI_L0));
+ d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE,
LVI_R0));
}
d2l_write(tc->i2c, VFUEN, VFUEN_EN);
--
2.43.0
Re: [Nouveau] Kernel problem with multiseat on one card
On Sat, 2023-12-02 at 20:18 +0700, Bagas Sanjaya wrote: > > > When i install the proprietary Nvidia drivers, i have the following: > > > > [MASTER] pci::08:00.0 > > │ ├─/sys/devices/pci:00/:00:03.1/:08:00.0/drm/card0 > > │ │ [MASTER] drm:card0 > > │ > > └─/sys/devices/pci:00/:00:03.1/:08:00.0/drm/renderD128 > > │ drm:renderD128 > > > > ─/sys/devices/platform/efi-framebuffer.0/graphics/fb0 > > │ graphics:fb0 "EFI VGA" > > > > So no VGA, DVI or HDMI items. > > Then report to the GitHub tracker [1]. > > Thanks. > > [1]: https://github.com/NVIDIA/open-gpu-kernel-modules/issues > No, do NOT report this on the Github tracker! That github tracker is ONLY for bugs that occur with OpenRM (the "Open GPU Kernel Module") but not with the the proprietary driver. If you have a bug with the the Nvidia proprietary driver, that must be reported on the Nvidia forum instead: https://forums.developer.nvidia.com/c/gpu-graphics/linux/148
Re: [PATCH 2/2] drm/msm/dpu: Set input_sel bit for INTF
On 01/12/2023 23:29, Abhinav Kumar wrote:
On 11/30/2023 11:36 PM, Dmitry Baryshkov wrote:
On Fri, 1 Dec 2023 at 03:31, Jessica Zhang
wrote:
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark
Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for
interface")
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 7 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 4 +++-
4 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 3442cf65b86f..d0884997ecb7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -320,7 +320,7 @@ static u32 dpu_hw_intf_get_line_count(struct
dpu_hw_intf *intf)
static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf)
{
- dpu_hw_setup_misr(>hw, INTF_MISR_CTRL);
+ dpu_hw_setup_misr(>hw, INTF_MISR_CTRL, true);
}
static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32
*misr_value)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index f38473e68f79..77b14107c84a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -83,7 +83,7 @@ static void dpu_hw_lm_setup_border_color(struct
dpu_hw_mixer *ctx,
static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx)
{
- dpu_hw_setup_misr(>hw, LM_MISR_CTRL);
+ dpu_hw_setup_misr(>hw, LM_MISR_CTRL, false);
}
static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32
*misr_value)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
index a8a0a4e76b94..f441df47fdde 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
@@ -481,7 +481,8 @@ void _dpu_hw_setup_qos_lut(struct
dpu_hw_blk_reg_map *c, u32 offset,
cfg->danger_safe_en ?
QOS_QOS_CTRL_DANGER_SAFE_EN : 0);
}
-void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, u32
misr_ctrl_offset)
+void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, u32
misr_ctrl_offset,
+ bool set_input_sel)
{
u32 config = 0;
@@ -491,6 +492,10 @@ void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map
*c, u32 misr_ctrl_offset)
wmb();
config = MISR_FRAME_COUNT | MISR_CTRL_ENABLE |
MISR_CTRL_FREE_RUN_MASK;
+
+ if (set_input_sel)
+ config |= MISR_CTRL_INPUT_SEL;
+
DPU_REG_WRITE(c, misr_ctrl_offset, config);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index bb496ebe283b..793670d62414 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -17,6 +17,7 @@
#define MISR_CTRL_ENABLE BIT(8)
#define MISR_CTRL_STATUS BIT(9)
#define MISR_CTRL_STATUS_CLEAR BIT(10)
+#define MISR_CTRL_INPUT_SEL BIT(24)
The public apq8916 TRM documents this as a 4-bit field. I think this
was followed into the later generations. Can we please document it
correctly and use an uint instead of just bool for set_input_sel?
Can you pls point us to this document you are referring?
I have this link in my bookmarks, which doesn't seem to work no longer:
https://developer.qualcomm.com/download/sd410/snapdragon-410e-technical-reference-manual.pdf?referrer=node/29241
96boards forum has several links and mentions of this doc.
I was not aware that bit level details are revealed in external
documents :)
Even though its a 4-bit field, it only takes a 0 or 1 as others are
undefined.
Exposing all the bits will only cause more confusion like it did for
others thinking that input select is actually configurable when its not.
I think what we should do is just pass "misr_type" to this API to tell
whether its lm misr or intf misr and set BIT(24) based on that.
This would be another simplification. Can we instead just use values 0
and 1 instead and maybe document that by default everybody should use 0.
#define MISR_CTRL_FREE_RUN_MASK BIT(31)
/*
@@ -357,7 +358,8 @@ void _dpu_hw_setup_qos_lut(struct
dpu_hw_blk_reg_map *c, u32 offset,
bool qos_8lvl,
const struct dpu_hw_qos_cfg *cfg);
-void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, u32
misr_ctrl_offset);
+void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, u32
misr_ctrl_offset,
+ bool set_input_sel);
int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
u32 misr_ctrl_offset,
--
2.43.0
--
With best wishes
[RFT PATCH v2 1/4] drm/msm/dpu: enable writeback on SM8150
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 9392ad2b4d3f..62deedb206b4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -34,6 +34,7 @@ static const struct dpu_mdp_cfg sm8150_mdp = {
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
},
};
@@ -291,6 +292,21 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = {
},
};
+static const struct dpu_wb_cfg sm8150_wb[] = {
+ {
+ .name = "wb_2", .id = WB_2,
+ .base = 0x65000, .len = 0x2c8,
+ .features = WB_SDM845_MASK,
+ .format_list = wb2_formats,
+ .num_formats = ARRAY_SIZE(wb2_formats),
+ .clk_ctrl = DPU_CLK_CTRL_WB2,
+ .xin_id = 6,
+ .vbif_idx = VBIF_RT,
+ .maxlinewidth = 4096,
+ .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+ },
+};
+
static const struct dpu_intf_cfg sm8150_intf[] = {
{
.name = "intf_0", .id = INTF_0,
@@ -385,6 +401,8 @@ const struct dpu_mdss_cfg dpu_sm8150_cfg = {
.pingpong = sm8150_pp,
.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
.merge_3d = sm8150_merge_3d,
+ .wb_count = ARRAY_SIZE(sm8150_wb),
+ .wb = sm8150_wb,
.intf_count = ARRAY_SIZE(sm8150_intf),
.intf = sm8150_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
--
2.39.2
[RFT PATCH v2 3/4] drm/msm/dpu: enable writeback on SM6125
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
index cec7af6667dc..79fca229df18 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
@@ -27,6 +27,7 @@ static const struct dpu_mdp_cfg sm6125_mdp = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
},
};
@@ -139,6 +140,21 @@ static const struct dpu_pingpong_cfg sm6125_pp[] = {
},
};
+static const struct dpu_wb_cfg sm6125_wb[] = {
+ {
+ .name = "wb_2", .id = WB_2,
+ .base = 0x65000, .len = 0x2c8,
+ .features = WB_SDM845_MASK,
+ .format_list = wb2_formats,
+ .num_formats = ARRAY_SIZE(wb2_formats),
+ .clk_ctrl = DPU_CLK_CTRL_WB2,
+ .xin_id = 6,
+ .vbif_idx = VBIF_RT,
+ .maxlinewidth = 2160,
+ .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+ },
+};
+
static const struct dpu_intf_cfg sm6125_intf[] = {
{
.name = "intf_0", .id = INTF_0,
@@ -210,6 +226,8 @@ const struct dpu_mdss_cfg dpu_sm6125_cfg = {
.dspp = sm6125_dspp,
.pingpong_count = ARRAY_SIZE(sm6125_pp),
.pingpong = sm6125_pp,
+ .wb_count = ARRAY_SIZE(sm6125_wb),
+ .wb = sm6125_wb,
.intf_count = ARRAY_SIZE(sm6125_intf),
.intf = sm6125_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
--
2.39.2
[RFT PATCH v2 4/4] drm/msm/dpu: enable writeback on SM6350
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 62db84bd15f2..3c179a73c030 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -27,6 +27,7 @@ static const struct dpu_mdp_cfg sm6350_mdp = {
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
},
};
@@ -146,6 +147,21 @@ static const struct dpu_dsc_cfg sm6350_dsc[] = {
},
};
+static const struct dpu_wb_cfg sm6350_wb[] = {
+ {
+ .name = "wb_2", .id = WB_2,
+ .base = 0x65000, .len = 0x2c8,
+ .features = WB_SM8250_MASK,
+ .format_list = wb2_formats,
+ .num_formats = ARRAY_SIZE(wb2_formats),
+ .clk_ctrl = DPU_CLK_CTRL_WB2,
+ .xin_id = 6,
+ .vbif_idx = VBIF_RT,
+ .maxlinewidth = 1920,
+ .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+ },
+};
+
static const struct dpu_intf_cfg sm6350_intf[] = {
{
.name = "intf_0", .id = INTF_0,
@@ -219,6 +235,8 @@ const struct dpu_mdss_cfg dpu_sm6350_cfg = {
.dsc = sm6350_dsc,
.pingpong_count = ARRAY_SIZE(sm6350_pp),
.pingpong = sm6350_pp,
+ .wb_count = ARRAY_SIZE(sm6350_wb),
+ .wb = sm6350_wb,
.intf_count = ARRAY_SIZE(sm6350_intf),
.intf = sm6350_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
--
2.39.2
[RFT PATCH v2 0/4] drm/msm/dpu: enable writeback on the other platforms
I was not able to test it on my own, this is a call for testing for the owners of these platforms. The git version of modetest now fully supports writeback. Use libdrm >= 2.4.117, run modetest -ac to determine the writeback connector, cat /sys/kernel/debug/dri/0/state to determine spare CRTC and plane, then run something like: modetest -M msm -a -s 36@85:1024x768 -o test.d -P 79@85:1024x768 where 36 is the Writeback connector id, 85 is CRTC and 79 is the plane. Then press Enter and check the test.d file for the raw image dump. Changes since v1: - Fixed the DPU_CLK_CTRL_WB2 definition Dmitry Baryshkov (4): drm/msm/dpu: enable writeback on SM8150 drm/msm/dpu: enable writeback on SC8108X drm/msm/dpu: enable writeback on SM6125 drm/msm/dpu: enable writeback on SM6350 .../drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 18 ++ .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h| 18 ++ .../drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 18 ++ .../drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 18 ++ 4 files changed, 72 insertions(+) -- 2.39.2
[RFT PATCH v2 2/4] drm/msm/dpu: enable writeback on SC8108X
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h| 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 9ffc8804a6fc..d4b531752ec2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -34,6 +34,7 @@ static const struct dpu_mdp_cfg sc8180x_mdp = {
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
},
};
@@ -298,6 +299,21 @@ static const struct dpu_dsc_cfg sc8180x_dsc[] = {
},
};
+static const struct dpu_wb_cfg sc8180x_wb[] = {
+ {
+ .name = "wb_2", .id = WB_2,
+ .base = 0x65000, .len = 0x2c8,
+ .features = WB_SDM845_MASK,
+ .format_list = wb2_formats,
+ .num_formats = ARRAY_SIZE(wb2_formats),
+ .clk_ctrl = DPU_CLK_CTRL_WB2,
+ .xin_id = 6,
+ .vbif_idx = VBIF_RT,
+ .maxlinewidth = 4096,
+ .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+ },
+};
+
static const struct dpu_intf_cfg sc8180x_intf[] = {
{
.name = "intf_0", .id = INTF_0,
@@ -411,6 +427,8 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
.pingpong = sc8180x_pp,
.merge_3d_count = ARRAY_SIZE(sc8180x_merge_3d),
.merge_3d = sc8180x_merge_3d,
+ .wb_count = ARRAY_SIZE(sc8180x_wb),
+ .wb = sc8180x_wb,
.intf_count = ARRAY_SIZE(sc8180x_intf),
.intf = sc8180x_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
--
2.39.2
[PATCH] drm/ci: remove rebase-merge directory
Gitlab runner can cache git repository, including the unfinished rebase
merge status. New CI job will come as a fresh checkout, however this
will not destroy the unfinished rebase, failing our build script.
Destroy the unfinished rebase state.
Suggested-by: David Heidelberg
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/ci/build.sh | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/ci/build.sh b/drivers/gpu/drm/ci/build.sh
index e5c5dcedd108..ca2923ed2290 100644
--- a/drivers/gpu/drm/ci/build.sh
+++ b/drivers/gpu/drm/ci/build.sh
@@ -58,6 +58,9 @@ git config --global user.email "f...@example.com"
git config --global user.name "freedesktop.org CI"
git config --global pull.rebase true
+# cleanup git state on the worker
+rm -rf .git/rebase-merge
+
# Try to merge fixes from target repo
if [ "$(git ls-remote --exit-code --heads ${UPSTREAM_REPO}
${TARGET_BRANCH}-external-fixes)" ]; then
git pull ${UPSTREAM_REPO} ${TARGET_BRANCH}-external-fixes
--
2.39.2
Re: (subset) [PATCH v3 00/12] RB1/QCM2290 features
On Wed, 29 Nov 2023 15:43:57 +0100, Konrad Dybcio wrote: > This series brings: > - interconnect plumbing > - display setup > > for QCM2290/QRB2210 and > > - CAN bus controller > - HDMI display > - wifi fw variant name > > [...] Applied, thanks! [06/12] arm64: dts: qcom: sc7180: Add the missing MDSS icc path commit: 8786398f8686d1a4267ab52f830b25f17e6d62fc [07/12] arm64: dts: qcom: sc7280: Add the missing MDSS icc path commit: c657056d99878c8a8ea84d5d4a9101bcb90b47f2 [08/12] arm64: dts: qcom: qcm2290: Add display nodes commit: a2b32096709dbf4af02675d98356a9d3ad86ff05 [09/12] arm64: dts: qcom: qcm2290: Hook up interconnects commit: 5b970ff0193d67da4a8d2d5fda50dd8ddb50a71e [10/12] arm64: dts: qcom: qrb2210-rb1: Set up HDMI commit: 616eda24edd48b8b56516886c51d211fbfd2679b [11/12] arm64: dts: qcom: qrb2210-rb1: Enable CAN bus controller commit: 252bc7ad359478dba8d77bce9502f2cc7bb547a3 [12/12] arm64: dts: qcom: qrb2210-rb1: add wifi variant property commit: b6a56a5a25d6273729b2b5139d58e3d390318ed2 Best regards, -- Bjorn Andersson
Re: [PATCH] drm/msm/dpu: Add missing safe_lut_tbl in sc8180x catalog
On 01/12/2023 02:35, Bjorn Andersson wrote:
Similar to SC8280XP, the misconfigured SAFE logic causes rather
significant delays in __arm_smmu_tlb_sync(), resulting in poor
performance for things such as USB.
Introduce appropriate SAFE values for SC8180X to correct this.
Fixes: f3af2d6ee9ab ("drm/msm/dpu: Add SC8180x to hw catalog")
Signed-off-by: Bjorn Andersson
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
Re: [PATCH v2 4/6] drm/msm/dsi: add a comment to explain pkt_per_line encoding
On 16/11/2023 20:45, Jonathan Marek wrote:
On 11/15/23 2:38 AM, Dmitry Baryshkov wrote:
On Wed, 15 Nov 2023 at 01:00, Jonathan Marek wrote:
Make it clear why the pkt_per_line value is being "divided by 2".
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 66f198e21a7e..842765063b1b 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -877,6 +877,8 @@ static void dsi_update_dsc_timing(struct
msm_dsi_host *msm_host, bool is_cmd_mod
/* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE
* registers have similar offsets, so for below common code use
* DSI_VIDEO_COMPRESSION_MODE_ for setting bits
+ *
+ * pkt_per_line is log2 encoded, >>1 works for supported
values (1,2,4)
*/
reg |=
DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1);
Should we switch to ffs() or fls() instead?
Just a ffs() on its own can be confusing as well (without the
information that only powers of two are possible), I think like this is
better.
Sounds fair. Could you please then add `if (pkt_per_line > 4)
drm_warn("pkt_per_line too big");`
With that in place:
Reviewed-by: Dmitry Baryshkov
reg |=
DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num);
--
2.26.1
--
With best wishes
Dmitry
[PATCH v4 1/4] drm/msm/mdss: switch mdss to use devm_of_icc_get()
Stop using hand-written reset function for ICC release, use
devm_of_icc_get() instead.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 16 ++--
1 file changed, 2 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 29bb38f0bb2c..53bc496ace99 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -50,14 +50,14 @@ static int msm_mdss_parse_data_bus_icc_path(struct device
*dev,
struct icc_path *path0;
struct icc_path *path1;
- path0 = of_icc_get(dev, "mdp0-mem");
+ path0 = devm_of_icc_get(dev, "mdp0-mem");
if (IS_ERR_OR_NULL(path0))
return PTR_ERR_OR_ZERO(path0);
msm_mdss->path[0] = path0;
msm_mdss->num_paths = 1;
- path1 = of_icc_get(dev, "mdp1-mem");
+ path1 = devm_of_icc_get(dev, "mdp1-mem");
if (!IS_ERR_OR_NULL(path1)) {
msm_mdss->path[1] = path1;
msm_mdss->num_paths++;
@@ -66,15 +66,6 @@ static int msm_mdss_parse_data_bus_icc_path(struct device
*dev,
return 0;
}
-static void msm_mdss_put_icc_path(void *data)
-{
- struct msm_mdss *msm_mdss = data;
- int i;
-
- for (i = 0; i < msm_mdss->num_paths; i++)
- icc_put(msm_mdss->path[i]);
-}
-
static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long
bw)
{
int i;
@@ -391,9 +382,6 @@ static struct msm_mdss *msm_mdss_init(struct
platform_device *pdev, bool is_mdp5
dev_dbg(>dev, "mapped mdss address space @%pK\n", msm_mdss->mmio);
ret = msm_mdss_parse_data_bus_icc_path(>dev, msm_mdss);
- if (ret)
- return ERR_PTR(ret);
- ret = devm_add_action_or_reset(>dev, msm_mdss_put_icc_path,
msm_mdss);
if (ret)
return ERR_PTR(ret);
--
2.39.2
[PATCH v4 3/4] drm/msm/mdss: inline msm_mdss_icc_request_bw()
There are just two places where we set the bandwidth: in the resume and
in the suspend paths. Drop the wrapping function
msm_mdss_icc_request_bw() and call icc_set_bw() directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index e1b208fd072e..eeca281e9d6d 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -66,14 +66,6 @@ static int msm_mdss_parse_data_bus_icc_path(struct device
*dev,
return 0;
}
-static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long
bw)
-{
- int i;
-
- for (i = 0; i < msm_mdss->num_mdp_paths; i++)
- icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw));
-}
-
static void msm_mdss_irq(struct irq_desc *desc)
{
struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc);
@@ -227,14 +219,15 @@ const struct msm_mdss_data *msm_mdss_get_mdss_data(struct
device *dev)
static int msm_mdss_enable(struct msm_mdss *msm_mdss)
{
- int ret;
+ int ret, i;
/*
* Several components have AXI clocks that can only be turned on if
* the interconnect is enabled (non-zero bandwidth). Let's make sure
* that the interconnects are at least at a minimum amount.
*/
- msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW);
+ for (i = 0; i < msm_mdss->num_mdp_paths; i++)
+ icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW));
ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);
if (ret) {
@@ -286,8 +279,12 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
static int msm_mdss_disable(struct msm_mdss *msm_mdss)
{
+ int i;
+
clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks);
- msm_mdss_icc_request_bw(msm_mdss, 0);
+
+ for (i = 0; i < msm_mdss->num_mdp_paths; i++)
+ icc_set_bw(msm_mdss->mdp_path[i], 0, 0);
return 0;
}
--
2.39.2
[PATCH v4 0/4] MDSS reg bus interconnect
Per agreement with Konrad, picked up this patch series. Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect. Gating that path may have a variety of effects. from none to otherwise inexplicable DSI timeouts. This series tries to address the lack of that. Dependencies: [1]. [1] https://patchwork.freedesktop.org/series/126888/ Changes since v3: - Rebased on top of msm-next-lumag / [1] Changes since v2: - Rebased on top of msm/next aka 6.6-rc2, Dropped merged patches. - Dropped the *1000 factor from reg-bus BW values (Konrad). Changes since v1: - Dropped the DPU part, the MDSS vote seems to be enough - Reworked MDSS voting patch. Replaced static bw value with the per-platform confgurable values. - Added sm8450 DT patch. Dmitry Baryshkov (3): drm/msm/mdss: switch mdss to use devm_of_icc_get() drm/msm/mdss: inline msm_mdss_icc_request_bw() drm/msm/mdss: Handle the reg bus ICC path Konrad Dybcio (1): drm/msm/mdss: Rename path references to mdp_path drivers/gpu/drm/msm/msm_mdss.c | 96 +- drivers/gpu/drm/msm/msm_mdss.h | 1 + 2 files changed, 62 insertions(+), 35 deletions(-) -- 2.39.2
[PATCH v4 2/4] drm/msm/mdss: Rename path references to mdp_path
From: Konrad Dybcio
The DPU1 driver needs to handle all MDPn<->DDR paths, as well as
CPU<->SLAVE_DISPLAY_CFG. The former ones share how their values are
calculated, but the latter one has static predefines spanning all SoCs.
In preparation for supporting the CPU<->SLAVE_DISPLAY_CFG path, rename
the path-related struct members to include "mdp_".
Signed-off-by: Konrad Dybcio
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 53bc496ace99..e1b208fd072e 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -40,8 +40,8 @@ struct msm_mdss {
struct irq_domain *domain;
} irq_controller;
const struct msm_mdss_data *mdss_data;
- struct icc_path *path[2];
- u32 num_paths;
+ struct icc_path *mdp_path[2];
+ u32 num_mdp_paths;
};
static int msm_mdss_parse_data_bus_icc_path(struct device *dev,
@@ -54,13 +54,13 @@ static int msm_mdss_parse_data_bus_icc_path(struct device
*dev,
if (IS_ERR_OR_NULL(path0))
return PTR_ERR_OR_ZERO(path0);
- msm_mdss->path[0] = path0;
- msm_mdss->num_paths = 1;
+ msm_mdss->mdp_path[0] = path0;
+ msm_mdss->num_mdp_paths = 1;
path1 = devm_of_icc_get(dev, "mdp1-mem");
if (!IS_ERR_OR_NULL(path1)) {
- msm_mdss->path[1] = path1;
- msm_mdss->num_paths++;
+ msm_mdss->mdp_path[1] = path1;
+ msm_mdss->num_mdp_paths++;
}
return 0;
@@ -70,8 +70,8 @@ static void msm_mdss_icc_request_bw(struct msm_mdss
*msm_mdss, unsigned long bw)
{
int i;
- for (i = 0; i < msm_mdss->num_paths; i++)
- icc_set_bw(msm_mdss->path[i], 0, Bps_to_icc(bw));
+ for (i = 0; i < msm_mdss->num_mdp_paths; i++)
+ icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(bw));
}
static void msm_mdss_irq(struct irq_desc *desc)
--
2.39.2
[PATCH v4 4/4] drm/msm/mdss: Handle the reg bus ICC path
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
another path that needs to be handled to ensure MDSS functions properly,
namely the "reg bus", a.k.a the CPU-MDSS interconnect.
Gating that path may have a variety of effects, from none to otherwise
inexplicable DSI timeouts.
Provide a way for MDSS driver to vote on this bus.
A note regarding vote values. Newer platforms have corresponding
bandwidth values in the vendor DT files. For the older platforms there
was a static vote in the mdss_mdp and rotator drivers. I choose to be
conservative here and choose this value as a default.
Co-developed-by: Konrad Dybcio
Signed-off-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_mdss.c | 49 +++---
drivers/gpu/drm/msm/msm_mdss.h | 1 +
2 files changed, 46 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index eeca281e9d6d..18b07619d6fc 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -28,6 +28,8 @@
#define MIN_IB_BW 4UL /* Min ib vote 400MB */
+#define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */
+
struct msm_mdss {
struct device *dev;
@@ -42,6 +44,7 @@ struct msm_mdss {
const struct msm_mdss_data *mdss_data;
struct icc_path *mdp_path[2];
u32 num_mdp_paths;
+ struct icc_path *reg_bus_path;
};
static int msm_mdss_parse_data_bus_icc_path(struct device *dev,
@@ -49,6 +52,7 @@ static int msm_mdss_parse_data_bus_icc_path(struct device
*dev,
{
struct icc_path *path0;
struct icc_path *path1;
+ struct icc_path *reg_bus_path;
path0 = devm_of_icc_get(dev, "mdp0-mem");
if (IS_ERR_OR_NULL(path0))
@@ -63,6 +67,10 @@ static int msm_mdss_parse_data_bus_icc_path(struct device
*dev,
msm_mdss->num_mdp_paths++;
}
+ reg_bus_path = of_icc_get(dev, "cpu-cfg");
+ if (!IS_ERR_OR_NULL(reg_bus_path))
+ msm_mdss->reg_bus_path = reg_bus_path;
+
return 0;
}
@@ -229,6 +237,13 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
for (i = 0; i < msm_mdss->num_mdp_paths; i++)
icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW));
+ if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw)
+ icc_set_bw(msm_mdss->reg_bus_path, 0,
+ msm_mdss->mdss_data->reg_bus_bw);
+ else
+ icc_set_bw(msm_mdss->reg_bus_path, 0,
+ DEFAULT_REG_BW);
+
ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);
if (ret) {
dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret);
@@ -286,6 +301,9 @@ static int msm_mdss_disable(struct msm_mdss *msm_mdss)
for (i = 0; i < msm_mdss->num_mdp_paths; i++)
icc_set_bw(msm_mdss->mdp_path[i], 0, 0);
+ if (msm_mdss->reg_bus_path)
+ icc_set_bw(msm_mdss->reg_bus_path, 0, 0);
+
return 0;
}
@@ -372,6 +390,8 @@ static struct msm_mdss *msm_mdss_init(struct
platform_device *pdev, bool is_mdp5
if (!msm_mdss)
return ERR_PTR(-ENOMEM);
+ msm_mdss->mdss_data = of_device_get_match_data(>dev);
+
msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ?
"mdss_phys" : "mdss");
if (IS_ERR(msm_mdss->mmio))
return ERR_CAST(msm_mdss->mmio);
@@ -462,8 +482,6 @@ static int mdss_probe(struct platform_device *pdev)
if (IS_ERR(mdss))
return PTR_ERR(mdss);
- mdss->mdss_data = of_device_get_match_data(>dev);
-
platform_set_drvdata(pdev, mdss);
/*
@@ -495,11 +513,13 @@ static const struct msm_mdss_data msm8998_data = {
.ubwc_enc_version = UBWC_1_0,
.ubwc_dec_version = UBWC_1_0,
.highest_bank_bit = 2,
+ .reg_bus_bw = 76800,
};
static const struct msm_mdss_data qcm2290_data = {
/* no UBWC */
.highest_bank_bit = 0x2,
+ .reg_bus_bw = 76800,
};
static const struct msm_mdss_data sc7180_data = {
@@ -507,6 +527,7 @@ static const struct msm_mdss_data sc7180_data = {
.ubwc_dec_version = UBWC_2_0,
.ubwc_static = 0x1e,
.highest_bank_bit = 0x3,
+ .reg_bus_bw = 76800,
};
static const struct msm_mdss_data sc7280_data = {
@@ -516,6 +537,7 @@ static const struct msm_mdss_data sc7280_data = {
.ubwc_static = 1,
.highest_bank_bit = 1,
.macrotile_mode = 1,
+ .reg_bus_bw = 74000,
};
static const struct msm_mdss_data sc8180x_data = {
@@ -523,6 +545,7 @@ static const struct msm_mdss_data sc8180x_data = {
.ubwc_dec_version = UBWC_3_0,
.highest_bank_bit = 3,
.macrotile_mode = 1,
+ .reg_bus_bw = 76800,
};
static const struct msm_mdss_data sc8280xp_data = {
@@ -532,12 +555,14 @@ static const struct msm_mdss_data sc8280xp_data
[PATCH v3] drm/msm/dsi: Document DSC related pclk_rate and hdisplay calculations
Provide actual documentation for the pclk and hdisplay calculations in
the case of DSC compression being used.
Signed-off-by: Dmitry Baryshkov
---
Changes since v2:
- Followed suggestion by Abhinav and Marijn to improve documentatry
comments.
Changes since v1:
- Converted dsi_adjust_pclk_for_compression() into kerneldoc (Marijn)
- Added a pointer from dsi_timing_setup() docs to
dsi_adjust_pclk_for_compression() (Marijn)
- Fixed two typo (Marijn)
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 33 --
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index deeecdfd6c4e..d60ad796527c 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -529,6 +529,25 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
clk_disable_unprepare(msm_host->byte_clk);
}
+/**
+ * dsi_adjust_pclk_for_compression() - Adjust the pclk rate for compression
case
+ * @mode: The selected mode for the DSI output
+ * @dsc: DRM DSC configuration for this DSI output
+ *
+ * Adjust the pclk rate by calculating a new hdisplay proportional to
+ * the compression ratio such that:
+ * new_hdisplay = old_hdisplay * compressed_bpp / uncompressed_bpp
+ *
+ * Porches do not need to be adjusted:
+ * - For VIDEO mode they are not compressed by DSC and are passed as is.
+ * - For CMD mode there are no actual porches. Instead these fields
+ * currently represent the overhead to the image data transfer. As such, they
+ * are calculated for the final mode parameters (after the compression) and
+ * are not to be adjusted too.
+ *
+ * FIXME: Reconsider this if/when CMD mode handling is rewritten to use
+ * refresh rate and data overhead as a starting point of the calculations.
+ */
static unsigned long dsi_adjust_pclk_for_compression(const struct
drm_display_mode *mode,
const struct drm_dsc_config *dsc)
{
@@ -951,8 +970,18 @@ static void dsi_timing_setup(struct msm_dsi_host
*msm_host, bool is_bonded_dsi)
if (ret)
return;
- /* Divide the display by 3 but keep back/font porch and
-* pulse width same
+ /*
+* DPU sends 3 bytes per pclk cycle to DSI. If widebus is
+* enabled, bus width is extended to 6 bytes.
+*
+* Calculate the number of pclks needed to transmit one line of
+* the compressed data.
+
+* The back/font porch and pulse width are kept intact. For
+* VIDEO mode they represent timing parameters rather than
+* actual data transfer, see the documentation for
+* dsi_adjust_pclk_for_compression(). For CMD mode they are
+* unused anyway.
*/
h_total -= hdisplay;
if (wide_bus_enabled && !(msm_host->mode_flags &
MIPI_DSI_MODE_VIDEO))
--
2.39.2
[PATCH RESEND 4/5] drm/msm/mdp5: migrate SMP dumping to using atomic_print_state
The Shared Memory Pool (SMP) state is a part of the MDP5's private
object state. Use existing infrastructure, atomic_print_state()
callback, to dump SMP state (which also makes it included into
debugfs/dri/N/state). This allows us to drop the custom debugfs file
too.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c | 2 --
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 46 ++--
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c | 12 ++-
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h | 4 ++-
4 files changed, 15 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c
index 43443a435d59..b40ed3a847c8 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c
@@ -31,8 +31,6 @@ static void mdp5_irq_error_handler(struct mdp_irq *irq,
uint32_t irqstatus)
if (dumpstate && __ratelimit()) {
struct drm_printer p = drm_info_printer(mdp5_kms->dev->dev);
drm_state_dump(mdp5_kms->dev, );
- if (mdp5_kms->smp)
- mdp5_smp_dump(mdp5_kms->smp, );
}
}
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index ec933d597e20..cd46c2b0ec0c 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -119,9 +119,19 @@ static void mdp5_global_destroy_state(struct
drm_private_obj *obj,
kfree(mdp5_state);
}
+static void mdp5_global_print_state(struct drm_printer *p,
+ const struct drm_private_state *state)
+{
+ struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state);
+
+ if (mdp5_state->mdp5_kms->smp)
+ mdp5_smp_dump(mdp5_state->mdp5_kms->smp, p, mdp5_state);
+}
+
static const struct drm_private_state_funcs mdp5_global_state_funcs = {
.atomic_duplicate_state = mdp5_global_duplicate_state,
.atomic_destroy_state = mdp5_global_destroy_state,
+ .atomic_print_state = mdp5_global_print_state,
};
static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms)
@@ -226,39 +236,6 @@ static void mdp5_kms_destroy(struct msm_kms *kms)
mdp5_destroy(mdp5_kms);
}
-#ifdef CONFIG_DEBUG_FS
-static int smp_show(struct seq_file *m, void *arg)
-{
- struct drm_info_node *node = m->private;
- struct drm_device *dev = node->minor->dev;
- struct msm_drm_private *priv = dev->dev_private;
- struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
- struct drm_printer p = drm_seq_file_printer(m);
-
- if (!mdp5_kms->smp) {
- drm_printf(, "no SMP pool\n");
- return 0;
- }
-
- mdp5_smp_dump(mdp5_kms->smp, );
-
- return 0;
-}
-
-static struct drm_info_list mdp5_debugfs_list[] = {
- {"smp", smp_show },
-};
-
-static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
-{
- drm_debugfs_create_files(mdp5_debugfs_list,
-ARRAY_SIZE(mdp5_debugfs_list),
-minor->debugfs_root, minor);
-
- return 0;
-}
-#endif
-
static const struct mdp_kms_funcs kms_funcs = {
.base = {
.hw_init = mdp5_hw_init,
@@ -277,9 +254,6 @@ static const struct mdp_kms_funcs kms_funcs = {
.get_format = mdp_get_format,
.set_split_display = mdp5_set_split_display,
.destroy = mdp5_kms_destroy,
-#ifdef CONFIG_DEBUG_FS
- .debugfs_init= mdp5_kms_debugfs_init,
-#endif
},
.set_irqmask = mdp5_set_irqmask,
};
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
index b68682c1b5bc..ab5e3ba5aa2f 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
@@ -325,22 +325,17 @@ void mdp5_smp_complete_commit(struct mdp5_smp *smp,
struct mdp5_smp_state *state
state->released = 0;
}
-void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p)
+void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p,
+ struct mdp5_global_state *global_state)
{
struct mdp5_kms *mdp5_kms = get_kms(smp);
struct mdp5_hw_pipe_state *hwpstate;
struct mdp5_smp_state *state;
- struct mdp5_global_state *global_state;
int total = 0, i, j;
drm_printf(p, "name\tinuse\tplane\n");
drm_printf(p, "\t-\t-\n");
- if (drm_can_sleep())
- drm_modeset_lock(_kms->glob_state_lock, NULL);
-
- global_state = mdp5_get_existing_global_state(mdp5_kms);
-
/* grab these *after* we hold the state_lock */
hwpstate = _state->hwpipe;
state = _state->smp;
@@ -365,9 +360,6 @@ void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer
*p)
drm_printf(p,
[PATCH RESEND 5/5] drm/msm/mdp5: drop global_state_lock
Since the commit b962a12050a3 ("drm/atomic: integrate modeset lock with
private objects") the DRM framework no longer requires the external
lock for private objects. Drop the lock, letting the DRM to manage
private object locking.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 8
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h | 1 -
2 files changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index cd46c2b0ec0c..b1d2f00974d5 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -84,11 +84,6 @@ struct mdp5_global_state *mdp5_get_global_state(struct
drm_atomic_state *s)
struct msm_drm_private *priv = s->dev->dev_private;
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
struct drm_private_state *priv_state;
- int ret;
-
- ret = drm_modeset_lock(_kms->glob_state_lock, s->acquire_ctx);
- if (ret)
- return ERR_PTR(ret);
priv_state = drm_atomic_get_private_obj_state(s, _kms->glob_state);
if (IS_ERR(priv_state))
@@ -138,8 +133,6 @@ static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms)
{
struct mdp5_global_state *state;
- drm_modeset_lock_init(_kms->glob_state_lock);
-
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return -ENOMEM;
@@ -613,7 +606,6 @@ static void mdp5_destroy(struct mdp5_kms *mdp5_kms)
pm_runtime_disable(_kms->pdev->dev);
drm_atomic_private_obj_fini(_kms->glob_state);
- drm_modeset_lock_fini(_kms->glob_state_lock);
}
static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
index 29bf11f08601..70fdc0b6c7c5 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
@@ -40,7 +40,6 @@ struct mdp5_kms {
* Global private object state, Do not access directly, use
* mdp5_global_get_state()
*/
- struct drm_modeset_lock glob_state_lock;
struct drm_private_obj glob_state;
struct mdp5_smp *smp;
--
2.39.2
[PATCH RESEND 0/5] drm/msm: cleanup private obj handling
Note: I'm resending this patch series as I haven't got any feedback from
the drm core maintainers to the first patch.
While debugging one of the features in DRM/MSM I noticed that MSM
subdrivers still wrap private object access with manual modeset locking.
Since commit b962a12050a3 ("drm/atomic: integrate modeset lock with
private objects") this is no longer required, as the DRM framework
handles private objects internally. Drop these custom locks, while also
cleaning up the surrounding code.
Dmitry Baryshkov (5):
drm/atomic: add private obj state to state dump
drm/msm/dpu: finalise global state object
drm/msm/dpu: drop global_state_lock
drm/msm/mdp5: migrate SMP dumping to using atomic_print_state
drm/msm/mdp5: drop global_state_lock
drivers/gpu/drm/drm_atomic.c | 9
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 14 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 -
drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c | 2 -
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 54 +---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h | 1 -
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c | 12 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h | 4 +-
8 files changed, 31 insertions(+), 66 deletions(-)
--
2.39.2
[PATCH RESEND 3/5] drm/msm/dpu: drop global_state_lock
Since the commit b962a12050a3 ("drm/atomic: integrate modeset lock with
private objects") the DRM framework no longer requires the external
lock for private objects. Drop the lock, letting the DRM to manage
private object locking.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 -
2 files changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 73f70e67cfef..26ac00f8f486 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -328,11 +328,6 @@ struct dpu_global_state *dpu_kms_get_global_state(struct
drm_atomic_state *s)
struct msm_drm_private *priv = s->dev->dev_private;
struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
struct drm_private_state *priv_state;
- int ret;
-
- ret = drm_modeset_lock(_kms->global_state_lock, s->acquire_ctx);
- if (ret)
- return ERR_PTR(ret);
priv_state = drm_atomic_get_private_obj_state(s,
_kms->global_state);
@@ -373,8 +368,6 @@ static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)
{
struct dpu_global_state *state;
- drm_modeset_lock_init(_kms->global_state_lock);
-
state = kzalloc(sizeof(*state), GFP_KERNEL);
if (!state)
return -ENOMEM;
@@ -388,7 +381,6 @@ static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)
static void dpu_kms_global_obj_fini(struct dpu_kms *dpu_kms)
{
drm_atomic_private_obj_fini(_kms->global_state);
- drm_modeset_lock_fini(_kms->global_state_lock);
}
static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index b6f53ca6e962..ed549f0f7c65 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -84,7 +84,6 @@ struct dpu_kms {
* Global private object state, Do not access directly, use
* dpu_kms_global_get_state()
*/
- struct drm_modeset_lock global_state_lock;
struct drm_private_obj global_state;
struct dpu_rm rm;
--
2.39.2
[PATCH RESEND 1/5] drm/atomic: add private obj state to state dump
The drm_atomic_print_new_state() already prints private object state via
drm_atomic_private_obj_print_state(). Add private object state dumping
to __drm_state_dump(), so that it is also included into drm_state_dump()
output and into debugfs/dri/N/state file.
Reviewed-by: Rob Clark
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/drm_atomic.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index f1a503aafe5a..c31fc0b48c31 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -1773,6 +1773,7 @@ static void __drm_state_dump(struct drm_device *dev,
struct drm_printer *p,
struct drm_crtc *crtc;
struct drm_connector *connector;
struct drm_connector_list_iter conn_iter;
+ struct drm_private_obj *obj;
if (!drm_drv_uses_atomic_modeset(dev))
return;
@@ -1801,6 +1802,14 @@ static void __drm_state_dump(struct drm_device *dev,
struct drm_printer *p,
if (take_locks)
drm_modeset_unlock(>mode_config.connection_mutex);
drm_connector_list_iter_end(_iter);
+
+ list_for_each_entry(obj, >privobj_list, head) {
+ if (take_locks)
+ drm_modeset_lock(>lock, NULL);
+ drm_atomic_private_obj_print_state(p, obj->state);
+ if (take_locks)
+ drm_modeset_unlock(>lock);
+ }
}
/**
--
2.39.2
[PATCH v2 1/3] drm/msm/dpu: enable writeback on SDM845
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 18 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 --
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 38ac0c1a134b..d44e00fd898d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -34,6 +34,7 @@ static const struct dpu_mdp_cfg sdm845_mdp = {
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
},
};
@@ -251,6 +252,21 @@ static const struct dpu_dsc_cfg sdm845_dsc[] = {
},
};
+static const struct dpu_wb_cfg sdm845_wb[] = {
+ {
+ .name = "wb_2", .id = WB_2,
+ .base = 0x65000, .len = 0x2c8,
+ .features = WB_SDM845_MASK,
+ .format_list = wb2_formats,
+ .num_formats = ARRAY_SIZE(wb2_formats),
+ .clk_ctrl = DPU_CLK_CTRL_WB2,
+ .xin_id = 6,
+ .vbif_idx = VBIF_RT,
+ .maxlinewidth = 4096,
+ .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+ },
+};
+
static const struct dpu_intf_cfg sdm845_intf[] = {
{
.name = "intf_0", .id = INTF_0,
@@ -344,6 +360,8 @@ const struct dpu_mdss_cfg dpu_sdm845_cfg = {
.pingpong = sdm845_pp,
.dsc_count = ARRAY_SIZE(sdm845_dsc),
.dsc = sdm845_dsc,
+ .wb_count = ARRAY_SIZE(sdm845_wb),
+ .wb = sdm845_wb,
.intf_count = ARRAY_SIZE(sdm845_intf),
.intf = sdm845_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index a1aada630780..1b71fa3ebe73 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -105,14 +105,16 @@
#define INTF_SC7280_MASK (INTF_SC7180_MASK)
-#define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
+#define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
BIT(DPU_WB_UBWC) | \
BIT(DPU_WB_YUV_CONFIG) | \
BIT(DPU_WB_PIPE_ALPHA) | \
BIT(DPU_WB_XY_ROI_OFFSET) | \
BIT(DPU_WB_QOS) | \
BIT(DPU_WB_QOS_8LVL) | \
-BIT(DPU_WB_CDP) | \
+BIT(DPU_WB_CDP))
+
+#define WB_SM8250_MASK (WB_SDM845_MASK | \
BIT(DPU_WB_INPUT_CTRL))
#define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
--
2.39.2
[PATCH v2 3/3] drm/msm/dpu: enable writeback on SM8450
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index d18145c226da..413c0b1f4ad3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -32,6 +32,7 @@ static const struct dpu_mdp_cfg sm8450_mdp = {
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
},
};
@@ -316,6 +317,21 @@ static const struct dpu_dsc_cfg sm8450_dsc[] = {
},
};
+static const struct dpu_wb_cfg sm8450_wb[] = {
+ {
+ .name = "wb_2", .id = WB_2,
+ .base = 0x65000, .len = 0x2c8,
+ .features = WB_SM8250_MASK,
+ .format_list = wb2_formats,
+ .num_formats = ARRAY_SIZE(wb2_formats),
+ .clk_ctrl = DPU_CLK_CTRL_WB2,
+ .xin_id = 6,
+ .vbif_idx = VBIF_RT,
+ .maxlinewidth = 4096,
+ .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+ },
+};
+
static const struct dpu_intf_cfg sm8450_intf[] = {
{
.name = "intf_0", .id = INTF_0,
@@ -411,6 +427,8 @@ const struct dpu_mdss_cfg dpu_sm8450_cfg = {
.dsc = sm8450_dsc,
.merge_3d_count = ARRAY_SIZE(sm8450_merge_3d),
.merge_3d = sm8450_merge_3d,
+ .wb_count = ARRAY_SIZE(sm8450_wb),
+ .wb = sm8450_wb,
.intf_count = ARRAY_SIZE(sm8450_intf),
.intf = sm8450_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
--
2.39.2
[PATCH v2 0/3] drm/msm/dpu: enable writeback on several platforms
This enables writeback on several platforms where I could actually test it. Changes since v1: - Fixed the CLK_CTRL for SDM845 platform. Dmitry Baryshkov (3): drm/msm/dpu: enable writeback on SDM845 drm/msm/dpu: enable writeback on SM8350 drm/msm/dpu: enable writeback on SM8450 .../drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 18 ++ .../drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 18 ++ .../drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 18 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 -- 4 files changed, 58 insertions(+), 2 deletions(-) -- 2.39.2
[PATCH v2 2/3] drm/msm/dpu: enable writeback on SM8350
Enable WB2 hardware block, enabling writeback support on this platform.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 5aaa24281906..610984d89a9a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -31,6 +31,7 @@ static const struct dpu_mdp_cfg sm8350_mdp = {
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
},
};
@@ -298,6 +299,21 @@ static const struct dpu_dsc_cfg sm8350_dsc[] = {
},
};
+static const struct dpu_wb_cfg sm8350_wb[] = {
+ {
+ .name = "wb_2", .id = WB_2,
+ .base = 0x65000, .len = 0x2c8,
+ .features = WB_SM8250_MASK,
+ .format_list = wb2_formats,
+ .num_formats = ARRAY_SIZE(wb2_formats),
+ .clk_ctrl = DPU_CLK_CTRL_WB2,
+ .xin_id = 6,
+ .vbif_idx = VBIF_RT,
+ .maxlinewidth = 4096,
+ .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+ },
+};
+
static const struct dpu_intf_cfg sm8350_intf[] = {
{
.name = "intf_0", .id = INTF_0,
@@ -393,6 +409,8 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = {
.dsc = sm8350_dsc,
.merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
.merge_3d = sm8350_merge_3d,
+ .wb_count = ARRAY_SIZE(sm8350_wb),
+ .wb = sm8350_wb,
.intf_count = ARRAY_SIZE(sm8350_intf),
.intf = sm8350_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
--
2.39.2
[PATCH 04/12] drm/msm: add arrays listing formats supported by MDP4/MDP5 hardware
MDP4 and MDP5 drivers enumerate supported formats each time the plane is
created. In preparation to merger of MDP DPU format databases, define
precise formats list, so that changes to the database do not cause the
driver to add unsupported format to the list.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 57 --
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 36 +++---
drivers/gpu/drm/msm/disp/mdp_format.c | 28 ---
drivers/gpu/drm/msm/disp/mdp_kms.h | 1 -
4 files changed, 80 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
index b689b618da78..cebe20c82a54 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
@@ -371,6 +371,47 @@ static const uint64_t supported_format_modifiers[] = {
DRM_FORMAT_MOD_INVALID
};
+const uint32_t mdp4_rgb_formats[] = {
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_RGBA,
+ DRM_FORMAT_BGRA,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_RGBX,
+ DRM_FORMAT_BGRX,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+};
+
+const uint32_t mdp4_rgb_yuv_formats[] = {
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_RGBA,
+ DRM_FORMAT_BGRA,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_RGBX,
+ DRM_FORMAT_BGRX,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_NV21,
+ DRM_FORMAT_NV16,
+ DRM_FORMAT_NV61,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_YUV420,
+ DRM_FORMAT_YVU420,
+};
+
/* initialize plane */
struct drm_plane *mdp4_plane_init(struct drm_device *dev,
enum mdp4_pipe pipe_id, bool private_plane)
@@ -379,6 +420,8 @@ struct drm_plane *mdp4_plane_init(struct drm_device *dev,
struct mdp4_plane *mdp4_plane;
int ret;
enum drm_plane_type type;
+ const uint32_t *formats;
+ unsigned int nformats;
mdp4_plane = kzalloc(sizeof(*mdp4_plane), GFP_KERNEL);
if (!mdp4_plane) {
@@ -392,13 +435,17 @@ struct drm_plane *mdp4_plane_init(struct drm_device *dev,
mdp4_plane->name = pipe_names[pipe_id];
mdp4_plane->caps = mdp4_pipe_caps(pipe_id);
- mdp4_plane->nformats = mdp_get_formats(mdp4_plane->formats,
- ARRAY_SIZE(mdp4_plane->formats),
- !pipe_supports_yuv(mdp4_plane->caps));
-
type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
+
+ if (pipe_supports_yuv(mdp4_plane->caps)) {
+ formats = mdp4_rgb_yuv_formats;
+ nformats = ARRAY_SIZE(mdp4_rgb_yuv_formats);
+ } else {
+ formats = mdp4_rgb_formats;
+ nformats = ARRAY_SIZE(mdp4_rgb_formats);
+ }
ret = drm_universal_plane_init(dev, plane, 0xff, _plane_funcs,
-mdp4_plane->formats, mdp4_plane->nformats,
+formats, nformats,
supported_format_modifiers, type, NULL);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
index 0d5ff03cb091..aa8342d93393 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
@@ -17,9 +17,6 @@
struct mdp5_plane {
struct drm_plane base;
-
- uint32_t nformats;
- uint32_t formats[32];
};
#define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
@@ -1007,6 +1004,32 @@ uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
return mask;
}
+const uint32_t mdp5_plane_formats[] = {
+ DRM_FORMAT_ARGB,
+ DRM_FORMAT_ABGR,
+ DRM_FORMAT_RGBA,
+ DRM_FORMAT_BGRA,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_RGBX,
+ DRM_FORMAT_BGRX,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_NV21,
+ DRM_FORMAT_NV16,
+ DRM_FORMAT_NV61,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_YUV420,
+ DRM_FORMAT_YVU420,
+};
+
/* initialize plane */
struct drm_plane *mdp5_plane_init(struct drm_device *dev,
enum drm_plane_type type)
@@ -1023,12 +1046,9 @@ struct drm_plane *mdp5_plane_init(struct drm_device *dev,
plane = _plane->base;
- mdp5_plane->nformats =
[PATCH 07/12] drm/msm: merge dpu_format and mdp_format in struct msm_format
Structures dpu_format and mdp_format are largely the same structures.
In order to remove duplication between format databases, merge these two
stucture definitions into the global struct msm_format.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 184 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 10 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 41 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 30 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 14 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 16 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 74 +++
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 4 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c| 26 +--
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 7 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c| 54 ++---
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c | 4 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h | 2 +-
drivers/gpu/drm/msm/disp/mdp_format.c | 28 ++-
drivers/gpu/drm/msm/disp/mdp_kms.h| 13 --
drivers/gpu/drm/msm/msm_drv.h | 28 +++
24 files changed, 279 insertions(+), 288 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 3c475f8042b0..9041b0d71b25 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -331,7 +331,7 @@ static bool dpu_crtc_get_scanout_position(struct drm_crtc
*crtc,
}
static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
- struct dpu_plane_state *pstate, struct dpu_format *format)
+ struct dpu_plane_state *pstate, const struct msm_format *format)
{
struct dpu_hw_mixer *lm = mixer->hw_lm;
uint32_t blend_op;
@@ -374,7 +374,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer
*mixer,
fg_alpha, bg_alpha, blend_op);
DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
- >base.pixel_format, format->alpha_enable, blend_op);
+ >pixel_format, format->alpha_enable, blend_op);
}
static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
@@ -406,7 +406,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc
*crtc,
struct dpu_crtc_mixer *mixer,
u32 num_mixers,
enum dpu_stage stage,
- struct dpu_format *format,
+ const struct msm_format *format,
uint64_t modifier,
struct dpu_sw_pipe *pipe,
unsigned int stage_idx,
@@ -423,7 +423,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc
*crtc,
trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
state, to_dpu_plane_state(state), stage_idx,
- format->base.pixel_format,
+ format->pixel_format,
modifier);
DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d
multirect_idx %d\n",
@@ -451,7 +451,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
struct drm_plane_state *state;
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
struct dpu_plane_state *pstate = NULL;
- struct dpu_format *format;
+ const struct msm_format *format;
struct dpu_hw_ctl *ctl = mixer->lm_ctl;
uint32_t lm_idx;
@@ -470,7 +470,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
pstate = to_dpu_plane_state(state);
fb = state->fb;
- format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
+ format = msm_framebuffer_format(pstate->base.fb);
if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
bg_alpha_enable = true;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index a01fda711883..35aaead897e1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -232,7 +232,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
{
[PATCH 03/12] drm/msm/dpu: use format-related definitions from mdp_common.xml.h
Instead of having DPU-specific defines, switch to the definitions from
the mdp_common.xml.h file. This is the preparation for merged of DPU and
MDP format tables.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 290 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 64 +---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 12 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +-
6 files changed, 164 insertions(+), 214 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 0b6a761d68b7..4fead04d83a0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -640,7 +640,7 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct
dpu_encoder_phys *phys_enc
wb_cfg->dest.height = job->fb->height;
wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
- if ((wb_cfg->dest.format->fetch_planes == DPU_PLANE_PLANAR) &&
+ if ((wb_cfg->dest.format->fetch_planes == MDP_PLANE_PLANAR) &&
(wb_cfg->dest.format->element[0] == C1_B_Cb))
swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index e366ab134249..05e82f5dd0e6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -35,11 +35,11 @@
bp, flg, fm, np) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_INTERLEAVED,\
+ .fetch_planes = MDP_PLANE_INTERLEAVED,\
.alpha_enable = alpha,\
.element = { (e0), (e1), (e2), (e3) },\
.bits = { g, b, r, a }, \
- .chroma_sample = DPU_CHROMA_RGB, \
+ .chroma_sample = CHROMA_FULL, \
.unpack_align_msb = 0,\
.unpack_tight = 1,\
.unpack_count = uc, \
@@ -54,11 +54,11 @@ bp, flg, fm, np)
\
alpha, bp, flg, fm, np, th) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_INTERLEAVED,\
+ .fetch_planes = MDP_PLANE_INTERLEAVED,\
.alpha_enable = alpha,\
.element = { (e0), (e1), (e2), (e3) },\
.bits = { g, b, r, a }, \
- .chroma_sample = DPU_CHROMA_RGB, \
+ .chroma_sample = CHROMA_FULL, \
.unpack_align_msb = 0,\
.unpack_tight = 1,\
.unpack_count = uc, \
@@ -74,7 +74,7 @@ alpha, bp, flg, fm, np, th)
\
alpha, chroma, count, bp, flg, fm, np)\
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_INTERLEAVED,\
+ .fetch_planes = MDP_PLANE_INTERLEAVED,\
.alpha_enable = alpha,\
.element = { (e0), (e1), (e2), (e3)}, \
.bits = { g, b, r, a }, \
@@ -92,7 +92,7 @@ alpha, chroma, count, bp, flg, fm, np)
\
#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
{ \
.base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
+ .fetch_planes = MDP_PLANE_PSEUDO_PLANAR, \
.alpha_enable = false,\
[PATCH 05/12] drm/msm/dpu: in dpu_format replace bitmap with unsigned long field
Using bitmap for the flags results in a clumsy syntax on test_bit,
replace it with unsigned long type and simple binary ops.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 18 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 16 +++-
2 files changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index 05e82f5dd0e6..3112d85808c7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -45,7 +45,7 @@ bp, flg, fm, np)
\
.unpack_count = uc, \
.bpp = bp,\
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT\
}
@@ -64,7 +64,7 @@ alpha, bp, flg, fm, np, th)
\
.unpack_count = uc, \
.bpp = bp,\
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -84,7 +84,7 @@ alpha, chroma, count, bp, flg, fm, np)
\
.unpack_count = count,\
.bpp = bp,\
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT\
}
@@ -102,7 +102,7 @@ alpha, chroma, count, bp, flg, fm, np)
\
.unpack_count = 2,\
.bpp = 2, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT\
}
@@ -121,7 +121,7 @@ flg, fm, np, th)
\
.unpack_count = 2,\
.bpp = 2, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th \
}
@@ -139,7 +139,7 @@ flg, fm, np, th)
\
.unpack_count = 2,\
.bpp = 2, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT\
}
@@ -158,7 +158,7 @@ flg, fm, np, th)
\
.unpack_count = 2,\
.bpp = 2, \
.fetch_mode = fm, \
- .flag = {(flg)}, \
+ .flags = flg, \
.num_planes = np, \
.tile_height = th
[PATCH 02/12] drm/msm/disp: add mdp_fetch_mode enum
Pull in new enum from the mesa registers. This commit should be replaced
with the registers sync with Mesa instead.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp_common.xml.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/mdp_common.xml.h
b/drivers/gpu/drm/msm/disp/mdp_common.xml.h
index 5220688727e4..2fa333bab3d2 100644
--- a/drivers/gpu/drm/msm/disp/mdp_common.xml.h
+++ b/drivers/gpu/drm/msm/disp/mdp_common.xml.h
@@ -107,5 +107,11 @@ enum mdp_bpc_alpha {
BPC8A = 3,
};
+enum mdp_fetch_mode {
+ MDP_FETCH_LINEAR = 0,
+ MDP_FETCH_TILE = 1,
+ MDP_FETCH_UBWC = 2,
+};
+
#endif /* MDP_COMMON_XML */
--
2.39.2
[PATCH 00/12] drm/msm: fold dpu_format into mdp_formats database
During the review of [1] Abhinav pointed out that mdp_rgb_formats and mdp_rgb_yuv_formats arrays from patch 1 are directly based on the struct mdp_format formats array. This was true, because MDP4 / MDP5 drivers used their own (small) list of supported formats. The DPU driver, supporting more formats, had larger database of the formats and their properties. While we don't have plans to expand MDP5 formats support, it make sense to merge these two databases into a common dataset. [1] https://patchwork.freedesktop.org/series/120377/ Dmitry Baryshkov (12): drm/msm: fix BPC1 -> BPC4 drm/msm/disp: add mdp_fetch_mode enum drm/msm/dpu: use format-related definitions from mdp_common.xml.h drm/msm: add arrays listing formats supported by MDP4/MDP5 hardware drm/msm/dpu: in dpu_format replace bitmap with unsigned long field drm/msm/dpu: pull format flag definitions to msm_drv.h drm/msm: merge dpu_format and mdp_format in struct msm_format drm/msm: convert msm_format::unpack_tight to the flag drm/msm: convert msm_format::unpack_align_msb to the flag drm/msm: convert msm_format::alpha_enable to the flag drm/msm: merge dpu format database to MDP formats drm/msm: drop msm_kms_funcs::get_format() callback drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 22 +- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 +- .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 658 +- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 23 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 16 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 123 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 45 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 17 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 22 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 75 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 6 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 1 - drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c| 89 ++- drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 16 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 1 - drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c| 98 ++- drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c | 4 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h | 2 +- drivers/gpu/drm/msm/disp/mdp_common.xml.h | 8 +- drivers/gpu/drm/msm/disp/mdp_format.c | 611 +--- drivers/gpu/drm/msm/disp/mdp_kms.h| 17 - drivers/gpu/drm/msm/msm_drv.h | 64 ++ drivers/gpu/drm/msm/msm_fb.c | 2 +- drivers/gpu/drm/msm/msm_kms.h | 4 - 30 files changed, 884 insertions(+), 1065 deletions(-) -- 2.39.2
[PATCH 09/12] drm/msm: convert msm_format::unpack_align_msb to the flag
Instead of having a u8 or bool field unpack_align_msb, convert it to the flag, this save space in the tables and allows us to handle all booleans in the same way. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 12 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +- drivers/gpu/drm/msm/msm_drv.h | 4 ++-- 4 files changed, 6 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index 419400311837..baf0fd67bf42 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -43,7 +43,6 @@ bp, flg, fm, np) \ .bpc_r_cr = r,\ .bpc_a = a, \ .chroma_sample = CHROMA_FULL, \ - .unpack_align_msb = 0,\ .unpack_count = uc, \ .bpp = bp,\ .fetch_mode = fm, \ @@ -64,7 +63,6 @@ alpha, bp, flg, fm, np, th) \ .bpc_r_cr = r,\ .bpc_a = a, \ .chroma_sample = CHROMA_FULL, \ - .unpack_align_msb = 0,\ .unpack_count = uc, \ .bpp = bp,\ .fetch_mode = fm, \ @@ -86,7 +84,6 @@ alpha, chroma, count, bp, flg, fm, np) \ .bpc_r_cr = r,\ .bpc_a = a, \ .chroma_sample = chroma, \ - .unpack_align_msb = 0,\ .unpack_count = count,\ .bpp = bp,\ .fetch_mode = fm, \ @@ -106,7 +103,6 @@ alpha, chroma, count, bp, flg, fm, np) \ .bpc_r_cr = r,\ .bpc_a = a, \ .chroma_sample = chroma, \ - .unpack_align_msb = 0,\ .unpack_count = 2,\ .bpp = 2, \ .fetch_mode = fm, \ @@ -127,7 +123,6 @@ flg, fm, np, th) \ .bpc_r_cr = r,\ .bpc_a = a, \ .chroma_sample = chroma, \ - .unpack_align_msb = 0,\ .unpack_count = 2,\ .bpp = 2, \ .fetch_mode = fm, \ @@ -147,11 +142,10 @@ flg, fm, np, th) \ .bpc_r_cr = r,\ .bpc_a = a, \ .chroma_sample = chroma, \ - .unpack_align_msb = 1,\ .unpack_count = 2,\ .bpp = 2, \ .fetch_mode = fm, \ - .flags = flg, \ + .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \ .num_planes = np, \ .tile_height = DPU_TILE_HEIGHT_DEFAULT\ } @@ -168,11 +162,10 @@ flg, fm, np, th) \ .bpc_r_cr = r,\ .bpc_a = a,
[PATCH 06/12] drm/msm/dpu: pull format flag definitions to msm_drv.h
In preparation to merger of formats databases, pull format flag definitions to msm_drv.h header, so that they are visibile to both dpu and mdp drivers. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 98 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 28 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 8 +- drivers/gpu/drm/msm/disp/mdp_format.c | 6 +- drivers/gpu/drm/msm/disp/mdp_kms.h | 3 +- drivers/gpu/drm/msm/msm_drv.h | 24 + 8 files changed, 91 insertions(+), 84 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index 3112d85808c7..25d3451e8260 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -44,8 +44,8 @@ bp, flg, fm, np) \ .unpack_tight = 1,\ .unpack_count = uc, \ .bpp = bp,\ - .fetch_mode = fm, \ - .flags = flg, \ + .base.fetch_mode = fm,\ + .base.flags = flg,\ .num_planes = np, \ .tile_height = DPU_TILE_HEIGHT_DEFAULT\ } @@ -63,8 +63,8 @@ alpha, bp, flg, fm, np, th) \ .unpack_tight = 1,\ .unpack_count = uc, \ .bpp = bp,\ - .fetch_mode = fm, \ - .flags = flg, \ + .base.fetch_mode = fm,\ + .base.flags = flg,\ .num_planes = np, \ .tile_height = th \ } @@ -83,8 +83,8 @@ alpha, chroma, count, bp, flg, fm, np) \ .unpack_tight = 1,\ .unpack_count = count,\ .bpp = bp,\ - .fetch_mode = fm, \ - .flags = flg, \ + .base.fetch_mode = fm,\ + .base.flags = flg,\ .num_planes = np, \ .tile_height = DPU_TILE_HEIGHT_DEFAULT\ } @@ -101,8 +101,8 @@ alpha, chroma, count, bp, flg, fm, np) \ .unpack_tight = 1,\ .unpack_count = 2,\ .bpp = 2, \ - .fetch_mode = fm, \ - .flags = flg, \ + .base.fetch_mode = fm,\ + .base.flags = flg,\ .num_planes = np, \ .tile_height = DPU_TILE_HEIGHT_DEFAULT\ } @@ -120,8 +120,8 @@ flg, fm, np, th) \ .unpack_tight = 1,\ .unpack_count = 2,\ .bpp = 2, \ - .fetch_mode = fm, \ - .flags = flg, \ + .base.fetch_mode = fm,\ + .base.flags = flg,\ .num_planes = np, \ .tile_height = th \ } @@ -138,8 +138,8 @@ flg, fm, np, th) \ .unpack_tight = 0,
[PATCH 12/12] drm/msm: drop msm_kms_funcs::get_format() callback
Now as all subdrivers were converted to use common database of formats,
drop the get_format() callback and use mdp_get_format() directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c| 2 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 1 -
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 1 -
drivers/gpu/drm/msm/msm_fb.c | 2 +-
drivers/gpu/drm/msm/msm_kms.h| 4
8 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index bd3ab2ab6515..bf7eb70ed2da 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -267,7 +267,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
drm_mode_to_intf_timing_params(phys_enc, , _params);
- fmt =
phys_enc->dpu_kms->base.funcs->get_format(_enc->dpu_kms->base, fmt_fourcc,
0);
+ fmt = mdp_get_format(_enc->dpu_kms->base, fmt_fourcc, 0);
DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
intf_cfg.intf = phys_enc->hw_intf->idx;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index cef6066c0d3e..c1ec514e73d3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -622,7 +622,7 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct
dpu_encoder_phys *phys_enc
format = msm_framebuffer_format(job->fb);
- wb_cfg->dest.format =
phys_enc->dpu_kms->base.funcs->get_format(_enc->dpu_kms->base,
+ wb_cfg->dest.format = mdp_get_format(_enc->dpu_kms->base,
format->pixel_format,
job->fb->modifier);
if (!wb_cfg->dest.format) {
/* this error should be detected during atomic_check */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index faff3aaf1029..4977269fbe57 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -981,7 +981,6 @@ static const struct msm_kms_funcs kms_funcs = {
.enable_vblank = dpu_kms_enable_vblank,
.disable_vblank = dpu_kms_disable_vblank,
.check_modified_format = dpu_format_check_modified_format,
- .get_format = mdp_get_format,
.destroy = dpu_kms_destroy,
.snapshot= dpu_kms_mdp_snapshot,
#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 1d7e0068e9c3..a8ede71d84de 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -659,7 +659,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
* select fill format to match user property expectation,
* h/w only supports RGB variants
*/
- fmt = priv->kms->funcs->get_format(priv->kms, DRM_FORMAT_ABGR, 0);
+ fmt = mdp_get_format(priv->kms, DRM_FORMAT_ABGR, 0);
/* should not happen ever */
if (!fmt)
return;
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
index 4ba1cb74ad76..6e4e74f9d63d 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
@@ -151,7 +151,6 @@ static const struct mdp_kms_funcs kms_funcs = {
.flush_commit= mdp4_flush_commit,
.wait_flush = mdp4_wait_flush,
.complete_commit = mdp4_complete_commit,
- .get_format = mdp_get_format,
.round_pixclk= mdp4_round_pixclk,
.destroy = mdp4_destroy,
},
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index 48f447f4e183..18670ea40a3a 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -267,7 +267,6 @@ static const struct mdp_kms_funcs kms_funcs = {
.prepare_commit = mdp5_prepare_commit,
.wait_flush = mdp5_wait_flush,
.complete_commit = mdp5_complete_commit,
- .get_format = mdp_get_format,
.set_split_display = mdp5_set_split_display,
.destroy = mdp5_kms_destroy,
#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c
index e3f61c39df69..8326150e5e0c 100644
--- a/drivers/gpu/drm/msm/msm_fb.c
+++ b/drivers/gpu/drm/msm/msm_fb.c
@@ -181,7 +181,7 @@ static struct drm_framebuffer
Re: (subset) [PATCH RFC v7 00/10] Support for Solid Fill Planes
On Fri, 27 Oct 2023 15:32:50 -0700, Jessica Zhang wrote: > Some drivers support hardware that have optimizations for solid fill > planes. This series aims to expose these capabilities to userspace as > some compositors have a solid fill flag (ex. SOLID_COLOR in the Android > hardware composer HAL) that can be set by apps like the Android Gears > test app. > > In order to expose this capability to userspace, this series will: > > [...] Applied to drm-misc-next, thanks! [01/10] drm: Introduce pixel_source DRM plane property commit: e50e5fed41c7eed2db4119645bf3480ec43fec11 [02/10] drm: Introduce solid fill DRM plane property commit: 85863a4e16e77079ee14865905ddc3ef9483a640 [03/10] drm: Add solid fill pixel source commit: 4b64167042927531f4cfaf035b8f88c2f7a05f06 [04/10] drm/atomic: Add pixel source to plane state dump commit: 8283ac7871a959848e09fc6593b8c12b8febfee6 [05/10] drm/atomic: Add solid fill data to plane state dump commit: e86413f5442ee094e66b3e75f2d3419ed0df9520 [06/10] drm/atomic: Move framebuffer checks to helper commit: 4ba6b7a646321e740c7f2d80c90505019c4e8fce [07/10] drm/atomic: Loosen FB atomic checks commit: f1e75da5364e780905d9cd6043f9c74cdcf84073 Best regards, -- Dmitry Baryshkov
[PATCH 01/12] drm/msm: fix BPC1 -> BPC4
Fix enum mdp_bpc::BPC1 value to be BPC4 instead (as shown in the DPU
driver). This commit should be replaced with the registers sync with
Mesa instead.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp_common.xml.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp_common.xml.h
b/drivers/gpu/drm/msm/disp/mdp_common.xml.h
index 4dd8d7db2862..5220688727e4 100644
--- a/drivers/gpu/drm/msm/disp/mdp_common.xml.h
+++ b/drivers/gpu/drm/msm/disp/mdp_common.xml.h
@@ -94,7 +94,7 @@ enum mdp_component_type {
};
enum mdp_bpc {
- BPC1 = 0,
+ BPC4 = 0,
BPC5 = 1,
BPC6 = 2,
BPC8 = 3,
--
2.39.2
Re: [RFC] drm/msm/rd: Check PT_PTRACED for cmdstream dumping
On 14/09/2023 20:24, Rob Clark wrote: From: Rob Clark So, when you want to get a cmdstream trace of some deqp or piglit test, but you happen to be running it on the same laptop with full desktop env, the current dump-everything firehose of `cat $debugfs/dri/n/rd` is quite a bit too much. Ptrace seemed kind of a natural way to control it, ie. either run what you want to trace under gdb or hack in a ptrace(PTRACE_TRACEME) call. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_gem_submit.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Dmitry Baryshkov I think this is a good idea, to be able to separate process being debugged and all other tasks. diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c index a908373cf34b..a105ca1f2102 100644 --- a/drivers/gpu/drm/msm/msm_gem_submit.c +++ b/drivers/gpu/drm/msm/msm_gem_submit.c @@ -979,7 +979,8 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data, /* The scheduler owns a ref now: */ msm_gem_submit_get(submit); - msm_rd_dump_submit(priv->rd, submit, NULL); + if (current->ptrace & PT_PTRACED) + msm_rd_dump_submit(priv->rd, submit, NULL); pm_runtime_get_sync(>pdev->dev); -- With best wishes Dmitry
[PATCH 11/12] drm/msm: merge dpu format database to MDP formats
Finally remove duplication between DPU and generic MDP code by merging
DPU format lists to the MDP format database.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 4 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 602 --
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 23 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 10 -
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +-
drivers/gpu/drm/msm/disp/mdp_format.c | 595 +++--
drivers/gpu/drm/msm/disp/mdp_kms.h| 2 -
drivers/gpu/drm/msm/msm_drv.h | 12 +
10 files changed, 549 insertions(+), 706 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 35aaead897e1..bd3ab2ab6515 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -267,7 +267,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
drm_mode_to_intf_timing_params(phys_enc, , _params);
- fmt = dpu_get_dpu_format(fmt_fourcc);
+ fmt =
phys_enc->dpu_kms->base.funcs->get_format(_enc->dpu_kms->base, fmt_fourcc,
0);
DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
intf_cfg.intf = phys_enc->hw_intf->idx;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index a400c44a1a71..cef6066c0d3e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -622,8 +622,8 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct
dpu_encoder_phys *phys_enc
format = msm_framebuffer_format(job->fb);
- wb_cfg->dest.format = dpu_get_dpu_format_ext(
- format->pixel_format, job->fb->modifier);
+ wb_cfg->dest.format =
phys_enc->dpu_kms->base.funcs->get_format(_enc->dpu_kms->base,
+format->pixel_format,
job->fb->modifier);
if (!wb_cfg->dest.format) {
/* this error should be detected during atomic_check */
DPU_ERROR("failed to get format %x\n", format->pixel_format);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index de9e93cb42c4..dff2ff173d80 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -11,186 +11,11 @@
#include "dpu_kms.h"
#include "dpu_formats.h"
-#define DPU_UBWC_META_MACRO_W_H16
-#define DPU_UBWC_META_BLOCK_SIZE 256
#define DPU_UBWC_PLANE_SIZE_ALIGNMENT 4096
-#define DPU_TILE_HEIGHT_DEFAULT1
-#define DPU_TILE_HEIGHT_TILED 4
-#define DPU_TILE_HEIGHT_UBWC 4
-#define DPU_TILE_HEIGHT_NV12 8
-
#define DPU_MAX_IMG_WIDTH 0x3FFF
#define DPU_MAX_IMG_HEIGHT 0x3FFF
-/*
- * DPU supported format packing, bpp, and other format
- * information.
- * DPU currently only supports interleaved RGB formats
- * UBWC support for a pixel format is indicated by the flag,
- * there is additional meta data plane for such formats
- */
-
-#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha, \
-bp, flg, fm, np) \
-{ \
- .pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_type = MDP_PLANE_INTERLEAVED, \
- .element = { (e0), (e1), (e2), (e3) },\
- .bpc_g_y = g, \
- .bpc_b_cb = b,\
- .bpc_r_cr = r,\
- .bpc_a = a, \
- .chroma_sample = CHROMA_FULL, \
- .unpack_count = uc, \
- .bpp = bp,\
- .fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
- (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0) | \
- flg, \
- .num_planes = np, \
- .tile_height = DPU_TILE_HEIGHT_DEFAULT\
-}
-
-#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc,\
-alpha, bp, flg, fm, np, th) \
-{
[PATCH 08/12] drm/msm: convert msm_format::unpack_tight to the flag
Instead of having a u8 or bool field unpack_tight, convert it to the flag, this save space in the tables and allows us to handle all booleans in the same way. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 22 +++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 3 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 3 +- drivers/gpu/drm/msm/disp/mdp_format.c | 52 ++--- drivers/gpu/drm/msm/msm_drv.h | 4 +- 7 files changed, 41 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index ea9d5fb01000..419400311837 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -44,11 +44,10 @@ bp, flg, fm, np) \ .bpc_a = a, \ .chroma_sample = CHROMA_FULL, \ .unpack_align_msb = 0,\ - .unpack_tight = 1,\ .unpack_count = uc, \ .bpp = bp,\ .fetch_mode = fm, \ - .flags = flg, \ + .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \ .num_planes = np, \ .tile_height = DPU_TILE_HEIGHT_DEFAULT\ } @@ -66,11 +65,10 @@ alpha, bp, flg, fm, np, th) \ .bpc_a = a, \ .chroma_sample = CHROMA_FULL, \ .unpack_align_msb = 0,\ - .unpack_tight = 1,\ .unpack_count = uc, \ .bpp = bp,\ .fetch_mode = fm, \ - .flags = flg, \ + .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \ .num_planes = np, \ .tile_height = th \ } @@ -89,11 +87,10 @@ alpha, chroma, count, bp, flg, fm, np) \ .bpc_a = a, \ .chroma_sample = chroma, \ .unpack_align_msb = 0,\ - .unpack_tight = 1,\ .unpack_count = count,\ .bpp = bp,\ .fetch_mode = fm, \ - .flags = flg, \ + .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \ .num_planes = np, \ .tile_height = DPU_TILE_HEIGHT_DEFAULT\ } @@ -110,11 +107,10 @@ alpha, chroma, count, bp, flg, fm, np) \ .bpc_a = a, \ .chroma_sample = chroma, \ .unpack_align_msb = 0,\ - .unpack_tight = 1,\ .unpack_count = 2,\ .bpp = 2, \ .fetch_mode = fm, \ - .flags = flg, \ + .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \ .num_planes = np, \ .tile_height = DPU_TILE_HEIGHT_DEFAULT\ } @@ -132,11 +128,10 @@ flg, fm, np, th) \ .bpc_a = a, \ .chroma_sample = chroma, \ .unpack_align_msb = 0,\ - .unpack_tight = 1,
[PATCH 10/12] drm/msm: convert msm_format::alpha_enable to the flag
Instead of having a bool field alpha_enable, convert it to the
flag, this save space in the tables and allows us to handle all booleans
in the same way.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 12 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 24 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 7 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 4 ++--
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 2 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c | 3 ++-
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 9
drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 3 ++-
drivers/gpu/drm/msm/disp/mdp_format.c | 2 +-
drivers/gpu/drm/msm/msm_drv.h | 4 ++--
11 files changed, 40 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 9041b0d71b25..201010038660 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -342,7 +342,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer
*mixer,
/* default to opaque blending */
if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
- !format->alpha_enable) {
+ !(format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE)) {
blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
DPU_BLEND_BG_ALPHA_BG_CONST;
} else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
@@ -373,8 +373,8 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer
*mixer,
lm->ops.setup_blend_config(lm, pstate->stage,
fg_alpha, bg_alpha, blend_op);
- DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
- >pixel_format, format->alpha_enable, blend_op);
+ DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%lu blend_op:0x%x\n",
+ >pixel_format, format->flags &
MSM_FORMAT_FLAG_ALPHA_ENABLE, blend_op);
}
static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
@@ -472,7 +472,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
format = msm_framebuffer_format(pstate->base.fb);
- if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
+ if (pstate->stage == DPU_STAGE_BASE &&
+ format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE)
bg_alpha_enable = true;
set_bit(pstate->pipe.sspp->idx, fetch_active);
@@ -495,7 +496,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc
*crtc,
for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
_dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate,
format);
- if (bg_alpha_enable && !format->alpha_enable)
+ if (bg_alpha_enable &&
+ !(format->flags & MSM_FORMAT_FLAG_ALPHA_ENABLE))
mixer[lm_idx].mixer_op_mode = 0;
else
mixer[lm_idx].mixer_op_mode |=
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index baf0fd67bf42..de9e93cb42c4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -36,7 +36,6 @@ bp, flg, fm, np)
\
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_INTERLEAVED, \
- .alpha_enable = alpha,\
.element = { (e0), (e1), (e2), (e3) },\
.bpc_g_y = g, \
.bpc_b_cb = b,\
@@ -46,7 +45,9 @@ bp, flg, fm, np)
\
.unpack_count = uc, \
.bpp = bp,\
.fetch_mode = fm, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
+ (alpha ? MSM_FORMAT_FLAG_ALPHA_ENABLE : 0) | \
+ flg, \
.num_planes = np, \
.tile_height = DPU_TILE_HEIGHT_DEFAULT\
}
@@ -56,7 +57,6 @@ alpha, bp, flg, fm, np, th)
\
{
Re: [PATCH v2 1/6] drm/msm/dpu: fix video mode DSC for DSI
On 16/11/2023 20:30, Jonathan Marek wrote:
On 11/15/23 3:53 AM, Dmitry Baryshkov wrote:
On Wed, 15 Nov 2023 at 01:00, Jonathan Marek wrote:
Add necessary DPU changes for DSC to work with DSI video mode.
Note this changes the logic to enable HCTL to match downstream, it will
now be enabled for the no-DSC no-widebus case.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 11 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 13 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 1 +
5 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 1cf7ff6caff4..d745c8678b9d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2477,7 +2477,7 @@ enum dpu_intf_mode
dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
return INTF_MODE_NONE;
}
-unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys
*phys_enc)
+unsigned int dpu_encoder_helper_get_dsc(const struct
dpu_encoder_phys *phys_enc)
Why?
drm_mode_to_intf_timing_params has "phys_enc" pointer declared as const,
so one of them needs to change to call dpu_encoder_helper_get_dsc
{
struct drm_encoder *encoder = phys_enc->parent;
struct dpu_encoder_virt *dpu_enc =
to_dpu_encoder_virt(encoder);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 6f04c3d56e77..7e27a7da0887 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -332,7 +332,7 @@ static inline enum dpu_3d_blend_mode
dpu_encoder_helper_get_3d_blend_mode(
* used for this encoder.
* @phys_enc: Pointer to physical encoder structure
*/
-unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys
*phys_enc);
+unsigned int dpu_encoder_helper_get_dsc(const struct
dpu_encoder_phys *phys_enc);
/**
* dpu_encoder_helper_split_config - split display configuration
helper function
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index a01fda711883..df10800a9615 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -100,6 +100,8 @@ static void drm_mode_to_intf_timing_params(
}
timing->wide_bus_en =
dpu_encoder_is_widebus_enabled(phys_enc->parent);
+ if (dpu_encoder_helper_get_dsc(phys_enc))
+ timing->compression_en = true;
/*
* for DP, divide the horizonal parameters by 2 when
@@ -112,6 +114,15 @@ static void drm_mode_to_intf_timing_params(
timing->h_front_porch = timing->h_front_porch >> 1;
timing->hsync_pulse_width =
timing->hsync_pulse_width >> 1;
}
+
+ /*
+ * for DSI, if compression is enabled, then divide the
horizonal active
+ * timing parameters by compression ratio.
+ */
+ if (phys_enc->hw_intf->cap->type != INTF_DP &&
timing->compression_en) {
+ timing->width = timing->width / 3; /* XXX: don't
assume 3:1 compression ratio */
Is this /3 from bpp / compressed_bpp?
It is the compression ratio of DSC for 8bpc (24bpp) compressed to 8bpp.
DSI driver doesn't support any other cases so this assumption should be
OK for now (the other common ratio is 3.75 for 10bpc compressed to 8bpp
- from downstream driver it appears this would mean a division by 3.75
here).
+ timing->xres = timing->width;
+ }
}
static u32 get_horizontal_total(const struct
dpu_hw_intf_timing_params *timing)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index e8b8908d3e12..d6fe45a6da2d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -166,10 +166,21 @@ static void
dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
* video timing. It is recommended to enable it for all
cases, except
* if compression is enabled in 1 pixel per clock mode
*/
+ if (!p->compression_en || p->wide_bus_en)
+ intf_cfg2 |= INTF_CFG2_DATA_HCTL_EN;
+
if (p->wide_bus_en)
- intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN |
INTF_CFG2_DATA_HCTL_EN;
+ intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN;
data_width = p->width;
+ if (p->wide_bus_en && !dp_intf)
+ data_width = p->width >> 1;
+
+ if (p->compression_en)
+ intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
+
+ if (p->compression_en && dp_intf)
+ DPU_ERROR("missing
[PATCH RESEND] drm/drv: propagate errors from drm_modeset_register_all()
In case the drm_modeset_register_all() function fails, its error code
will be ignored. Instead make the drm_dev_register() bail out in case of
such an error.
Fixes: 79190ea2658a ("drm: Add callbacks for late registering")
Reviewed-by: Neil Armstrong
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/drm_drv.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 535f16e7882e..3c835c99daad 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -949,8 +949,11 @@ int drm_dev_register(struct drm_device *dev, unsigned long
flags)
goto err_minors;
}
- if (drm_core_check_feature(dev, DRIVER_MODESET))
- drm_modeset_register_all(dev);
+ if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+ ret = drm_modeset_register_all(dev);
+ if (ret)
+ goto err_unload;
+ }
DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
driver->name, driver->major, driver->minor,
@@ -960,6 +963,9 @@ int drm_dev_register(struct drm_device *dev, unsigned long
flags)
goto out_unlock;
+err_unload:
+ if (dev->driver->unload)
+ dev->driver->unload(dev);
err_minors:
remove_compat_control_link(dev);
drm_minor_unregister(dev, DRM_MINOR_ACCEL);
--
2.39.2
[PATCH RESEND 2/5] drm/msm/dpu: finalise global state object
Add calls to finalise global state object and corresponding lock.
Fixes: de3916c70a24 ("drm/msm/dpu: Track resources in global state")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index fe7267b3bff5..73f70e67cfef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -385,6 +385,12 @@ static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)
return 0;
}
+static void dpu_kms_global_obj_fini(struct dpu_kms *dpu_kms)
+{
+ drm_atomic_private_obj_fini(_kms->global_state);
+ drm_modeset_lock_fini(_kms->global_state_lock);
+}
+
static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms)
{
struct icc_path *path0;
@@ -826,6 +832,8 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
dpu_rm_destroy(_kms->rm);
dpu_kms->rm_init = false;
+ dpu_kms_global_obj_fini(dpu_kms);
+
dpu_kms->catalog = NULL;
if (dpu_kms->hw_mdp)
--
2.39.2
Re: [Nouveau] Kernel problem with multiseat on one card
On Sat, Dec 02, 2023 at 03:28:25PM +, Timur Tabi wrote: > On Sat, 2023-12-02 at 20:18 +0700, Bagas Sanjaya wrote: > > > > > > When i install the proprietary Nvidia drivers, i have the following: > > > > > > [MASTER] pci::08:00.0 > > > │ ├─/sys/devices/pci:00/:00:03.1/:08:00.0/drm/card0 > > > │ │ [MASTER] drm:card0 > > > │ > > > └─/sys/devices/pci:00/:00:03.1/:08:00.0/drm/renderD128 > > > │ drm:renderD128 > > > > > > ─/sys/devices/platform/efi-framebuffer.0/graphics/fb0 > > > │ graphics:fb0 "EFI VGA" > > > > > > So no VGA, DVI or HDMI items. > > > > Then report to the GitHub tracker [1]. > > > > Thanks. > > > > [1]: https://github.com/NVIDIA/open-gpu-kernel-modules/issues > > > > No, do NOT report this on the Github tracker! > > That github tracker is ONLY for bugs that occur with OpenRM (the "Open GPU > Kernel Module") but not with the the proprietary driver. If you have a bug > with the the Nvidia proprietary driver, that must be reported on the Nvidia > forum instead: > > https://forums.developer.nvidia.com/c/gpu-graphics/linux/148 > Thanks for the correct pointer! Sorry for inconvenience. -- An old man doll... just what I always wanted! - Clara signature.asc Description: PGP signature
[PATCH RESEND] drm/display: Drop obsolete dependency on COMPILE_TEST
Since commit 0166dc11be91 ("of: make CONFIG_OF user selectable"), it
is possible to test-build any driver which depends on OF on any
architecture by explicitly selecting OF. Therefore depending on
COMPILE_TEST as an alternative is no longer needed.
Signed-off-by: Jean Delvare
Cc: David Airlie
Cc: Daniel Vetter
---
Already sent on: 2022-10-03, 2023-01-27
This is one of the only 4 remaining occurrences of this deprecated
construct.
drivers/gpu/drm/display/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- linux-6.6.orig/drivers/gpu/drm/display/Kconfig
+++ linux-6.6/drivers/gpu/drm/display/Kconfig
@@ -3,7 +3,7 @@
config DRM_DP_AUX_BUS
tristate
depends on DRM
- depends on OF || COMPILE_TEST
+ depends on OF
config DRM_DISPLAY_HELPER
tristate
--
Jean Delvare
SUSE L3 Support
[PATCH RESEND] drm/logicvc: Drop obsolete dependency on COMPILE_TEST
Since commit 0166dc11be91 ("of: make CONFIG_OF user selectable"), it
is possible to test-build any driver which depends on OF on any
architecture by explicitly selecting OF. Therefore depending on
COMPILE_TEST as an alternative is no longer needed.
Signed-off-by: Jean Delvare
Reviewed-by: Paul Kocialkowski
Cc: David Airlie
Cc: Daniel Vetter
---
Already sent on: 2022-11-21, 2023-01-27
This is one of the only 4 remaining occurrences of this deprecated
construct.
drivers/gpu/drm/logicvc/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- linux-6.6.orig/drivers/gpu/drm/logicvc/Kconfig
+++ linux-6.6/drivers/gpu/drm/logicvc/Kconfig
@@ -1,7 +1,7 @@
config DRM_LOGICVC
tristate "LogiCVC DRM"
depends on DRM
- depends on OF || COMPILE_TEST
+ depends on OF
select DRM_KMS_HELPER
select DRM_KMS_DMA_HELPER
select DRM_GEM_DMA_HELPER
--
Jean Delvare
SUSE L3 Support
Re: [PATCH] drm/msm/gpu: Fix null-pointer dereference in zap_shader_load_mdt
On 23/11/2023 05:33, Kunwu Chan wrote:
kasprintf() returns a pointer to dynamically allocated memory
which can be NULL upon failure. Ensure the allocation was successful
by checking the pointer validity.
Fixes: a9e2559c931d ("drm/msm/gpu: Move zap shader loading to adreno")
Signed-off-by: Kunwu Chan
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4
1 file changed, 4 insertions(+)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
[PATCH v2] drm/msm/dpu: correct clk bit for WB2 block
On sc7280 there are two clk bits for WB2: vbif_cli and clk_ctrl. While
programming the VBIF params of WB, the driver should be toggling the
former bit, while the sc7180_mdp, sc7280_mdp and sm8250_mdp structs
list the latter one.
Correct that to ensure proper programming sequence for WB2 on these
platforms.
Fixes: 255f056181ac ("drm/msm/dpu: sc7180: add missing WB2 clock control")
Fixes: 3ce166380567 ("drm/msm/dpu: add writeback support for sc7280")
Fixes: 53324b99bd7b ("drm/msm/dpu: add writeback blocks to the sm8250 DPU
catalog")
Signed-off-by: Dmitry Baryshkov
---
Changes since v1:
- Fixed the bits for all three platforms supporting WB (Abhinav)
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 94278a3e3483..9f8068fa0175 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -32,7 +32,7 @@ static const struct dpu_mdp_cfg sm8250_mdp = {
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
- [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index c0d88ddccb28..9bfa15e4e645 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -25,7 +25,7 @@ static const struct dpu_mdp_cfg sc7180_mdp = {
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
- [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 15942fa5a8e0..b9c296e51e36 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -25,7 +25,7 @@ static const struct dpu_mdp_cfg sc7280_mdp = {
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
- [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
+ [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
},
};
--
2.39.2
