From: Michel Dänzer <daen...@vmware.com>
While investigating the cause of CRTC FIFO underruns, I noticed that when
converting the memory bandwidth calculation from the userspac X driver code,
an instance of '8.0' was apparently accidentally converted to '80'.
Signed-off-by: Michel Dänzer <daen...@vmware.com>
---
drivers/gpu/drm/radeon/r100.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 374ecac..33198dd 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -2350,7 +2350,7 @@ void r100_bandwidth_update(struct radeon_device *rdev)
/*
Find the total latency for the display data.
*/
- disp_latency_overhead.full = rfixed_const(80);
+ disp_latency_overhead.full = rfixed_const(8);
disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
mc_latency_mclk.full += disp_latency_overhead.full +
cur_latency_mclk.full;
mc_latency_sclk.full += disp_latency_overhead.full +
cur_latency_sclk.full;
--
1.6.4.3
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