Re: [RFC PATCH v5] Xilinx AXI-Stream FIFO v4.1 IP core
On Wed, Aug 01, 2018 at 11:52:39AM +0300, Dan Carpenter wrote: > The README is empty... It should say what changes are needed to get > this out of staging. > > regards, > dan carpenter > Right :) It's ready as far as I'm concerned. Best, Jacob ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[RFC PATCH v5] Xilinx AXI-Stream FIFO v4.1 IP core
This IP core has read and write AXI-Stream FIFOs, the contents of which can be accessed from the AXI4 memory-mapped interface. This is useful for transferring data from a processor into the FPGA fabric. The driver creates a character device that can be read/written to with standard open/read/write/close. See Xilinx PG080 document for IP details. https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf The driver currently supports only store-forward mode with a 32-bit AXI4 Lite interface. DOES NOT support: - cut-through mode - AXI4 (non-lite) Signed-off-by: Jacob Feder --- Added EOL Cheers, Jacob drivers/staging/Kconfig |2 + drivers/staging/Makefile|1 + drivers/staging/axis-fifo/Kconfig |9 + drivers/staging/axis-fifo/Makefile |1 + drivers/staging/axis-fifo/README|0 drivers/staging/axis-fifo/axis-fifo.c | 1108 +++ drivers/staging/axis-fifo/axis-fifo.txt | 89 +++ 7 files changed, 1210 insertions(+) create mode 100644 drivers/staging/axis-fifo/Kconfig create mode 100644 drivers/staging/axis-fifo/Makefile create mode 100644 drivers/staging/axis-fifo/README create mode 100644 drivers/staging/axis-fifo/axis-fifo.c create mode 100644 drivers/staging/axis-fifo/axis-fifo.txt diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index 75a4804..6385920 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -126,4 +126,6 @@ source "drivers/staging/mt7621-eth/Kconfig" source "drivers/staging/mt7621-dts/Kconfig" +source "drivers/staging/axis-fifo/Kconfig" + endif # STAGING diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index e84959a..19b8435 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -54,3 +54,4 @@ obj-$(CONFIG_SOC_MT7621) += mt7621-dma/ obj-$(CONFIG_SOC_MT7621) += mt7621-mmc/ obj-$(CONFIG_SOC_MT7621) += mt7621-eth/ obj-$(CONFIG_SOC_MT7621) += mt7621-dts/ +obj-$(CONFIG_XIL_AXIS_FIFO)+= axis-fifo/ diff --git a/drivers/staging/axis-fifo/Kconfig b/drivers/staging/axis-fifo/Kconfig new file mode 100644 index 000..6875372 --- /dev/null +++ b/drivers/staging/axis-fifo/Kconfig @@ -0,0 +1,9 @@ +# +# "Xilinx AXI-Stream FIFO IP core driver" +# +config XIL_AXIS_FIFO + tristate "Xilinx AXI-Stream FIFO IP core driver" + default n + help + This adds support for the Xilinx AXI-Stream + FIFO IP core driver. diff --git a/drivers/staging/axis-fifo/Makefile b/drivers/staging/axis-fifo/Makefile new file mode 100644 index 000..fe62cd1 --- /dev/null +++ b/drivers/staging/axis-fifo/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_XIL_AXIS_FIFO) += axis-fifo.o diff --git a/drivers/staging/axis-fifo/README b/drivers/staging/axis-fifo/README new file mode 100644 index 000..e69de29 diff --git a/drivers/staging/axis-fifo/axis-fifo.c b/drivers/staging/axis-fifo/axis-fifo.c new file mode 100644 index 000..2a73302 --- /dev/null +++ b/drivers/staging/axis-fifo/axis-fifo.c @@ -0,0 +1,1108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core + * + * Copyright (C) 2018 Jacob Feder + * + * Authors: Jacob Feder + * + * See Xilinx PG080 document for IP details + */ + +/* + * includes + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* + * driver parameters + * + */ + +#define DRIVER_NAME "axis_fifo" + +#define READ_BUF_SIZE 128U /* read buffer length in words */ +#define WRITE_BUF_SIZE 128U /* write buffer length in words */ + +/* + * IP register offsets + * + */ + +#define XLLF_ISR_OFFSET 0x /* Interrupt Status */ +#define XLLF_IER_OFFSET 0x0004 /* Interrupt Enable */ + +#define XLLF_TDFR_OFFSET 0x0008 /* Transmit Reset */ +#define XLLF_TDFV_OFFSET 0x000c /* Transmit Vacancy */ +#define XLLF_TDFD_OFFSET 0x0010 /* Transmit Data */ +#define XLLF_TLR_OFFSET 0x0014 /* Transmit Length */ + +#define XLLF_RDFR_OFFSET 0x0018 /* Receive Reset */ +#define XLLF_RDFO_OFFSET 0x001c /* Receive Occupancy */ +#define XLLF_RDFD_OFFSET 0x0020 /* Receive Data */ +#define XLLF_RLR_OFFSET 0x0024 /* Receive Length */ +#define XLLF_SRR_OFFSET 0x0028 /* Local Link Reset */ +#define XLLF_TDR_OFFSET 0x002C /* Transmit Destination */ +#define XLLF_RDR_OFFSET 0x0030 /* Receive Destination */ + +/* + * reset register masks + * -
[RFC PATCH v4] Xilinx AXI-Stream FIFO v4.1 IP core driver
This IP core has read and write AXI-Stream FIFOs, the contents of which can be accessed from the AXI4 memory-mapped interface. This is useful for transferring data from a processor into the FPGA fabric. The driver creates a character device that can be read/written to with standard open/read/write/close. See Xilinx PG080 document for IP details. https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf The driver currently supports only store-forward mode with a 32-bit AXI4 Lite interface. DOES NOT support: - cut-through mode - AXI4 (non-lite) Signed-off-by: Jacob Feder --- Just had a typo in my makefile. It should be compiling correctly now with no warnings. Best, Jacob drivers/staging/Kconfig |2 + drivers/staging/Makefile|1 + drivers/staging/axis-fifo/Kconfig |9 + drivers/staging/axis-fifo/Makefile |1 + drivers/staging/axis-fifo/README|0 drivers/staging/axis-fifo/axis-fifo.c | 1108 +++ drivers/staging/axis-fifo/axis-fifo.txt | 89 +++ 7 files changed, 1210 insertions(+) create mode 100644 drivers/staging/axis-fifo/Kconfig create mode 100644 drivers/staging/axis-fifo/Makefile create mode 100644 drivers/staging/axis-fifo/README create mode 100644 drivers/staging/axis-fifo/axis-fifo.c create mode 100644 drivers/staging/axis-fifo/axis-fifo.txt diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index 75a4804..6385920 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -126,4 +126,6 @@ source "drivers/staging/mt7621-eth/Kconfig" source "drivers/staging/mt7621-dts/Kconfig" +source "drivers/staging/axis-fifo/Kconfig" + endif # STAGING diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index e84959a..19b8435 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -54,3 +54,4 @@ obj-$(CONFIG_SOC_MT7621) += mt7621-dma/ obj-$(CONFIG_SOC_MT7621) += mt7621-mmc/ obj-$(CONFIG_SOC_MT7621) += mt7621-eth/ obj-$(CONFIG_SOC_MT7621) += mt7621-dts/ +obj-$(CONFIG_XIL_AXIS_FIFO)+= axis-fifo/ diff --git a/drivers/staging/axis-fifo/Kconfig b/drivers/staging/axis-fifo/Kconfig new file mode 100644 index 000..77d5701 --- /dev/null +++ b/drivers/staging/axis-fifo/Kconfig @@ -0,0 +1,9 @@ +# +# "Xilinx AXI-Stream FIFO IP core driver" +# +config XIL_AXIS_FIFO + tristate "Xilinx AXI-Stream FIFO IP core driver" + default n + help + This adds support for the Xilinx AXI-Stream + FIFO IP core driver. \ No newline at end of file diff --git a/drivers/staging/axis-fifo/Makefile b/drivers/staging/axis-fifo/Makefile new file mode 100644 index 000..fe62cd1 --- /dev/null +++ b/drivers/staging/axis-fifo/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_XIL_AXIS_FIFO) += axis-fifo.o diff --git a/drivers/staging/axis-fifo/README b/drivers/staging/axis-fifo/README new file mode 100644 index 000..e69de29 diff --git a/drivers/staging/axis-fifo/axis-fifo.c b/drivers/staging/axis-fifo/axis-fifo.c new file mode 100644 index 000..2a73302 --- /dev/null +++ b/drivers/staging/axis-fifo/axis-fifo.c @@ -0,0 +1,1108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core + * + * Copyright (C) 2018 Jacob Feder + * + * Authors: Jacob Feder + * + * See Xilinx PG080 document for IP details + */ + +/* + * includes + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* + * driver parameters + * + */ + +#define DRIVER_NAME "axis_fifo" + +#define READ_BUF_SIZE 128U /* read buffer length in words */ +#define WRITE_BUF_SIZE 128U /* write buffer length in words */ + +/* + * IP register offsets + * + */ + +#define XLLF_ISR_OFFSET 0x /* Interrupt Status */ +#define XLLF_IER_OFFSET 0x0004 /* Interrupt Enable */ + +#define XLLF_TDFR_OFFSET 0x0008 /* Transmit Reset */ +#define XLLF_TDFV_OFFSET 0x000c /* Transmit Vacancy */ +#define XLLF_TDFD_OFFSET 0x0010 /* Transmit Data */ +#define XLLF_TLR_OFFSET 0x0014 /* Transmit Length */ + +#define XLLF_RDFR_OFFSET 0x0018 /* Receive Reset */ +#define XLLF_RDFO_OFFSET 0x001c /* Receive Occupancy */ +#define XLLF_RDFD_OFFSET 0x0020 /* Receive Data */ +#define XLLF_RLR_OFFSET 0x0024 /* Receive Length */ +#define XLLF_SRR_OFFSET 0x0028 /* Local Link Reset */ +#define XLLF_TDR_OFFSET 0x002C /* Transmit Destination */
Re: [RFC PATCH v3] Xilinx AXI-Stream FIFO v4.1 IP core driver
First I run "make menuconfig" and select my driver in "device drivers" > "staging". If I run "make" or "make all" or "make drivers/staging/axis-fifo" everything compiles without errors or warnings even if I put blatant syntax errors in my code. What am I missing here? Thanks, Jacob ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[RFC PATCH v3] Xilinx AXI-Stream FIFO v4.1 IP core driver
I hope I did the Makefile/Kconfig corretly :) Thanks for all the feedback. Cheers, Jacob This IP core has read and write AXI-Stream FIFOs, the contents of which can be accessed from the AXI4 memory-mapped interface. This is useful for transferring data from a processor into the FPGA fabric. The driver creates a character device that can be read/written to with standard open/read/write/close. See Xilinx PG080 document for IP details. https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf The driver currently supports only store-forward mode with a 32-bit AXI4 Lite interface. DOES NOT support: - cut-through mode - AXI4 (non-lite) Signed-off-by: Jacob Feder --- drivers/staging/axisfifo/Kconfig |9 + drivers/staging/axisfifo/Makefile |1 + drivers/staging/axisfifo/axis-fifo.c | 1125 + drivers/staging/axisfifo/axisfifo.txt | 89 +++ 4 files changed, 1224 insertions(+) create mode 100644 drivers/staging/axisfifo/Kconfig create mode 100644 drivers/staging/axisfifo/Makefile create mode 100644 drivers/staging/axisfifo/axis-fifo.c create mode 100644 drivers/staging/axisfifo/axisfifo.txt diff --git a/drivers/staging/axisfifo/Kconfig b/drivers/staging/axisfifo/Kconfig new file mode 100644 index 000..5ad68bf --- /dev/null +++ b/drivers/staging/axisfifo/Kconfig @@ -0,0 +1,9 @@ +# +# "Xilinx AXI-Stream FIFO IP core driver" +# +config XIL_AXISFIFO + tristate "Xilinx AXI-Stream FIFO IP core driver" + default n + help + This adds support for the Xilinx AXI-Stream + FIFO IP core driver. \ No newline at end of file diff --git a/drivers/staging/axisfifo/Makefile b/drivers/staging/axisfifo/Makefile new file mode 100644 index 000..bab1770 --- /dev/null +++ b/drivers/staging/axisfifo/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_XIL_AXISFIFO) := axis-fifo.o diff --git a/drivers/staging/axisfifo/axis-fifo.c b/drivers/staging/axisfifo/axis-fifo.c new file mode 100644 index 000..9cd203f --- /dev/null +++ b/drivers/staging/axisfifo/axis-fifo.c @@ -0,0 +1,1125 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core + * + * Copyright (C) 2018 Jacob Feder + * + * Authors: Jacob Feder + * + * See Xilinx PG080 document for IP details + */ + +/* + * includes + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* + * driver parameters + * + */ + +#define DRIVER_NAME "axis_fifo" + +#define READ_BUF_SIZE 128 /* read buffer length in words */ +#define WRITE_BUF_SIZE 128 /* write buffer length in words */ + +/* + * IP register offsets + * + */ + +#define XLLF_ISR_OFFSET 0x /* Interrupt Status */ +#define XLLF_IER_OFFSET 0x0004 /* Interrupt Enable */ + +#define XLLF_TDFR_OFFSET 0x0008 /* Transmit Reset */ +#define XLLF_TDFV_OFFSET 0x000c /* Transmit Vacancy */ +#define XLLF_TDFD_OFFSET 0x0010 /* Transmit Data */ +#define XLLF_TLR_OFFSET 0x0014 /* Transmit Length */ + +#define XLLF_RDFR_OFFSET 0x0018 /* Receive Reset */ +#define XLLF_RDFO_OFFSET 0x001c /* Receive Occupancy */ +#define XLLF_RDFD_OFFSET 0x0020 /* Receive Data */ +#define XLLF_RLR_OFFSET 0x0024 /* Receive Length */ +#define XLLF_SRR_OFFSET 0x0028 /* Local Link Reset */ +#define XLLF_TDR_OFFSET 0x002C /* Transmit Destination */ +#define XLLF_RDR_OFFSET 0x0030 /* Receive Destination */ + +/* + * reset register masks + * + */ + +#define XLLF_RDFR_RESET_MASK0x00a5 /* receive reset value */ +#define XLLF_TDFR_RESET_MASK0x00a5 /* Transmit reset value */ +#define XLLF_SRR_RESET_MASK 0x00a5 /* Local Link reset value */ + +/* + * interrupt masks + * + */ + +#define XLLF_INT_RPURE_MASK 0x8000 /* Receive under-read */ +#define XLLF_INT_RPORE_MASK 0x4000 /* Receive over-read */ +#define XLLF_INT_RPUE_MASK0x2000 /* Receive underrun (empty) */ +#define XLLF_INT_TPOE_MASK0x1000 /* Transmit overrun */ +#define XLLF_INT_TC_MASK 0x0800 /* Transmit complete */ +#define XLLF_INT_RC_MASK 0x0400 /* Receive complete */ +#define XLLF_INT_TSE_MASK 0x0200 /* Transmit length mismatch */ +#define XLLF_INT_TRC_MASK 0x0100 /* Transmit reset complete */ +#define XLLF_INT_RRC_MASK 0x0080 /* Receive reset complete */ +#define XLLF_I
Re: [RFC PATCH v2] Xilinx AXI-Stream FIFO v4.1 IP core driver
On Mon, Jul 16, 2018 at 09:43:47AM +0200, Greg KH wrote: > On Sun, Jul 15, 2018 at 04:38:51PM -0400, Jacob Feder wrote: > > On Sun, Jul 15, 2018 at 09:44:58PM +0200, Greg KH wrote: > > > On Sun, Jul 15, 2018 at 12:34:28PM -0400, Jacob Feder wrote: > > > > Hi, > > > > I have updated this with the recommended changes. I haven't tried out > > > > the > > > > UIO though. It will be a pretty significant undertaking and I don't want > > > > to spend the time on it unless there is a specific reason you think it > > > > will be faster. > > > > > > > > Thanks all. > > > > > > > > Cheers, > > > > Jacob > > > > > > > > This IP core has read and write AXI-Stream FIFOs, the contents of which > > > > can > > > > be accessed from the AXI4 memory-mapped interface. This is useful for > > > > transferring data from a processor into the FPGA fabric. The driver > > > > creates > > > > a character device that can be read/written to with standard > > > > open/read/write/close. > > > > > > > > See Xilinx PG080 document for IP details. > > > > > > > > https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf > > > > > > > > The driver currently supports only store-forward mode with a 32-bit > > > > AXI4 Lite interface. DOES NOT support: > > > > - cut-through mode > > > > - AXI4 (non-lite) > > > > > > > > Signed-off-by: Jacob Feder > > > > --- > > > > Documentation/devicetree/bindings/axisfifo.txt | 89 ++ > > > > > > This should live in the directory with the driver until it gets > > > accepted into the "main" part of the kernel tree. > > > > > > > Ok will do. > > > > > > drivers/staging/axisfifo/axis-fifo.c | 1242 > > > > > > > > 2 files changed, 1331 insertions(+) > > > > create mode 100644 Documentation/devicetree/bindings/axisfifo.txt > > > > create mode 100644 drivers/staging/axisfifo/axis-fifo.c > > > > > > No Makefile or Kconfig to actually build the driver? > > > > > > Please fix that up so we can at least test-build the thing :) > > > > > > thanks, > > > > > > greg k-h > > > > Oh... how do I do that exactly? :) I am currently building it with > > Petalinux (Xilinx's wrapper for Yocto). I'm guessing there is a makefile > > somewhere in the Yocto directory I can give you? > > No, it needs to be in the directory of the driver itself. Look at how > all of the other drivers/staging/*/Makefile look, same for Kconfig. If > you need help, just ask and I can easily make one up for you. > > thanks, > > greg k-h I'll give it a shot. Thanks, Jacob ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [RFC PATCH v2] Xilinx AXI-Stream FIFO v4.1 IP core driver
On Sun, Jul 15, 2018 at 09:44:58PM +0200, Greg KH wrote: > On Sun, Jul 15, 2018 at 12:34:28PM -0400, Jacob Feder wrote: > > Hi, > > I have updated this with the recommended changes. I haven't tried out the > > UIO though. It will be a pretty significant undertaking and I don't want > > to spend the time on it unless there is a specific reason you think it > > will be faster. > > > > Thanks all. > > > > Cheers, > > Jacob > > > > This IP core has read and write AXI-Stream FIFOs, the contents of which can > > be accessed from the AXI4 memory-mapped interface. This is useful for > > transferring data from a processor into the FPGA fabric. The driver creates > > a character device that can be read/written to with standard > > open/read/write/close. > > > > See Xilinx PG080 document for IP details. > > > > https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf > > > > The driver currently supports only store-forward mode with a 32-bit > > AXI4 Lite interface. DOES NOT support: > > - cut-through mode > > - AXI4 (non-lite) > > > > Signed-off-by: Jacob Feder > > --- > > Documentation/devicetree/bindings/axisfifo.txt | 89 ++ > > This should live in the directory with the driver until it gets > accepted into the "main" part of the kernel tree. > Ok will do. > > drivers/staging/axisfifo/axis-fifo.c | 1242 > > > > 2 files changed, 1331 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/axisfifo.txt > > create mode 100644 drivers/staging/axisfifo/axis-fifo.c > > No Makefile or Kconfig to actually build the driver? > > Please fix that up so we can at least test-build the thing :) > > thanks, > > greg k-h Oh... how do I do that exactly? :) I am currently building it with Petalinux (Xilinx's wrapper for Yocto). I'm guessing there is a makefile somewhere in the Yocto directory I can give you? Thanks, Jacob ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[RFC PATCH v2] Xilinx AXI-Stream FIFO v4.1 IP core driver
Hi,
I have updated this with the recommended changes. I haven't tried out the
UIO though. It will be a pretty significant undertaking and I don't want
to spend the time on it unless there is a specific reason you think it
will be faster.
Thanks all.
Cheers,
Jacob
This IP core has read and write AXI-Stream FIFOs, the contents of which can
be accessed from the AXI4 memory-mapped interface. This is useful for
transferring data from a processor into the FPGA fabric. The driver creates
a character device that can be read/written to with standard
open/read/write/close.
See Xilinx PG080 document for IP details.
https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf
The driver currently supports only store-forward mode with a 32-bit
AXI4 Lite interface. DOES NOT support:
- cut-through mode
- AXI4 (non-lite)
Signed-off-by: Jacob Feder
---
Documentation/devicetree/bindings/axisfifo.txt | 89 ++
drivers/staging/axisfifo/axis-fifo.c | 1242
2 files changed, 1331 insertions(+)
create mode 100644 Documentation/devicetree/bindings/axisfifo.txt
create mode 100644 drivers/staging/axisfifo/axis-fifo.c
diff --git a/Documentation/devicetree/bindings/axisfifo.txt
b/Documentation/devicetree/bindings/axisfifo.txt
new file mode 100644
index 000..cd9bc69
--- /dev/null
+++ b/Documentation/devicetree/bindings/axisfifo.txt
@@ -0,0 +1,89 @@
+Xilinx AXI-Stream FIFO v4.1 IP core
+
+This IP core has read and write AXI-Stream FIFOs, the contents of which can
+be accessed from the AXI4 memory-mapped interface. This is useful for
+transferring data from a processor into the FPGA fabric. The driver creates
+a character device that can be read/written to with standard
+open/read/write/close.
+
+See Xilinx PG080 document for IP details.
+
+Currently supports only store-forward mode with a 32-bit
+AXI4-Lite interface. DOES NOT support:
+ - cut-through mode
+ - AXI4 (non-lite)
+
+Required properties:
+- compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
+- interrupt-names: Should be "interrupt"
+- interrupt-parent: Should be <>
+- interrupts: Should contain interrupts lines.
+- reg: Should contain registers location and length.
+- xlnx,axi-str-rxd-protocol: Should be "XIL_AXI_STREAM_ETH_DATA"
+- xlnx,axi-str-rxd-tdata-width: Should be <0x20>
+- xlnx,axi-str-txc-protocol: Should be "XIL_AXI_STREAM_ETH_CTRL"
+- xlnx,axi-str-txc-tdata-width: Should be <0x20>
+- xlnx,axi-str-txd-protocol: Should be "XIL_AXI_STREAM_ETH_DATA"
+- xlnx,axi-str-txd-tdata-width: Should be <0x20>
+- xlnx,axis-tdest-width: AXI-Stream TDEST width
+- xlnx,axis-tid-width: AXI-Stream TID width
+- xlnx,axis-tuser-width: AXI-Stream TUSER width
+- xlnx,data-interface-type: Should be <0x0>
+- xlnx,has-axis-tdest: Should be <0x0> (this feature isn't supported)
+- xlnx,has-axis-tid: Should be <0x0> (this feature isn't supported)
+- xlnx,has-axis-tkeep: Should be <0x0> (this feature isn't supported)
+- xlnx,has-axis-tstrb: Should be <0x0> (this feature isn't supported)
+- xlnx,has-axis-tuser: Should be <0x0> (this feature isn't supported)
+- xlnx,rx-fifo-depth: Depth of RX FIFO in words
+- xlnx,rx-fifo-pe-threshold: RX programmable empty interrupt threshold
+- xlnx,rx-fifo-pf-threshold: RX programmable full interrupt threshold
+- xlnx,s-axi-id-width: Should be <0x4>
+- xlnx,s-axi4-data-width: Should be <0x20>
+- xlnx,select-xpm: Should be <0x0>
+- xlnx,tx-fifo-depth: Depth of TX FIFO in words
+- xlnx,tx-fifo-pe-threshold: TX programmable empty interrupt threshold
+- xlnx,tx-fifo-pf-threshold: TX programmable full interrupt threshold
+- xlnx,use-rx-cut-through: Should be <0x0> (this feature isn't supported)
+- xlnx,use-rx-data: <0x1> if RX FIFO is enabled, <0x0> otherwise
+- xlnx,use-tx-ctrl: Should be <0x0> (this feature isn't supported)
+- xlnx,use-tx-cut-through: Should be <0x0> (this feature isn't supported)
+- xlnx,use-tx-data: <0x1> if TX FIFO is enabled, <0x0> otherwise
+
+Example:
+
+axi_fifo_mm_s_0: axi_fifo_mm_s@43c0 {
+ compatible = "xlnx,axi-fifo-mm-s-4.1";
+ interrupt-names = "interrupt";
+ interrupt-parent = <>;
+ interrupts = <0 29 4>;
+ reg = <0x43c0 0x1>;
+ xlnx,axi-str-rxd-protocol = "XIL_AXI_STREAM_ETH_DATA";
+ xlnx,axi-str-rxd-tdata-width = <0x20>;
+ xlnx,axi-str-txc-protocol = "XIL_AXI_STREAM_ETH_CTRL";
+ xlnx,axi-str-txc-tdata-width = <0x20>;
+ xlnx,axi-str-txd-protocol = "XIL_AXI_STREAM_ETH_DATA";
+ xlnx,axi-str-txd-tdata-width = <0x20>;
+ xlnx,axis-tdest-width = <0x4>;
+ xlnx,axis-tid-width = <0x4>;
+ xlnx,axis-tuser-width = <0x4>;
+ xlnx,data-interface-t
Re: [RFC PATCH v1] Xilinx AXI-Stream FIFO v4.1 IP core driver
On Mon, Jul 09, 2018 at 05:25:21PM +0300, Dan Carpenter wrote:
> On Sat, Jul 07, 2018 at 10:19:40PM -0400, Jacob Feder wrote:
> > +static ssize_t sysfs_write(struct device *dev, const char *buf,
> > + size_t count, unsigned int addr_offset)
> > +{
> > + struct axis_fifo_local *device_wrapper = dev_get_drvdata(dev);
>
> What does the "local" mean in axis_fifo_local? "device_wrapper" is a
> weird name. It's sort of long but also meaningless and or confusing.
> What kind of device? What is it wrapping? How is it not a fifo? And
> because it's a bit long then we run into the 80 character limit. Maybe
> just say "struct axis_fifo_local *fifo;"?
fixed
>
> > +
> > + if (!mutex_trylock(_wrapper->write_mutex)) {
> > + dev_err(device_wrapper->os_device,
> > + "couldn't acquire write lock\n");
> > + return -EBUSY;
> > + }
>
> Greg has said to remove this.
>
fixed
> > +
> > + if (!mutex_trylock(_wrapper->read_mutex)) {
> > + dev_err(device_wrapper->os_device,
> > + "couldn't acquire read lock\n");
> > + mutex_unlock(_wrapper->write_mutex);
> > + dev_dbg(device_wrapper->os_device, "released write lock\n");
> > + return -EBUSY;
> > + }
> > +
> > + dev_dbg(device_wrapper->os_device, "acquired locks\n");
>
> Remove this, because it's related to locks. Also you can get this info
> from ftrace. The extra debug code just obscures the interest parts of
> the code because there is too much debugging.
>
> ->os_device is a bad name, because there isn't an operating system
> device. What does that even mean?
>
fixed
> > +
> > + if (count != 4) {
>
> Remove the magic number. Just say sizeof(u32).
>
fixed
> > + dev_err(device_wrapper->os_device,
> > + "error, sysfs write to address 0x%x expected 4 bytes\n",
> > + addr_offset);
> > + mutex_unlock(_wrapper->write_mutex);
> > + mutex_unlock(_wrapper->read_mutex);
>
> Don't let user space spam /var/log messages. Just return -EINVAL;
>
fixed
> > + return -EINVAL;
> > + }
> > +
> > + dev_dbg(device_wrapper->os_device,
> > + "writing 0x%x to sysfs address 0x%x\n",
> > + *(unsigned int *)buf, addr_offset);
> > + iowrite32(*(unsigned int __force *)buf,
>
> __force is for when you're casting to and from __user types. It's not
> required here.
>
fixed
> > + device_wrapper->base_addr + addr_offset);
> > + mutex_unlock(_wrapper->write_mutex);
> > + mutex_unlock(_wrapper->read_mutex);
> > + dev_dbg(device_wrapper->os_device, "released locks\n");
>
> ftrace.
>
> > +
> > + return 4;
>
> This is a magic number. Use "return count;" instead.
>
fixed
> > +}
>
> So now it's:
>
> static ssize_t sysfs_write(struct device *dev, const char *buf,
> size_t count, unsigned int addr_offset)
> {
> struct axis_fifo_local *fifo = dev_get_drvdata(dev);
>
> if (count != sizeof(u32))
> return -EINVAL;
>
> iowrite32(*(u32 *)buf, fifo->base_addr + addr_offset);
>
> return count;
> }
>
> Sysfs files are supposed to be human readable text files so I don't
> feel like casting *(u32 *)buf is the right thing. In other words you do
> echo "1234" > /sys/whatever. What are we trying to write here?
> Normally we would use kstrotul() and write the value that
> way.
>
fixed
> > +// reads a single packet from the fifo as dictated by the tlast signal
>
> Please use /* */ style comments.
>
fixed
> > +static ssize_t axis_fifo_read(struct file *device_file, char __user *buf,
> > + size_t len, loff_t *off)
> > +{
> > + struct axis_fifo_local *device_wrapper =
> > + (struct axis_fifo_local *)device_file->private_data;
> > + unsigned int bytes_available;
> > + unsigned int words_available;
> > + unsigned int word;
> > + unsigned int buff_word;
>
> One f in buf. Otherwise it means a person who works out a lot. This
> is just an iterator. "int i;"
>
fixed
> > + int wait_ret;
>
> Just say "int ret;"
>
fixed
> > + u32 read_buff[READ_BUFF_SIZE];
> > +
> &g
Re: [RFC PATCH v1] Xilinx AXI-Stream FIFO v4.1 IP core driver
On Mon, Jul 09, 2018 at 09:43:28AM +0200, Greg KH wrote: > On Sun, Jul 08, 2018 at 02:25:38PM -0400, jacob feder wrote: > > On Sun, Jul 8, 2018 at 9:28 AM Greg KH wrote: > > > > On Sat, Jul 07, 2018 at 10:19:40PM -0400, Jacob Feder wrote: > > > Hi all, > > > I have developed this driver for a Xilinx-provided IP block for their > > Zynq > > > SoC. I fixed all of the checkpatch.pl problems I knew how to. If > > someone > > > could chime in on how to fix the remaining few it would be > > appreciated. > > > > > > Also looking for feedback on general structure. It's my first driver > > (and > > > patch submission) so I'm sure there are plenty of things to be > > improved > > on > > > :). > > > > > > Functionally everything works OK except the performance isn't as good > > as > > I > > > was hoping for. I have been testing it by operating the FIFO in > > loopback > > > mode (AXI-Stream TX interface feeding back into RX interface) running > > on > > > the XC7Z020 (7000 series) Zynq device. I am getting anything between > > > 3-16MB/s depending on the amount of data transferred. The performance > > > claimed by the PG080 datasheet is ~65MB/s. The CPU isn't under > > significant > > > load (~12%) as reported by top so I don't think that's the bottleneck. > > > > > > Please +CC in responses as I'm not on the mailing list. > > > > > > Cheers > > > > > > > > > This IP core has read and write AXI-Stream FIFOs, the contents of > > which > > can > > > be accessed from the AXI4 memory-mapped interface. This is useful for > > > transferring data from a processor into the FPGA fabric. The driver > > creates > > > a character device that can be read/written to with standard > > > open/read/write/close. > > > > Why not use the uio api, which allows userspace to mmap the memory of > > the device and access it directly from userspace? That should make > > things a lot faster, right? > > > > > > > > I thought about the UIO method but based on what I read it seemed like more > > of > > a hack (and also doesn't expose interrupts?). Whether it would make > > things faster I have no idea. > > Directly mmap is faster than read/write in a serial way, right? I'm not sure - to me it seems the same unless mmap is using a different technique under the hood. With mmap you would still need to write serially to the FIFO registers. E.g. you can't write the data to a block of memory. It all has to go to the same spot (TDFD register or RDFD for reading). > > > > > Or if that doesn't work, what about the fpga API the kernel now has? > > Would that work for this hardware? > > > > > > > > I'm not totally sure what you're referring to here, but I think the FPGA > > kernel > > drivers are for downloading bitstreams to the FPGA (bitstream is > > equivalent to asm for fpgas), which isn't what I'm trying to do. > > Ah, ok. > > > > > > > See Xilinx PG080 document for IP details. > > > > Do you have a link to that? If so, can you put it in here? > > > > > > > > https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/ > > v4_1/pg080-axi-fifo-mm-s.pdf > > Can you put this in the changelog message please? > Yes will do on v2. > > > Currently supports only store-forward mode with a 32-bit > > > AXI4-Lite interface. DOES NOT support: > > > - cut-through mode > > > - AXI4 (non-lite) > > > > > > Signed-off-by: Jacob Feder > > > --- > > > drivers/staging/axisfifo/axis-fifo.c | 1296 > > ++ > > > drivers/staging/axisfifo/axis-fifo.h | 119 > > > 2 files changed, 1415 insertions(+) > > > create mode 100644 drivers/staging/axisfifo/axis-fifo.c > > > create mode 100644 drivers/staging/axisfifo/axis-fifo.h > > > > Why does a single .c file need a .h file? > > > > > > > > Good point... this can be consolidated :) > > > > > > I'll be glad to take this driver, as others can clean it up in-tree (I > > think your locking is crazy and is probably causing a lot of performance > > issues), but
Re: [RFC PATCH v1] Xilinx AXI-Stream FIFO v4.1 IP core driver
On Sun, Jul 08, 2018 at 03:28:16PM +0200, Greg KH wrote: > On Sat, Jul 07, 2018 at 10:19:40PM -0400, Jacob Feder wrote: > > Hi all, > > I have developed this driver for a Xilinx-provided IP block for their Zynq > > SoC. I fixed all of the checkpatch.pl problems I knew how to. If someone > > could chime in on how to fix the remaining few it would be appreciated. > > > > Also looking for feedback on general structure. It's my first driver (and > > patch submission) so I'm sure there are plenty of things to be improved on > > :). > > > > Functionally everything works OK except the performance isn't as good as I > > was hoping for. I have been testing it by operating the FIFO in loopback > > mode (AXI-Stream TX interface feeding back into RX interface) running on > > the XC7Z020 (7000 series) Zynq device. I am getting anything between > > 3-16MB/s depending on the amount of data transferred. The performance > > claimed by the PG080 datasheet is ~65MB/s. The CPU isn't under significant > > load (~12%) as reported by top so I don't think that's the bottleneck. > > > > Please +CC in responses as I'm not on the mailing list. > > > > Cheers > > > > > > This IP core has read and write AXI-Stream FIFOs, the contents of which can > > be accessed from the AXI4 memory-mapped interface. This is useful for > > transferring data from a processor into the FPGA fabric. The driver creates > > a character device that can be read/written to with standard > > open/read/write/close. > > Why not use the uio api, which allows userspace to mmap the memory of > the device and access it directly from userspace? That should make > things a lot faster, right? I thought about the UIO method but based on what I read it seemed like more of a hack (and also doesn't expose interrupts?). Whether it would make things faster I have no idea. > > Or if that doesn't work, what about the fpga API the kernel now has? > Would that work for this hardware? > I'm not totally sure what you're referring to here, but I think the FPGA kernel drivers are for downloading bitstreams to the FPGA (bitstream is equivalent to asm for fpgas), which isn't what I'm trying to do. > > > > > See Xilinx PG080 document for IP details. > > Do you have a link to that? If so, can you put it in here? > https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf > > > > Currently supports only store-forward mode with a 32-bit > > AXI4-Lite interface. DOES NOT support: > > - cut-through mode > > - AXI4 (non-lite) > > > > Signed-off-by: Jacob Feder > > --- > > drivers/staging/axisfifo/axis-fifo.c | 1296 > > ++ > > drivers/staging/axisfifo/axis-fifo.h | 119 > > 2 files changed, 1415 insertions(+) > > create mode 100644 drivers/staging/axisfifo/axis-fifo.c > > create mode 100644 drivers/staging/axisfifo/axis-fifo.h > > Why does a single .c file need a .h file? Good point... this can be consolidated :) > > I'll be glad to take this driver, as others can clean it up in-tree (I > think your locking is crazy and is probably causing a lot of performance > issues), but I need a TODO file for it listing what you think is needed > to do in order to get this out of the staging tree? I'm confused about why you don't like the locking - all I'm doing is locking on open() calls to prevent multiple userspace apps from reading/writing to the fifo simultaneously. This shouldn't reduce performance because the mutexes are only tested on open() not on read() or write(). Presumably the user is only opening once. I think locking is necessary - if the hardware registers are accessed in the wrong order it goes into an unknown state and must be reset (and will probably cause a kernel panic). > > Or, if you thin it should use the fpga or uio interface instead, maybe > it's just easier to redo it based on that? > > thanks, > > greg k-h I have made some slight modifications today. Let me know if there are any other things you think I should change. I can integrate those then resubmit a v2 for you to bring into the tree. In terms of TODO it's all ok as far as I'm concerned unless someone wants to look into the performance. (actually see below - I think this could explain why performance of my system is lower - xilinx is using some sort of DMA driver instead of io_remap) https://forums.xilinx.com/xlnx/attachments/xlnx/ELINUX/13011/2/Linux-DMA-In-Device-Drivers.pdf Thanks!! Cheers, Jacob ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[RFC PATCH v1] Xilinx AXI-Stream FIFO v4.1 IP core driver
Hi all,
I have developed this driver for a Xilinx-provided IP block for their Zynq
SoC. I fixed all of the checkpatch.pl problems I knew how to. If someone
could chime in on how to fix the remaining few it would be appreciated.
Also looking for feedback on general structure. It's my first driver (and
patch submission) so I'm sure there are plenty of things to be improved on
:).
Functionally everything works OK except the performance isn't as good as I
was hoping for. I have been testing it by operating the FIFO in loopback
mode (AXI-Stream TX interface feeding back into RX interface) running on
the XC7Z020 (7000 series) Zynq device. I am getting anything between
3-16MB/s depending on the amount of data transferred. The performance
claimed by the PG080 datasheet is ~65MB/s. The CPU isn't under significant
load (~12%) as reported by top so I don't think that's the bottleneck.
Please +CC in responses as I'm not on the mailing list.
Cheers
This IP core has read and write AXI-Stream FIFOs, the contents of which can
be accessed from the AXI4 memory-mapped interface. This is useful for
transferring data from a processor into the FPGA fabric. The driver creates
a character device that can be read/written to with standard
open/read/write/close.
See Xilinx PG080 document for IP details.
Currently supports only store-forward mode with a 32-bit
AXI4-Lite interface. DOES NOT support:
- cut-through mode
- AXI4 (non-lite)
Signed-off-by: Jacob Feder
---
drivers/staging/axisfifo/axis-fifo.c | 1296 ++
drivers/staging/axisfifo/axis-fifo.h | 119
2 files changed, 1415 insertions(+)
create mode 100644 drivers/staging/axisfifo/axis-fifo.c
create mode 100644 drivers/staging/axisfifo/axis-fifo.h
diff --git a/drivers/staging/axisfifo/axis-fifo.c
b/drivers/staging/axisfifo/axis-fifo.c
new file mode 100644
index 000..a61f22b
--- /dev/null
+++ b/drivers/staging/axisfifo/axis-fifo.c
@@ -0,0 +1,1296 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core
+ *
+ * Copyright (C) 2018 Jacob Feder
+ *
+ * Authors: Jacob Feder
+ *
+ * See Xilinx PG080 document for IP details
+ */
+
+/*
+ * includes
+ *
+ */
+
+#include "axis-fifo.h"
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+/*
+ * globals
+ *
+ */
+
+static unsigned int num_fifo_devices; /* number of initialized devices */
+static struct mutex num_fifo_devices_mutex; /* mutex for num_fifo_devices */
+
+static int read_timeout = 1000; /* ms to wait before read() times out */
+static int write_timeout = 1000; /* ms to wait before write() times out */
+
+/*
+ * module command-line arguments
+ *
+ */
+
+module_param(read_timeout, int, 0444);
+MODULE_PARM_DESC(read_timeout, "ms to wait before blocking read() timing out;
set to -1 for no timeout");
+module_param(write_timeout, int, 0444);
+MODULE_PARM_DESC(write_timeout, "ms to wait before blocking write() timing
out; set to -1 for no timeout");
+
+/*
+ * sysfs entries
+ *
+ */
+
+static ssize_t sysfs_write(struct device *dev, const char *buf,
+ size_t count, unsigned int addr_offset)
+{
+ struct axis_fifo_local *device_wrapper = dev_get_drvdata(dev);
+
+ if (!mutex_trylock(_wrapper->write_mutex)) {
+ dev_err(device_wrapper->os_device,
+ "couldn't acquire write lock\n");
+ return -EBUSY;
+ }
+
+ if (!mutex_trylock(_wrapper->read_mutex)) {
+ dev_err(device_wrapper->os_device,
+ "couldn't acquire read lock\n");
+ mutex_unlock(_wrapper->write_mutex);
+ dev_dbg(device_wrapper->os_device, "released write lock\n");
+ return -EBUSY;
+ }
+
+ dev_dbg(device_wrapper->os_device, "acquired locks\n");
+
+ if (count != 4) {
+ dev_err(device_wrapper->os_device,
+ "error, sysfs write to address 0x%x expected 4 bytes\n",
+ addr_offset);
+ mutex_unlock(_wrapper->write_mutex);
+ mutex_unlock(_wrapper->read_mutex);
+ return -EINVAL;
+ }
+
+ dev_dbg(device_wrapper->os_device,
+ "writing 0x%x to sysfs address 0x%x\n",
+ *(unsigned int *)buf, addr_offset);
+ iowrite32(*(unsigned int __force *)buf,
+ device_wrapper->base_addr + addr_offset);
+ mutex_unlock(_w
