Fix a lot of checkpath errors of the type:
-CHECK: spaces preferred around that
-CHECK: Alignment should match open parenthesis
Signed-off-by: Jose Carlos Cazarin Filho
---
My second commit to the kernel, I know you ppl don't like these kind of commits
fixing style-only erros pointed by the checkpath, but I'm doing this just to
learn
Thanks!
drivers/staging/rtl8188eu/hal/phy.c | 54 ++---
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/staging/rtl8188eu/hal/phy.c
b/drivers/staging/rtl8188eu/hal/phy.c
index 51c40abfa..f0d242dec 100644
--- a/drivers/staging/rtl8188eu/hal/phy.c
+++ b/drivers/staging/rtl8188eu/hal/phy.c
@@ -52,7 +52,7 @@ void phy_set_bb_reg(struct adapter *adapt, u32 regaddr, u32
bitmask, u32 data)
}
static u32 rf_serial_read(struct adapter *adapt,
- enum rf_radio_path rfpath, u32 offset)
+ enum rf_radio_path rfpath, u32 offset)
{
u32 ret = 0;
struct bb_reg_def *phyreg = >HalData->PHYRegDef[rfpath];
@@ -69,10 +69,10 @@ static u32 rf_serial_read(struct adapter *adapt,
bMaskDWord);
tmplong2 = (tmplong2 & (~bLSSIReadAddress)) |
- (offset<<23) | bLSSIReadEdge;
+ (offset << 23) | bLSSIReadEdge;
phy_set_bb_reg(adapt, rFPGA0_XA_HSSIParameter2, bMaskDWord,
- tmplong&(~bLSSIReadEdge));
+ tmplong & (~bLSSIReadEdge));
udelay(10);
phy_set_bb_reg(adapt, phyreg->rfHSSIPara2, bMaskDWord, tmplong2);
@@ -102,12 +102,12 @@ static void rf_serial_write(struct adapter *adapt,
struct bb_reg_def *phyreg = >HalData->PHYRegDef[rfpath];
offset &= 0xff;
- data_and_addr = ((offset<<20) | (data&0x000f)) & 0x0fff;
+ data_and_addr = ((offset << 20) | (data & 0x000f)) & 0x0fff;
phy_set_bb_reg(adapt, phyreg->rf3wireOffset, bMaskDWord, data_and_addr);
}
u32 rtw_hal_read_rfreg(struct adapter *adapt, enum rf_radio_path rf_path,
-u32 reg_addr, u32 bit_mask)
+ u32 reg_addr, u32 bit_mask)
{
u32 original_value, bit_shift;
@@ -117,7 +117,7 @@ u32 rtw_hal_read_rfreg(struct adapter *adapt, enum
rf_radio_path rf_path,
}
void phy_set_rf_reg(struct adapter *adapt, enum rf_radio_path rf_path,
-u32 reg_addr, u32 bit_mask, u32 data)
+ u32 reg_addr, u32 bit_mask, u32 data)
{
u32 original_value, bit_shift;
@@ -143,20 +143,20 @@ static void get_tx_power_index(struct adapter *adapt, u8
channel, u8 *cck_pwr,
for (TxCount = 0; TxCount < path_nums; TxCount++) {
if (TxCount == RF_PATH_A) {
cck_pwr[TxCount] =
hal_data->Index24G_CCK_Base[TxCount][index];
- ofdm_pwr[TxCount] =
hal_data->Index24G_BW40_Base[RF_PATH_A][index]+
+ ofdm_pwr[TxCount] =
hal_data->Index24G_BW40_Base[RF_PATH_A][index] +
hal_data->OFDM_24G_Diff[TxCount][RF_PATH_A];
- bw20_pwr[TxCount] =
hal_data->Index24G_BW40_Base[RF_PATH_A][index]+
+ bw20_pwr[TxCount] =
hal_data->Index24G_BW40_Base[RF_PATH_A][index] +
hal_data->BW20_24G_Diff[TxCount][RF_PATH_A];
bw40_pwr[TxCount] =
hal_data->Index24G_BW40_Base[TxCount][index];
} else if (TxCount == RF_PATH_B) {
cck_pwr[TxCount] =
hal_data->Index24G_CCK_Base[TxCount][index];
- ofdm_pwr[TxCount] =
hal_data->Index24G_BW40_Base[RF_PATH_A][index]+
- hal_data->BW20_24G_Diff[RF_PATH_A][index]+
+ ofdm_pwr[TxCount] =
hal_data->Index24G_BW40_Base[RF_PATH_A][index] +
+ hal_data->BW20_24G_Diff[RF_PATH_A][index] +
hal_data->BW20_24G_Diff[TxCount][index];
- bw20_pwr[TxCount] =
hal_data->Index24G_BW40_Base[RF_PATH_A][index]+
- hal_data->BW20_24G_Diff[TxCount][RF_PATH_A]+
+ bw20_pwr[TxCount] =
hal_data->Index24G_BW40_Base[RF_PATH_A][index] +
+ hal_data->BW20_24G_Diff[TxCount][RF_PATH_A] +
hal_data->BW20_24G_Diff[TxCount][index];
bw40_pwr[TxCount] =
hal_data->Index24G_BW40_Base[TxCount][index];
}
@@ -190,7 +190,7 @@ void phy_set_tx_power_level(struct adapter *adapt, u8
channel)
rtl88eu_phy_rf6052_set_cck_txpower(adapt, _pwr[0]);
rtl88eu_phy_rf6052_set_ofdm_txpower(adapt, _pwr[0], _pwr[0],
- _pwr[0], channel);
+