Re: [PATCH v7 0/7] clk: clk-wizard: clock-wizard: Driver updates
Hi Shubhrajyoti, Shubhrajyoti Datta wrote on Wed, 4 Nov 2020 20:36:40 +0530: > In the thread [1] Greg suggested that we move the driver > to the clk from the staging. > Add patches to address the concerns regarding the fractional and > set rate support in the TODO. > > The patch set does the following > - Trivial fixes for kernel doc. > - Move the driver to the clk folder > - Add capability to set rate. > - Add fractional support. > - Add support for configurable outputs. > - Make the output names unique so that multiple instances > do not crib. Can someone tell me the status of this series? I think it would benefit everyone to have this driver "officially" supported in the main tree, unless there are crucial issues; in this case it might be good to know which ones? Thanks, Miquèl ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH] docs: dt: fix several broken doc references
Hi Mauro, Mauro Carvalho Chehab wrote on Sun, 23 Feb 2020 09:59:53 +0100: > There are several DT doc references that require manual fixes. > I found 3 cases fixed on this patch: > > - directory named "binding/" instead of "bindings/"; > - .txt to .yaml renames; > - file renames (still on txt format); > > Signed-off-by: Mauro Carvalho Chehab > --- > .../devicetree/bindings/mtd/cadence-nand-controller.txt | 2 +- > .../devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt | 2 +- > Documentation/devicetree/bindings/sound/st,stm32-sai.txt | 2 +- > Documentation/devicetree/bindings/sound/st,stm32-spdifrx.txt | 2 +- > Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 2 +- > MAINTAINERS | 4 ++-- > .../devicetree/bindings/net/wireless/siliabs,wfx.txt | 2 +- > 7 files changed, 8 insertions(+), 8 deletions(-) For the Cadence file, Reviewed-by: Miquel Raynal Thanks, Miquèl ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH] staging: Remove the mt29f_spinand driver
Hi Greg, Greg Kroah-Hartman wrote on Mon, 5 Nov 2018 15:34:33 +0100: > On Mon, Nov 05, 2018 at 03:27:34PM +0100, Miquel Raynal wrote: > > Hi Greg, > > > > Greg Kroah-Hartman wrote on Mon, 5 Nov > > 2018 14:29:49 +0100: > > > > > On Mon, Nov 05, 2018 at 11:12:27AM +0100, Miquel Raynal wrote: > > > > Hi Greg, > > > > > > > > Boris Brezillon wrote on Mon, 22 Oct 2018 > > > > 22:10:59 +0200: > > > > > > > > > A new SPI NAND subsystem has been added in drivers/mtd/nand/spi/ and > > > > > Micron's MT29F devices are now supported in > > > > > drivers/mtd/nand/spi/micron.c. > > > > > > > > > > Remove the old driver. > > > > > > > > > > Signed-off-by: Boris Brezillon > > > > > --- > > > > > Hello, > > > > > > > > > > If anything is missing in drivers/mtd/nand/spi/micron.c to properly > > > > > support the devices supported by the mt29f_spinand driver, please let > > > > > me know. > > > > > I might accept to delay removal of this driver if I have some > > > > > guarantees > > > > > that existing users will actually switch to the new driver at some > > > > > point. > > > > > > > > > > Regards, > > > > > > > > > > Boris > > > > > --- > > > > > > > > I plan to apply this patch but I would like your approval first. > > > > > > > > As a summary, the mt29f_spinand driver is a Micron SPI NAND chip > > > > driver interfacing with the raw NAND API (which is 'wrong'). > > > > > > > > Boris has recently contributed a SPI NAND framework supporting SPI > > > > NAND chips from several vendors, including Micron, that is supposed to > > > > take over this driver. > > > > > > > > Do you see anything that should prevent us to remove it now? > > > > > > Not at all, I was going to add this patch to my tree right now, as I > > > couldn't do anything until after 4.20-rc1 was out. Any objection from > > > me just taking it that way and getting it into 4.20-final? > > > > I'm fine with you taking it but I have changes in the pipe that are > > impacted by this removal so it would be great if this could happen > > pretty early in the 4.20 release cycle (4.20-rc2?), so I will still be > > able to base nand/next on top of it. > > If you need to work on top of this, please take it through your tree and > feel free to add: > > Acked-by: Greg Kroah-Hartman > > That way I'm not holding up any work from anyone else. Sure, patch applied (nand/next). Thanks, Miquèl ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH] staging: Remove the mt29f_spinand driver
Hi Greg, Greg Kroah-Hartman wrote on Mon, 5 Nov 2018 14:29:49 +0100: > On Mon, Nov 05, 2018 at 11:12:27AM +0100, Miquel Raynal wrote: > > Hi Greg, > > > > Boris Brezillon wrote on Mon, 22 Oct 2018 > > 22:10:59 +0200: > > > > > A new SPI NAND subsystem has been added in drivers/mtd/nand/spi/ and > > > Micron's MT29F devices are now supported in > > > drivers/mtd/nand/spi/micron.c. > > > > > > Remove the old driver. > > > > > > Signed-off-by: Boris Brezillon > > > --- > > > Hello, > > > > > > If anything is missing in drivers/mtd/nand/spi/micron.c to properly > > > support the devices supported by the mt29f_spinand driver, please let > > > me know. > > > I might accept to delay removal of this driver if I have some guarantees > > > that existing users will actually switch to the new driver at some > > > point. > > > > > > Regards, > > > > > > Boris > > > --- > > > > I plan to apply this patch but I would like your approval first. > > > > As a summary, the mt29f_spinand driver is a Micron SPI NAND chip > > driver interfacing with the raw NAND API (which is 'wrong'). > > > > Boris has recently contributed a SPI NAND framework supporting SPI > > NAND chips from several vendors, including Micron, that is supposed to > > take over this driver. > > > > Do you see anything that should prevent us to remove it now? > > Not at all, I was going to add this patch to my tree right now, as I > couldn't do anything until after 4.20-rc1 was out. Any objection from > me just taking it that way and getting it into 4.20-final? I'm fine with you taking it but I have changes in the pipe that are impacted by this removal so it would be great if this could happen pretty early in the 4.20 release cycle (4.20-rc2?), so I will still be able to base nand/next on top of it. Thanks, Miquèl ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH] staging: Remove the mt29f_spinand driver
Hi Greg, Boris Brezillon wrote on Mon, 22 Oct 2018 22:10:59 +0200: > A new SPI NAND subsystem has been added in drivers/mtd/nand/spi/ and > Micron's MT29F devices are now supported in > drivers/mtd/nand/spi/micron.c. > > Remove the old driver. > > Signed-off-by: Boris Brezillon > --- > Hello, > > If anything is missing in drivers/mtd/nand/spi/micron.c to properly > support the devices supported by the mt29f_spinand driver, please let > me know. > I might accept to delay removal of this driver if I have some guarantees > that existing users will actually switch to the new driver at some > point. > > Regards, > > Boris > --- I plan to apply this patch but I would like your approval first. As a summary, the mt29f_spinand driver is a Micron SPI NAND chip driver interfacing with the raw NAND API (which is 'wrong'). Boris has recently contributed a SPI NAND framework supporting SPI NAND chips from several vendors, including Micron, that is supposed to take over this driver. Do you see anything that should prevent us to remove it now? > drivers/staging/Kconfig | 2 - > drivers/staging/Makefile | 1 - > drivers/staging/mt29f_spinand/Kconfig | 16 - > drivers/staging/mt29f_spinand/Makefile| 1 - > drivers/staging/mt29f_spinand/TODO| 13 - > drivers/staging/mt29f_spinand/mt29f_spinand.c | 980 -- > drivers/staging/mt29f_spinand/mt29f_spinand.h | 106 -- > 7 files changed, 1119 deletions(-) > delete mode 100644 drivers/staging/mt29f_spinand/Kconfig > delete mode 100644 drivers/staging/mt29f_spinand/Makefile > delete mode 100644 drivers/staging/mt29f_spinand/TODO > delete mode 100644 drivers/staging/mt29f_spinand/mt29f_spinand.c > delete mode 100644 drivers/staging/mt29f_spinand/mt29f_spinand.h > Thanks, Miquèl ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
Re: [PATCH 00/19] mtd: rawnand: API cleanup (2nd batch)
Hi Boris,
Boris Brezillon wrote on Mon, 17 Sep 2018
10:29:39 +0200:
> On Sat, 15 Sep 2018 19:54:40 +0200
> Miquel Raynal wrote:
>
> > Hi Boris,
> >
> > Boris Brezillon wrote on Fri, 7 Sep 2018
> > 00:38:32 +0200:
> >
> > > Hello,
> > >
> > > This is the 2nd batch of API cleanup patches. This time we move
> > > deprecated hooks/fields to the nand_legacy struct, and then move some
> > > of the code found in nand_base.c into separate source/header files.
> > >
> > > With this new organization, new comers should more easily identify the
> > > bits they can use in their NAND controller drivers and those that are
> > > only meant for core code. It also shrink a bit nand_base.c which was
> > > over 6000 lines of code.
> > >
> > > Note that existing coding style issues (reported by checkpatch) in arch
> > > or driver code are intentionally not fixed to keep the series focused
> > > on the API/core cleanup.
> > >
> > > Regards,
> > >
> > > Boris
> > >
> > > Boris Brezillon (19):
> > > mtd: rawnand: Leave chip->IO_ADDR_{R,W} to NULL when unused
> > > mtd: rawnand: Create a legacy struct and move ->IO_ADDR_{R,W} there
> > > mtd: rawnand: Deprecate ->{read,write}_{byte,buf}() hooks
> > > mtd: rawnand: Deprecate ->cmd_ctrl() and ->cmdfunc()
> > > mtd: rawnand: Deprecate ->dev_ready() and ->waitfunc()
> > > mtd: rawnand: Deprecate ->block_{bad,markbad}() hooks
> > > mtd: rawnand: Deprecate ->erase()
> > > mtd: rawnand: Deprecate ->{set,get}_features() hooks
> > > mtd: rawnand: Deprecate ->chip_delay
> > > mtd: rawnand: Move function prototypes after struct declarations
> > > mtd: rawnand: Get rid of nand_flash_dev forward declation
> > > mtd: rawnand: Get rid of the duplicate nand_chip forward declaration
> > > mtd: rawnand: Get rid of a few unused definitions
> > > mtd: rawnand: Move platform_nand_xxx definitions out of rawnand.h
> > > mtd: rawnand: Inline onfi_get_async_timing_mode()
> > > mtd: rawnand: Keep all internal stuff private
> > > mtd: rawnand: Move legacy code to nand_legacy.c
> > > mtd: rawnand: Move ONFI code to nand_onfi.c
> > > mtd: rawnand: Move JEDEC code to nand_jedec.c
> > >
> > > Documentation/driver-api/mtdnand.rst | 30 +-
> > > arch/arm/mach-ep93xx/snappercl15.c |8 +-
> > > arch/arm/mach-ep93xx/ts72xx.c|9 +-
> > > arch/arm/mach-imx/mach-qong.c|6 +-
> > > arch/arm/mach-ixp4xx/ixdp425-setup.c |2 +-
> > > arch/arm/mach-omap1/board-fsample.c |3 +-
> > > arch/arm/mach-omap1/board-h2.c |3 +-
> > > arch/arm/mach-omap1/board-h3.c |2 +-
> > > arch/arm/mach-omap1/board-nand.c |2 +-
> > > arch/arm/mach-omap1/board-perseus2.c |3 +-
> > > arch/arm/mach-orion5x/ts78xx-setup.c |9 +-
> > > arch/arm/mach-pxa/balloon3.c |5 +-
> > > arch/arm/mach-pxa/em-x270.c |9 +-
> > > arch/arm/mach-pxa/palmtx.c |5 +-
> > > arch/mips/alchemy/devboards/db1200.c |9 +-
> > > arch/mips/alchemy/devboards/db1300.c |9 +-
> > > arch/mips/alchemy/devboards/db1550.c |9 +-
> > > arch/mips/netlogic/xlr/platform-flash.c |3 +-
> > > arch/mips/pnx833x/common/platform.c |5 +-
> > > arch/mips/rb532/devices.c|5 +-
> > > arch/sh/boards/mach-migor/setup.c|8 +-
> > > drivers/mtd/nand/raw/Makefile|4 +-
> > > drivers/mtd/nand/raw/ams-delta.c | 22 +-
> > > drivers/mtd/nand/raw/atmel/nand-controller.c | 22 +-
> > > drivers/mtd/nand/raw/au1550nd.c | 43 +-
> > > drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c | 22 +-
> > > drivers/mtd/nand/raw/brcmnand/brcmnand.c | 15 +-
> > > drivers/mtd/nand/raw/cafe_nand.c | 22 +-
> > > drivers/mtd/nand/raw/cmx270_nand.c | 28 +-
> > > drivers/mtd/nand/raw/cs553x_nand.c | 42 +-
> > > drivers/mtd/nand/raw/davinci_nand.c | 34 +-
> > > drivers/mtd/nand/raw/denali.c
Re: [PATCH 00/19] mtd: rawnand: API cleanup (2nd batch)
Hi Boris,
Boris Brezillon wrote on Fri, 7 Sep 2018
00:38:32 +0200:
> Hello,
>
> This is the 2nd batch of API cleanup patches. This time we move
> deprecated hooks/fields to the nand_legacy struct, and then move some
> of the code found in nand_base.c into separate source/header files.
>
> With this new organization, new comers should more easily identify the
> bits they can use in their NAND controller drivers and those that are
> only meant for core code. It also shrink a bit nand_base.c which was
> over 6000 lines of code.
>
> Note that existing coding style issues (reported by checkpatch) in arch
> or driver code are intentionally not fixed to keep the series focused
> on the API/core cleanup.
>
> Regards,
>
> Boris
>
> Boris Brezillon (19):
> mtd: rawnand: Leave chip->IO_ADDR_{R,W} to NULL when unused
> mtd: rawnand: Create a legacy struct and move ->IO_ADDR_{R,W} there
> mtd: rawnand: Deprecate ->{read,write}_{byte,buf}() hooks
> mtd: rawnand: Deprecate ->cmd_ctrl() and ->cmdfunc()
> mtd: rawnand: Deprecate ->dev_ready() and ->waitfunc()
> mtd: rawnand: Deprecate ->block_{bad,markbad}() hooks
> mtd: rawnand: Deprecate ->erase()
> mtd: rawnand: Deprecate ->{set,get}_features() hooks
> mtd: rawnand: Deprecate ->chip_delay
> mtd: rawnand: Move function prototypes after struct declarations
> mtd: rawnand: Get rid of nand_flash_dev forward declation
> mtd: rawnand: Get rid of the duplicate nand_chip forward declaration
> mtd: rawnand: Get rid of a few unused definitions
> mtd: rawnand: Move platform_nand_xxx definitions out of rawnand.h
> mtd: rawnand: Inline onfi_get_async_timing_mode()
> mtd: rawnand: Keep all internal stuff private
> mtd: rawnand: Move legacy code to nand_legacy.c
> mtd: rawnand: Move ONFI code to nand_onfi.c
> mtd: rawnand: Move JEDEC code to nand_jedec.c
>
> Documentation/driver-api/mtdnand.rst | 30 +-
> arch/arm/mach-ep93xx/snappercl15.c |8 +-
> arch/arm/mach-ep93xx/ts72xx.c|9 +-
> arch/arm/mach-imx/mach-qong.c|6 +-
> arch/arm/mach-ixp4xx/ixdp425-setup.c |2 +-
> arch/arm/mach-omap1/board-fsample.c |3 +-
> arch/arm/mach-omap1/board-h2.c |3 +-
> arch/arm/mach-omap1/board-h3.c |2 +-
> arch/arm/mach-omap1/board-nand.c |2 +-
> arch/arm/mach-omap1/board-perseus2.c |3 +-
> arch/arm/mach-orion5x/ts78xx-setup.c |9 +-
> arch/arm/mach-pxa/balloon3.c |5 +-
> arch/arm/mach-pxa/em-x270.c |9 +-
> arch/arm/mach-pxa/palmtx.c |5 +-
> arch/mips/alchemy/devboards/db1200.c |9 +-
> arch/mips/alchemy/devboards/db1300.c |9 +-
> arch/mips/alchemy/devboards/db1550.c |9 +-
> arch/mips/netlogic/xlr/platform-flash.c |3 +-
> arch/mips/pnx833x/common/platform.c |5 +-
> arch/mips/rb532/devices.c|5 +-
> arch/sh/boards/mach-migor/setup.c|8 +-
> drivers/mtd/nand/raw/Makefile|4 +-
> drivers/mtd/nand/raw/ams-delta.c | 22 +-
> drivers/mtd/nand/raw/atmel/nand-controller.c | 22 +-
> drivers/mtd/nand/raw/au1550nd.c | 43 +-
> drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c | 22 +-
> drivers/mtd/nand/raw/brcmnand/brcmnand.c | 15 +-
> drivers/mtd/nand/raw/cafe_nand.c | 22 +-
> drivers/mtd/nand/raw/cmx270_nand.c | 28 +-
> drivers/mtd/nand/raw/cs553x_nand.c | 42 +-
> drivers/mtd/nand/raw/davinci_nand.c | 34 +-
> drivers/mtd/nand/raw/denali.c| 23 +-
> drivers/mtd/nand/raw/diskonchip.c| 50 +-
> drivers/mtd/nand/raw/fsl_elbc_nand.c | 18 +-
> drivers/mtd/nand/raw/fsl_ifc_nand.c | 24 +-
> drivers/mtd/nand/raw/fsl_upm.c | 30 +-
> drivers/mtd/nand/raw/fsmc_nand.c |1 -
> drivers/mtd/nand/raw/gpio.c | 16 +-
> drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c | 22 +-
> drivers/mtd/nand/raw/hisi504_nand.c | 18 +-
> drivers/mtd/nand/raw/internals.h | 114 ++
> drivers/mtd/nand/raw/jz4740_nand.c | 14 +-
> drivers/mtd/nand/raw/jz4780_nand.c | 10 +-
> drivers/mtd/nand/raw/lpc32xx_mlc.c | 12 +-
> drivers/mtd/nand/raw/lpc32xx_slc.c | 26 +-
> drivers/mtd/nand/raw/mpc5121_nfc.c | 14 +-
> drivers/mtd/nand/raw/mtk_nand.c | 12 +-
> drivers/mtd/nand/raw/mxc_nand.c | 20 +-
> drivers/mtd/nand/raw/nand_amd.c |2 +-
> drivers/mtd/nand/raw/nand_base.c | 1260
> +++---
>
Re: [PATCH v2 00/23] mtd: rawnand: Stop passing mtd_info to drivers
Hi Boris,
Boris Brezillon wrote on Thu, 6 Sep 2018
14:05:12 +0200:
> Hello,
>
> This is the first set of patches aiming at cleaning the raw NAND API.
>
> This one focuses on inconsistencies we have in the API + the nand_chip
> and nand_ecc_ctrl interfaces. Some functions/hooks are passed a
> nand_chip object, some are passed an mtd_info object and some are
> passed both.
>
> Since mtd_info can be extracted from nand_chip, we can simply always
> pass a nand_chip and make things consistent. Hopefully with these
> changes merged we'll stop seeing new drivers reproducing the same
> mistake (passing both mtd_info and nand_chip or using mtd_info where
> nand_chip is more appropriate).
>
> For those who want to see what's in the pipe, here is a branch [1]
> containing all the cleanups I plan to merge.
>
> Not much has changed in this v2. I just rebased on top of nand/next,
> fixed typos, added A-b/R-b tags, and that's all.
>
> Regards,
>
> Boris
>
> [1]https://github.com/bbrezillon/linux-0day/commits/nand/api-cleanup
>
> Boris Brezillon (23):
> mtd: rawnand: plat_nand: Pass a nand_chip object to all
> platform_nand_ctrl hooks
> mtd: rawnand: Pass a nand_chip object to nand_scan()
> mtd: rawnand: Pass a nand_chip object to nand_release()
> mtd: rawnand: Pass a nand_chip object to nand_wait_ready()
> mtd: rawnand: Pass a nand_chip object to ecc->hwctl()
> mtd: rawnand: Pass a nand_chip object to ecc->calculate()
> mtd: rawnand: Pass a nand_chip object to ecc->correct()
> mtd: rawnand: Pass a nand_chip object to ecc->read_xxx() hooks
> mtd: rawnand: Pass a nand_chip object to ecc->write_xxx() hooks
> mtd: rawnand: Pass a nand_chip object to chip->read_xxx() hooks
> mtd: rawnand: Pass a nand_chip object to chip->write_xxx() hooks
> mtd: rawnand: Pass a nand_chip object to chip->select_chip()
> mtd: rawnand: Pass a nand_chip object to chip->block_xxx() hooks
> mtd: rawnand: Pass a nand_chip object to chip->cmd_ctrl()
> mtd: rawnand: Pass a nand_chip object to chip->dev_ready()
> mtd: rawnand: Pass a nand_chip object to chip->cmdfunc()
> mtd: rawnand: Pass a nand_chip object to chip->waitfunc()
> mtd: rawnand: Pass a nand_chip object to chip->erase()
> mtd: rawnand: Pass a nand_chip object to chip->{get,set}_features()
> mtd: rawnand: Pass a nand_chip object to chip->setup_read_retry()
> mtd: rawnand: Pass a nand_chip object to chip->setup_data_interface()
> mtd: rawnand: Pass a nand_chip object to all nand_xxx_bbt() helpers
> mtd: rawnand: Pass a nand_chip object nand_erase_nand()
>
> Documentation/driver-api/mtdnand.rst | 4 +-
> arch/arm/mach-ep93xx/snappercl15.c | 7 +-
> arch/arm/mach-ep93xx/ts72xx.c| 7 +-
> arch/arm/mach-imx/mach-qong.c| 11 +-
> arch/arm/mach-ixp4xx/ixdp425-setup.c | 3 +-
> arch/arm/mach-omap1/board-fsample.c | 2 +-
> arch/arm/mach-omap1/board-h2.c | 2 +-
> arch/arm/mach-omap1/board-h3.c | 2 +-
> arch/arm/mach-omap1/board-nand.c | 3 +-
> arch/arm/mach-omap1/board-perseus2.c | 2 +-
> arch/arm/mach-omap1/common.h | 2 +-
> arch/arm/mach-orion5x/ts78xx-setup.c | 18 +-
> arch/arm/mach-pxa/balloon3.c | 8 +-
> arch/arm/mach-pxa/em-x270.c | 5 +-
> arch/arm/mach-pxa/palmtx.c | 5 +-
> arch/mips/alchemy/devboards/db1200.c | 5 +-
> arch/mips/alchemy/devboards/db1300.c | 5 +-
> arch/mips/alchemy/devboards/db1550.c | 5 +-
> arch/mips/netlogic/xlr/platform-flash.c | 4 +-
> arch/mips/pnx833x/common/platform.c | 3 +-
> arch/mips/rb532/devices.c| 5 +-
> arch/sh/boards/mach-migor/setup.c| 6 +-
> drivers/mtd/nand/raw/ams-delta.c | 24 +-
> drivers/mtd/nand/raw/atmel/nand-controller.c | 74 ++-
> drivers/mtd/nand/raw/au1550nd.c | 70 ++-
> drivers/mtd/nand/raw/bcm47xxnflash/main.c| 2 +-
> drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c | 38 +-
> drivers/mtd/nand/raw/brcmnand/brcmnand.c | 78 +--
> drivers/mtd/nand/raw/cafe_nand.c | 56 +--
> drivers/mtd/nand/raw/cmx270_nand.c | 20 +-
> drivers/mtd/nand/raw/cs553x_nand.c | 33 +-
> drivers/mtd/nand/raw/davinci_nand.c | 59 +--
> drivers/mtd/nand/raw/denali.c| 87 ++--
> drivers/mtd/nand/raw/diskonchip.c| 116 ++---
> drivers/mtd/nand/raw/docg4.c | 83 ++--
> drivers/mtd/nand/raw/fsl_elbc_nand.c | 52 +-
> drivers/mtd/nand/raw/fsl_ifc_nand.c | 46 +-
> drivers/mtd/nand/raw/fsl_upm.c | 34 +-
> drivers/mtd/nand/raw/fsmc_nand.c | 42 +-
>
Re: [PATCH] staging:mt29f_spinand: MT29F2G failing as only 16-bit arguments and variables used for addressing.
Hi Dan,
Dan Carpenter wrote on Wed, 1 Aug 2018
15:05:51 +0300:
> On Wed, Aug 01, 2018 at 11:24:19AM +0800, Jheng-Jhong Wu wrote:
> > For NAND flash chips with more than 1Gbit (e.g. MT29F2G) more than 16 bits
> > are necessary to address the correct page. The driver sets the address for
> > more than 16 bits, but it uses 16-bit arguments and variables (these are
> > page_id, block_id, row) to do address operations. Obviously, these
> > arguments and variables cannot deal with more than 16-bit address.
> >
> > Signed-off-by: Jheng-Jhong Wu
>
> This seems reasonable... It would be needed to make commit 6efb21d6d0e7
> ("staging:mt29f_spinand: MT29F2G failing as only 16 bits used for
> addressing.") work. It also fixes a static checker warning.
>
> My only concern is that the mtd/nand code seems to use -1 as a magical
> page_id. For example:
I guess you missed Boris' comment: this driver is very likely to be
removed. A SPI-NAND framework has been added. It does not use the raw
NAND framework anymore, which was wrong anyway.
Thanks,
Miquèl
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Re: [PATCH 5/5] mtd: Stop updating erase_info->state and calling mtd_erase_callback()
Hi Boris,
On Tue, 13 Feb 2018 09:17:14 +0100, Boris Brezillon
<boris.brezil...@bootlin.com> wrote:
> On Tue, 13 Feb 2018 08:42:46 +0100
> Miquel Raynal <miquel.ray...@bootlin.com> wrote:
>
> > Hi Boris,
> >
> > Just a few comments about the form.
> >
> > Otherwise:
> > Reviewed-by: Miquel Raynal <miquel.ray...@bootlin.com>
> >
> >
> > > diff --git a/drivers/mtd/devices/lart.c b/drivers/mtd/devices/lart.c
> > > index 555b94406e0b..3d6c8ffd351f 100644
> > > --- a/drivers/mtd/devices/lart.c
> > > +++ b/drivers/mtd/devices/lart.c
> > > @@ -415,7 +415,6 @@ static int flash_erase (struct mtd_info *mtd,struct
> > > erase_info *instr)
> > >{
> > > if (!erase_block (addr))
> > > {
> > > - instr->state = MTD_ERASE_FAILED;
> > >return (-EIO);
> > > }
> >
> > You can also safely remove these '{' '}'
>
> Well, this patch is not about fixing coding style issues, otherwise I'd
> have a lot more work on this driver :-)
Sure, I was not referring to the weird style but just that you switch
from two to one line in the block, thus the braces are not needed
anymore.
>
> >
> > >
> > > @@ -425,9 +424,6 @@ static int flash_erase (struct mtd_info *mtd,struct
> > > erase_info *instr)
> > > if (addr == mtd->eraseregions[i].offset +
> > > (mtd->eraseregions[i].erasesize * mtd->eraseregions[i].numblocks)) i++;
> > >}
> > >
> > > - instr->state = MTD_ERASE_DONE;
> > > - mtd_erase_callback(instr);
> > > -
> > > return (0);
> > > }
> > >
> > > diff --git a/drivers/mtd/devices/mtd_dataflash.c
> > > b/drivers/mtd/devices/mtd_dataflash.c
> > > index 5dc8bd042cc5..aaaeaae01e1d 100644
> > > --- a/drivers/mtd/devices/mtd_dataflash.c
> > > +++ b/drivers/mtd/devices/mtd_dataflash.c
> > > @@ -220,10 +220,6 @@ static int dataflash_erase(struct mtd_info *mtd,
> > > struct erase_info *instr)
> > > }
> > > mutex_unlock(>lock);
> > >
> > > - /* Inform MTD subsystem that erase is complete */
> > > - instr->state = MTD_ERASE_DONE;
> > > - mtd_erase_callback(instr);
> > > -
> > > return 0;
> > > }
> > >
> > > diff --git a/drivers/mtd/devices/mtdram.c b/drivers/mtd/devices/mtdram.c
> > > index 0bf4aeaf0cb8..efef43c6684b 100644
> > > --- a/drivers/mtd/devices/mtdram.c
> > > +++ b/drivers/mtd/devices/mtdram.c
> > > @@ -60,8 +60,6 @@ static int ram_erase(struct mtd_info *mtd, struct
> > > erase_info *instr)
> > > if (check_offs_len(mtd, instr->addr, instr->len))
> > > return -EINVAL;
> > > memset((char *)mtd->priv + instr->addr, 0xff, instr->len);
> > > - instr->state = MTD_ERASE_DONE;
> > > - mtd_erase_callback(instr);
> >
> > Space ?
>
> I could add a blank line, but again, I'm just following the coding style
> in place in this file :-).
Ok.
>
> >
> > > return 0;
> > > }
> > >
> > > diff --git a/drivers/mtd/devices/phram.c b/drivers/mtd/devices/phram.c
> > > index 7287696a21f9..a963c88d392d 100644
> > > --- a/drivers/mtd/devices/phram.c
> > > +++ b/drivers/mtd/devices/phram.c
> > > @@ -44,8 +44,6 @@ static int phram_erase(struct mtd_info *mtd, struct
> > > erase_info *instr)
> > >* I don't feel at all ashamed. This kind of thing is possible anyway
> > >* with flash, but unlikely.
> > >*/
> >
> > Not sure this comment is still relevant? Maybe you could remove it
> > or at least change it?
> >
> > > - instr->state = MTD_ERASE_DONE;
> > > - mtd_erase_callback(instr);
> >
> > Space ?
> >
> > > return 0;
> > > }
> > >
> > > diff --git a/drivers/mtd/devices/pmc551.c b/drivers/mtd/devices/pmc551.c
> > > index cadea0620cd0..5d842cbca3de 100644
> > > --- a/drivers/mtd/devices/pmc551.c
> > > +++ b/drivers/mtd/devices/pmc551.c
> > > @@ -184,12 +184,10 @@ static int pmc551_erase(struct mtd_info *mtd,
> > > struct erase_info *instr)
> > > }
> > >
> > >out:
> > > - instr->state = MTD_ERASE_DONE;
> > > #ifdef CONFIG_MTD_PMC551_DEBUG
> > > printk(KERN_DEBUG "pmc551_erase() done\n");
>
Re: [PATCH 5/5] mtd: Stop updating erase_info->state and calling mtd_erase_callback()
Hi Boris,
Just a few comments about the form.
Otherwise:
Reviewed-by: Miquel Raynal <miquel.ray...@bootlin.com>
> diff --git a/drivers/mtd/devices/lart.c b/drivers/mtd/devices/lart.c
> index 555b94406e0b..3d6c8ffd351f 100644
> --- a/drivers/mtd/devices/lart.c
> +++ b/drivers/mtd/devices/lart.c
> @@ -415,7 +415,6 @@ static int flash_erase (struct mtd_info *mtd,struct
> erase_info *instr)
>{
> if (!erase_block (addr))
> {
> - instr->state = MTD_ERASE_FAILED;
>return (-EIO);
> }
You can also safely remove these '{' '}'
>
> @@ -425,9 +424,6 @@ static int flash_erase (struct mtd_info *mtd,struct
> erase_info *instr)
> if (addr == mtd->eraseregions[i].offset +
> (mtd->eraseregions[i].erasesize * mtd->eraseregions[i].numblocks)) i++;
>}
>
> - instr->state = MTD_ERASE_DONE;
> - mtd_erase_callback(instr);
> -
> return (0);
> }
>
> diff --git a/drivers/mtd/devices/mtd_dataflash.c
> b/drivers/mtd/devices/mtd_dataflash.c
> index 5dc8bd042cc5..aaaeaae01e1d 100644
> --- a/drivers/mtd/devices/mtd_dataflash.c
> +++ b/drivers/mtd/devices/mtd_dataflash.c
> @@ -220,10 +220,6 @@ static int dataflash_erase(struct mtd_info *mtd, struct
> erase_info *instr)
> }
> mutex_unlock(>lock);
>
> - /* Inform MTD subsystem that erase is complete */
> - instr->state = MTD_ERASE_DONE;
> - mtd_erase_callback(instr);
> -
> return 0;
> }
>
> diff --git a/drivers/mtd/devices/mtdram.c b/drivers/mtd/devices/mtdram.c
> index 0bf4aeaf0cb8..efef43c6684b 100644
> --- a/drivers/mtd/devices/mtdram.c
> +++ b/drivers/mtd/devices/mtdram.c
> @@ -60,8 +60,6 @@ static int ram_erase(struct mtd_info *mtd, struct
> erase_info *instr)
> if (check_offs_len(mtd, instr->addr, instr->len))
> return -EINVAL;
> memset((char *)mtd->priv + instr->addr, 0xff, instr->len);
> - instr->state = MTD_ERASE_DONE;
> - mtd_erase_callback(instr);
Space ?
> return 0;
> }
>
> diff --git a/drivers/mtd/devices/phram.c b/drivers/mtd/devices/phram.c
> index 7287696a21f9..a963c88d392d 100644
> --- a/drivers/mtd/devices/phram.c
> +++ b/drivers/mtd/devices/phram.c
> @@ -44,8 +44,6 @@ static int phram_erase(struct mtd_info *mtd, struct
> erase_info *instr)
>* I don't feel at all ashamed. This kind of thing is possible anyway
>* with flash, but unlikely.
>*/
Not sure this comment is still relevant? Maybe you could remove it
or at least change it?
> - instr->state = MTD_ERASE_DONE;
> - mtd_erase_callback(instr);
Space ?
> return 0;
> }
>
> diff --git a/drivers/mtd/devices/pmc551.c b/drivers/mtd/devices/pmc551.c
> index cadea0620cd0..5d842cbca3de 100644
> --- a/drivers/mtd/devices/pmc551.c
> +++ b/drivers/mtd/devices/pmc551.c
> @@ -184,12 +184,10 @@ static int pmc551_erase(struct mtd_info *mtd, struct
> erase_info *instr)
> }
>
>out:
> - instr->state = MTD_ERASE_DONE;
> #ifdef CONFIG_MTD_PMC551_DEBUG
> printk(KERN_DEBUG "pmc551_erase() done\n");
> #endif
>
> - mtd_erase_callback(instr);
> return 0;
> }
>
> diff --git a/drivers/mtd/devices/powernv_flash.c
> b/drivers/mtd/devices/powernv_flash.c
> index 26f9feaa5d17..5f383630c16f 100644
> --- a/drivers/mtd/devices/powernv_flash.c
> +++ b/drivers/mtd/devices/powernv_flash.c
> @@ -175,19 +175,12 @@ static int powernv_flash_erase(struct mtd_info *mtd,
> struct erase_info *erase)
> {
> int rc;
>
> - erase->state = MTD_ERASING;
> -
> /* todo: register our own notifier to do a true async implementation */
> rc = powernv_flash_async_op(mtd, FLASH_OP_ERASE, erase->addr,
> erase->len, NULL, NULL);
Are you sure this is still needed? Maybe this should go away in your
first patch?
> -
> - if (rc) {
> + if (rc)
> erase->fail_addr = erase->addr;
> - erase->state = MTD_ERASE_FAILED;
> - } else {
> - erase->state = MTD_ERASE_DONE;
> - }
> - mtd_erase_callback(erase);
> +
> return rc;
> }
>
> diff --git a/drivers/mtd/devices/slram.c b/drivers/mtd/devices/slram.c
> index 0ec85f316d24..2f05e1801047 100644
> --- a/drivers/mtd/devices/slram.c
> +++ b/drivers/mtd/devices/slram.c
> @@ -88,8 +88,6 @@ static int slram_erase(struct mtd_info *mtd, struct
> erase_info *instr)
>* I don't feel at all ashamed. This kind of thing is possible anyway
>* with flash, but unlikely.
>*/
Same with this comment.
> - instr->state = MTD_ERASE_DONE;
> - mtd_erase_callback(instr);
Space ?
> return(0);
> }
>
--
Miquel Raynal, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
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Re: [PATCH 5/5] mtd: nand: add ->exec_op() implementation
Hi Boris,
On Fri, 1 Dec 2017 10:50:53 +0100
Boris Brezillon <boris.brezil...@free-electrons.com> wrote:
> Hi Miquel,
>
> On Thu, 30 Nov 2017 23:25:38 +0100
> Miquel RAYNAL <miquel.ray...@free-electrons.com> wrote:
>
> > > > diff --git a/drivers/mtd/nand/nand_base.c
> > > > b/drivers/mtd/nand/nand_base.c index 52965a8aeb2c..46bf31aff909
> > > > 100644 --- a/drivers/mtd/nand/nand_base.c
> > > > +++ b/drivers/mtd/nand/nand_base.c
> > > > @@ -689,6 +689,59 @@ static void nand_wait_status_ready(struct
> > > > mtd_info *mtd, unsigned long timeo) };
> > > >
> > > > /**
> > > > + * nand_soft_waitrdy - Read the status waiting for it to be
> > > > ready
> > > > + * @chip: NAND chip structure
> > > > + * @timeout_ms: Timeout in ms
> > > > + *
> > > > + * Poll the status using ->exec_op() until it is ready unless
> > > > it takes too
> > > > + * much time.
> > > > + *
> > > > + * This helper is intended to be used by drivers without R/B
> > > > pin available to
> > > > + * poll for the chip status until ready and may be called at
> > > > any time in the
> > > > + * middle of any set of instruction. The READ_STATUS just need
> > > > to ask a single
> > > > + * time for it and then any read will return the status. Once
> > > > the READ_STATUS
> > > > + * cycles are done, the function will send a READ0 command to
> > > > cancel the
> > > > + * "READ_STATUS state" and let the normal flow of operation to
> > > > continue.
> > > > + *
> > > > + * This helper *cannot* send a WAITRDY command or ->exec_op()
> > > > implementations
> > >
> > > ^ instruction
> > >
> > > > + * using it will enter an infinite loop.
> > >
> > > Hm, not sure why this would be the case, but okay. Maybe you
> > > should move this comment outside the kernel doc header, since
> > > this is an implementation detail, not something the caller/user
> > > should be aware of.
> >
> > Right.
> >
> > >
> > > There's another important aspect to mention here: this function
> > > can only be called from an ->exec_op() implementation if this
> > > implementation is re-entrant.
> >
> > I do not agree with this statement: this function can be called
> > from an ->exec_op() implementation even if it is not reentrant as
> > long as it does not send a WAITRDY instruction itself. No?
>
> If the ->exec_op() implementation is not re-entrant, no,
> nand_soft_waitrdy() can't be called from ->exec_op(), because then
> you will re-enter ->exec_op() to execute the read_status_op(), and
> BOOM!
>
> >
> > Or maybe you wanted to point that the entire ->exec_op()
> > implementation must be reentrant in order to use this function in
> > it?
>
> Yes, what did you understand?
Ok, I think I misunderstood the "if this implementation is re-entrant".
The implementation you were referring to was ->exec_op()'s
implementation, not nand_soft_waitrdy()'s.
>
> >
> > >
> > > > + *
> > > > + * Return 0 if the NAND chip is ready, a negative error
> > > > otherwise.
> > > > + */
> > > > +int nand_soft_waitrdy(struct nand_chip *chip, unsigned long
> > > > timeout_ms) +{
> > > > + u8 status = 0;
> > > > + int ret;
> > > > +
> > > > + if (!chip->exec_op)
> > > > + return -ENOTSUPP;
> > > > +
> > > > + ret = nand_status_op(chip, NULL);
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + timeout_ms = jiffies + msecs_to_jiffies(timeout_ms);
> > > > + do {
> > > > + ret = nand_read_data_op(chip, ,
> > > > sizeof(status), true);
> > > > + if (ret)
> > > > + break;
> > > > +
> > > > + if (status & NAND_STATUS_READY)
> > > > + break;
> > > > +
> > > > + udelay(100);
> > >
> > > Sounds a bit high, especially for a read page which takes around
> > > 20us.
> >
> > Well, this value is
Re: [PATCH 5/5] mtd: nand: add ->exec_op() implementation
> > diff --git a/drivers/mtd/nand/nand_base.c
> > b/drivers/mtd/nand/nand_base.c index 52965a8aeb2c..46bf31aff909
> > 100644 --- a/drivers/mtd/nand/nand_base.c
> > +++ b/drivers/mtd/nand/nand_base.c
> > @@ -689,6 +689,59 @@ static void nand_wait_status_ready(struct
> > mtd_info *mtd, unsigned long timeo) };
> >
> > /**
> > + * nand_soft_waitrdy - Read the status waiting for it to be ready
> > + * @chip: NAND chip structure
> > + * @timeout_ms: Timeout in ms
> > + *
> > + * Poll the status using ->exec_op() until it is ready unless it
> > takes too
> > + * much time.
> > + *
> > + * This helper is intended to be used by drivers without R/B pin
> > available to
> > + * poll for the chip status until ready and may be called at any
> > time in the
> > + * middle of any set of instruction. The READ_STATUS just need to
> > ask a single
> > + * time for it and then any read will return the status. Once the
> > READ_STATUS
> > + * cycles are done, the function will send a READ0 command to
> > cancel the
> > + * "READ_STATUS state" and let the normal flow of operation to
> > continue.
> > + *
> > + * This helper *cannot* send a WAITRDY command or ->exec_op()
> > implementations
>
> ^ instruction
>
> > + * using it will enter an infinite loop.
>
> Hm, not sure why this would be the case, but okay. Maybe you should
> move this comment outside the kernel doc header, since this is an
> implementation detail, not something the caller/user should be aware
> of.
Right.
>
> There's another important aspect to mention here: this function can
> only be called from an ->exec_op() implementation if this
> implementation is re-entrant.
I do not agree with this statement: this function can be called from an
->exec_op() implementation even if it is not reentrant as long as it
does not send a WAITRDY instruction itself. No?
Or maybe you wanted to point that the entire ->exec_op()
implementation must be reentrant in order to use this function in it?
>
> > + *
> > + * Return 0 if the NAND chip is ready, a negative error otherwise.
> > + */
> > +int nand_soft_waitrdy(struct nand_chip *chip, unsigned long
> > timeout_ms) +{
> > + u8 status = 0;
> > + int ret;
> > +
> > + if (!chip->exec_op)
> > + return -ENOTSUPP;
> > +
> > + ret = nand_status_op(chip, NULL);
> > + if (ret)
> > + return ret;
> > +
> > + timeout_ms = jiffies + msecs_to_jiffies(timeout_ms);
> > + do {
> > + ret = nand_read_data_op(chip, ,
> > sizeof(status), true);
> > + if (ret)
> > + break;
> > +
> > + if (status & NAND_STATUS_READY)
> > + break;
> > +
> > + udelay(100);
>
> Sounds a bit high, especially for a read page which takes around 20us.
Well, this value is arbitrary but greping for NAND_OP_WAIT_RDY tells us
the different timeouts with which this function is usually called, to
get an idea of the possible wait periods: tR, tBERS, tFEAT, tPROG, tRST.
While a tR_max is 200us, a tRST_max is 25us. That is why I choose
100us as period, which I found somehow well tuned for every timeout. But
if you think most of the time the delay will be smaller, I will update
the value to repeat the operation every 20us.
>
> > + } while (time_before(jiffies, timeout_ms));
> > +
> > + nand_exit_status_op(chip);
> > +
> > + if (ret)
> > + return ret;
> > +
> > + return status & NAND_STATUS_READY ? 0 : -ETIMEDOUT;
> > +};
> > +EXPORT_SYMBOL_GPL(nand_soft_waitrdy);
> > +
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Re: [PATCH 1/5] mtd: nand: use usual return values for the ->erase() hook
> > diff --git a/drivers/mtd/nand/nand_base.c
> > b/drivers/mtd/nand/nand_base.c index 630048f5abdc..4d1f2bda6095
> > 100644 --- a/drivers/mtd/nand/nand_base.c
> > +++ b/drivers/mtd/nand/nand_base.c
> > @@ -3077,7 +3077,7 @@ int nand_erase_nand(struct mtd_info *mtd,
> > struct erase_info *instr, status = chip->erase(mtd, page &
> > chip->pagemask);
> > /* See if block erase succeeded */
> > - if (status & NAND_STATUS_FAIL) {
> > + if (status) {
> > pr_debug("%s: failed erase, page 0x%08x\n",
> > __func__, page);
> > instr->state = MTD_ERASE_FAILED;
>
> You forgot to patch single_erase() accordingly.
Right, sorry about that, I will fix that.
Thanks,
Miquèl
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[PATCH 3/5] mtd: nand: force drivers to explicitly send READ/PROG commands
From: Boris Brezillon <boris.brezil...@free-electrons.com> The core currently send the READ0 and SEQIN+PAGEPROG commands in nand_do_read/write_ops(). This is inconsistent with ->read/write_oob[_raw]() hooks behavior which are expected to send these commands. There's already a flag (NAND_ECC_CUSTOM_PAGE_ACCESS) to inform the core that a specific controller wants to send the READ/SEQIN+PAGEPROG commands on its own, but it's an opt-in flag, and existing drivers are unlikely to be updated to pass it. Moreover, some controllers cannot dissociate the READ/PAGEPROG commands from the associated data transfer and ECC engine activation, and developers have to hack things in their ->cmdfunc() implementation to handle such complex cases, or have to accept the perf penalty of sending twice the same command. To address this problem we are planning on adding a new interface which is passed all information about a NAND operation (including the amount of data to transfer) and replacing all calls to ->cmdfunc() to calls to this new ->exec_op() hook. But, in order to do that, we need to have all ->cmdfunc() calls placed near their associated ->read/write_buf/byte() calls. Modify the core and relevant drivers to make NAND_ECC_CUSTOM_PAGE_ACCESS the default case, and remove this flag. Signed-off-by: Boris Brezillon <boris.brezil...@free-electrons.com> [miquel.ray...@free-electrons.com: tested, fixed and rebased on nand/next] Signed-off-by: Miquel Raynal <miquel.ray...@free-electrons.com> --- drivers/mtd/nand/atmel/nand-controller.c | 7 ++- drivers/mtd/nand/bf5xx_nand.c | 6 +- drivers/mtd/nand/brcmnand/brcmnand.c | 13 +++- drivers/mtd/nand/cafe_nand.c | 6 +- drivers/mtd/nand/denali.c | 1 - drivers/mtd/nand/docg4.c | 12 ++-- drivers/mtd/nand/fsl_elbc_nand.c | 10 +-- drivers/mtd/nand/fsl_ifc_nand.c | 6 +- drivers/mtd/nand/gpmi-nand/gpmi-nand.c| 31 +- drivers/mtd/nand/hisi504_nand.c | 6 +- drivers/mtd/nand/lpc32xx_mlc.c| 5 +- drivers/mtd/nand/lpc32xx_slc.c| 11 +++- drivers/mtd/nand/mtk_nand.c | 22 +++ drivers/mtd/nand/nand_base.c | 87 +++ drivers/mtd/nand/nand_micron.c| 56 ++--- drivers/mtd/nand/omap2.c | 10 ++- drivers/mtd/nand/pxa3xx_nand.c| 6 +- drivers/mtd/nand/qcom_nandc.c | 11 drivers/mtd/nand/sh_flctl.c | 6 +- drivers/mtd/nand/sunxi_nand.c | 34 +++ drivers/mtd/nand/tango_nand.c | 1 - drivers/mtd/nand/vf610_nfc.c | 6 +- drivers/staging/mt29f_spinand/mt29f_spinand.c | 5 +- include/linux/mtd/rawnand.h | 11 24 files changed, 171 insertions(+), 198 deletions(-) diff --git a/drivers/mtd/nand/atmel/nand-controller.c b/drivers/mtd/nand/atmel/nand-controller.c index e81fdd2d47b1..b2f00b398490 100644 --- a/drivers/mtd/nand/atmel/nand-controller.c +++ b/drivers/mtd/nand/atmel/nand-controller.c @@ -841,6 +841,8 @@ static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf, struct atmel_nand *nand = to_atmel_nand(chip); int ret; + nand_prog_page_begin_op(chip, page, 0, NULL, 0); + ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw); if (ret) return ret; @@ -857,7 +859,7 @@ static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf, atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize); - return 0; + return nand_prog_page_end_op(chip); } static int atmel_nand_pmecc_write_page(struct mtd_info *mtd, @@ -881,6 +883,8 @@ static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf, struct mtd_info *mtd = nand_to_mtd(chip); int ret; + nand_read_page_op(chip, page, 0, NULL, 0); + ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw); if (ret) return ret; @@ -1178,7 +1182,6 @@ static int atmel_hsmc_nand_ecc_init(struct atmel_nand *nand) chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page; chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw; chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw; - chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS; return 0; } diff --git a/drivers/mtd/nand/bf5xx_nand.c b/drivers/mtd/nand/bf5xx_nand.c index 5655dca6ce43..87bbd177b3e5 100644 --- a/drivers/mtd/nand/bf5xx_nand.c +++ b/drivers/mtd/nand/bf5xx_nand.c @@ -572,6 +572,8 @@ static void bf5xx_nand_dma_write_buf(struct mtd_info *mtd, static int bf5xx_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int pag
[PATCH 5/5] mtd: nand: add ->exec_op() implementation
Introduce a new interface to instruct NAND controllers to send specific
NAND operations. The new interface takes the form of a single method
called ->exec_op(). This method is designed to replace ->cmd_ctrl(),
->cmdfunc() and ->read/write_byte/word/buf() hooks.
->exec_op() is passed a set of instructions describing the operation
to execute. Each instruction has a type (ADDR, CMD, DATA, WAITRDY)
and delay. The type is directly matching the description of NAND
operations in various NAND datasheet and standards (ONFI, JEDEC), the
delay is here to help simple controllers wait enough time between each
instruction. Advanced controllers with integrated timings control can
ignore these delays.
Advanced controllers (that are not limited to independent ADDR, CMD and
DATA cycles) may use the parser added by this commit to get the best
matching hook, if any. The instructions may be split by the parser in
order to comply with the controller constraints filled in an array of
supported patterns.
For instance, if a controller driver declares supporting up to 4 address
cycles and then writes up to 512 bytes within one pattern (both are
optional in this pattern):
NAND_OP_PARSER_PAT_ADDR_ELEM(true, 4)
NAND_OP_PARSER_PAT_DATA_OUT_ELEM(true, 512)
It means that if the matching operation is made of 5 address cycles
followed by 1024 bytes to write, then the controller will be asked to:
- send 4 address cycles (the first four cycles),
- send 1 address cycle (the last one) +
write 512 bytes (the first half),
- write 512 bytes again (the second half).
Various other helpers are also added to ease NAND controller drivers
writing.
This new interface should really ease the support of new vendor specific
operations, and at least report whether the command is supported or not
by a given controller, which was not possible before.
Suggested-by: Boris Brezillon <boris.brezil...@free-electrons.com>
Signed-off-by: Miquel Raynal <miquel.ray...@free-electrons.com>
---
drivers/mtd/nand/nand_base.c | 1037 +++--
drivers/mtd/nand/nand_hynix.c |9 +
include/linux/mtd/rawnand.h | 391 +++-
3 files changed, 1397 insertions(+), 40 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 52965a8aeb2c..46bf31aff909 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -689,6 +689,59 @@ static void nand_wait_status_ready(struct mtd_info *mtd,
unsigned long timeo)
};
/**
+ * nand_soft_waitrdy - Read the status waiting for it to be ready
+ * @chip: NAND chip structure
+ * @timeout_ms: Timeout in ms
+ *
+ * Poll the status using ->exec_op() until it is ready unless it takes too
+ * much time.
+ *
+ * This helper is intended to be used by drivers without R/B pin available to
+ * poll for the chip status until ready and may be called at any time in the
+ * middle of any set of instruction. The READ_STATUS just need to ask a single
+ * time for it and then any read will return the status. Once the READ_STATUS
+ * cycles are done, the function will send a READ0 command to cancel the
+ * "READ_STATUS state" and let the normal flow of operation to continue.
+ *
+ * This helper *cannot* send a WAITRDY command or ->exec_op() implementations
+ * using it will enter an infinite loop.
+ *
+ * Return 0 if the NAND chip is ready, a negative error otherwise.
+ */
+int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms)
+{
+ u8 status = 0;
+ int ret;
+
+ if (!chip->exec_op)
+ return -ENOTSUPP;
+
+ ret = nand_status_op(chip, NULL);
+ if (ret)
+ return ret;
+
+ timeout_ms = jiffies + msecs_to_jiffies(timeout_ms);
+ do {
+ ret = nand_read_data_op(chip, , sizeof(status), true);
+ if (ret)
+ break;
+
+ if (status & NAND_STATUS_READY)
+ break;
+
+ udelay(100);
+ } while (time_before(jiffies, timeout_ms));
+
+ nand_exit_status_op(chip);
+
+ if (ret)
+ return ret;
+
+ return status & NAND_STATUS_READY ? 0 : -ETIMEDOUT;
+};
+EXPORT_SYMBOL_GPL(nand_soft_waitrdy);
+
+/**
* nand_command - [DEFAULT] Send command to NAND device
* @mtd: MTD device structure
* @command: the command to be sent
@@ -1238,6 +1291,134 @@ static int nand_init_data_interface(struct nand_chip
*chip)
}
/**
+ * nand_fill_column_cycles - fill the column fields on an address array
+ * @chip: The NAND chip
+ * @addrs: Array of address cycles to fill
+ * @offset_in_page: The offset in the page
+ *
+ * Fills the first or the two first bytes of the @addrs field depending
+ * on the NAND bus width and the page size.
+ */
+static int nand_fill_column_cycles(struct nand_chip *chip, u8 *addrs,
+ unsigned int offset_in_pa
[PATCH 2/5] mtd: nand: provide several helpers to do common NAND operations
From: Boris Brezillon <boris.brezil...@free-electrons.com>
This is part of the process of removing direct calls to ->cmdfunc()
outside of the core in order to introduce a better interface to execute
NAND operations.
Here we provide several helpers and make use of them to remove all
direct calls to ->cmdfunc(). This way, we can easily modify those
helpers to make use of the new ->exec_op() interface when available.
Signed-off-by: Boris Brezillon <boris.brezil...@free-electrons.com>
[miquel.ray...@free-electrons.com: rebased and fixed some conflicts]
Signed-off-by: Miquel Raynal <miquel.ray...@free-electrons.com>
---
drivers/mtd/nand/atmel/nand-controller.c |2 +-
drivers/mtd/nand/brcmnand/brcmnand.c |9 +-
drivers/mtd/nand/cafe_nand.c | 14 +-
drivers/mtd/nand/denali.c| 37 +-
drivers/mtd/nand/diskonchip.c|4 +-
drivers/mtd/nand/docg4.c |2 +-
drivers/mtd/nand/fsmc_nand.c |5 +-
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 58 +-
drivers/mtd/nand/hisi504_nand.c |3 +-
drivers/mtd/nand/jz4740_nand.c | 16 +-
drivers/mtd/nand/lpc32xx_mlc.c |2 +-
drivers/mtd/nand/lpc32xx_slc.c | 22 +-
drivers/mtd/nand/mtk_nand.c | 11 +-
drivers/mtd/nand/nand_base.c | 1007 +-
drivers/mtd/nand/nand_hynix.c| 115 ++--
drivers/mtd/nand/nand_micron.c | 77 ++-
drivers/mtd/nand/omap2.c |8 +-
drivers/mtd/nand/pxa3xx_nand.c |8 +-
drivers/mtd/nand/qcom_nandc.c| 16 +-
drivers/mtd/nand/r852.c | 11 +-
drivers/mtd/nand/sunxi_nand.c| 71 +--
drivers/mtd/nand/tango_nand.c| 26 +-
drivers/mtd/nand/tmio_nand.c |5 +-
include/linux/mtd/rawnand.h | 27 +
24 files changed, 1130 insertions(+), 426 deletions(-)
diff --git a/drivers/mtd/nand/atmel/nand-controller.c
b/drivers/mtd/nand/atmel/nand-controller.c
index 90a71a56bc23..e81fdd2d47b1 100644
--- a/drivers/mtd/nand/atmel/nand-controller.c
+++ b/drivers/mtd/nand/atmel/nand-controller.c
@@ -1000,7 +1000,7 @@ static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip
*chip, u8 *buf,
* to the non-optimized one.
*/
if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+ nand_read_page_op(chip, page, 0, NULL, 0);
return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
raw);
diff --git a/drivers/mtd/nand/brcmnand/brcmnand.c
b/drivers/mtd/nand/brcmnand/brcmnand.c
index e0eb51d8c012..3f441096a14c 100644
--- a/drivers/mtd/nand/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/brcmnand/brcmnand.c
@@ -1071,7 +1071,7 @@ static void brcmnand_wp(struct mtd_info *mtd, int wp)
return;
brcmnand_set_wp(ctrl, wp);
- chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
+ nand_status_op(chip, NULL);
/* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */
ret = bcmnand_ctrl_poll_status(ctrl,
NAND_CTRL_RDY |
@@ -1453,7 +1453,7 @@ static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
/* At FC_BYTES boundary, switch to next column */
if (host->last_byte > 0 && offs == 0)
- chip->cmdfunc(mtd, NAND_CMD_RNDOUT, addr, -1);
+ nand_change_read_column_op(chip, addr, NULL, 0, false);
ret = ctrl->flash_cache[offs];
break;
@@ -1689,7 +1689,7 @@ static int brcmstb_nand_verify_erased_page(struct
mtd_info *mtd,
sas = mtd->oobsize / chip->ecc.steps;
/* read without ecc for verification */
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+ nand_read_page_op(chip, page, 0, NULL, 0);
ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page);
if (ret)
return ret;
@@ -2369,12 +2369,11 @@ static int brcmnand_resume(struct device *dev)
list_for_each_entry(host, >host_list, node) {
struct nand_chip *chip = >chip;
- struct mtd_info *mtd = nand_to_mtd(chip);
brcmnand_save_restore_cs_config(host, 1);
/* Reset the chip, required by some chips after power-up */
- chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ nand_reset_op(chip);
}
return 0;
diff --git a/drivers/mtd/nand/cafe_nand.c b/drivers/mtd/nand/cafe_nand.c
index bc558c438a57..95c2cfa68b66 100644
--- a/drivers/mtd/nand/cafe_nand.c
+++ b/drivers/mtd/nand/cafe_nand.c
@@ -353,23 +353,15 @@ static void cafe_nand_bug(struct mtd_info *mtd)
static int
[PATCH 4/5] mtd: nand: use a static data_interface in the nand_chip structure
Change the nand_chip structure, to embed the nand_data_interface object.
Also remove the nand_get_default_data_interface() function that become
useless but add the initialization of the data_interface at the very
beginning of nand_scan_ident() to be sure core functions using timings
may be used safely.
Signed-off-by: Miquel Raynal <miquel.ray...@free-electrons.com>
---
drivers/mtd/nand/nand_base.c| 44 ++---
drivers/mtd/nand/nand_timings.c | 21 +---
include/linux/mtd/rawnand.h | 7 ++-
3 files changed, 26 insertions(+), 46 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index ee9825780a6c..52965a8aeb2c 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -816,8 +816,8 @@ static void nand_ccs_delay(struct nand_chip *chip)
* Wait tCCS_min if it is correctly defined, otherwise wait 500ns
* (which should be safe for all NANDs).
*/
- if (chip->data_interface && chip->data_interface->timings.sdr.tCCS_min)
- ndelay(chip->data_interface->timings.sdr.tCCS_min / 1000);
+ if (chip->setup_data_interface)
+ ndelay(chip->data_interface.timings.sdr.tCCS_min / 1000);
else
ndelay(500);
}
@@ -1112,7 +1112,6 @@ static int nand_wait(struct mtd_info *mtd, struct
nand_chip *chip)
static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
{
struct mtd_info *mtd = nand_to_mtd(chip);
- const struct nand_data_interface *conf;
int ret;
if (!chip->setup_data_interface)
@@ -1132,8 +1131,8 @@ static int nand_reset_data_interface(struct nand_chip
*chip, int chipnr)
* timings to timing mode 0.
*/
- conf = nand_get_default_data_interface();
- ret = chip->setup_data_interface(mtd, chipnr, conf);
+ onfi_fill_data_interface(chip, NAND_SDR_IFACE, 0);
+ ret = chip->setup_data_interface(mtd, chipnr, >data_interface);
if (ret)
pr_err("Failed to configure data interface to SDR timing mode
0\n");
@@ -1158,7 +1157,7 @@ static int nand_setup_data_interface(struct nand_chip
*chip, int chipnr)
struct mtd_info *mtd = nand_to_mtd(chip);
int ret;
- if (!chip->setup_data_interface || !chip->data_interface)
+ if (!chip->setup_data_interface)
return 0;
/*
@@ -1179,7 +1178,7 @@ static int nand_setup_data_interface(struct nand_chip
*chip, int chipnr)
goto err;
}
- ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface);
+ ret = chip->setup_data_interface(mtd, chipnr, >data_interface);
err:
return ret;
}
@@ -1219,21 +1218,16 @@ static int nand_init_data_interface(struct nand_chip
*chip)
modes = GENMASK(chip->onfi_timing_mode_default, 0);
}
- chip->data_interface = kzalloc(sizeof(*chip->data_interface),
- GFP_KERNEL);
- if (!chip->data_interface)
- return -ENOMEM;
for (mode = fls(modes) - 1; mode >= 0; mode--) {
- ret = onfi_init_data_interface(chip, chip->data_interface,
- NAND_SDR_IFACE, mode);
+ ret = onfi_fill_data_interface(chip, NAND_SDR_IFACE, mode);
if (ret)
continue;
/* Pass -1 to only */
ret = chip->setup_data_interface(mtd,
NAND_DATA_IFACE_CHECK_ONLY,
-chip->data_interface);
+>data_interface);
if (!ret) {
chip->onfi_timing_mode_default = mode;
break;
@@ -1243,11 +1237,6 @@ static int nand_init_data_interface(struct nand_chip
*chip)
return 0;
}
-static void nand_release_data_interface(struct nand_chip *chip)
-{
- kfree(chip->data_interface);
-}
-
/**
* nand_read_page_op - Do a READ PAGE operation
* @chip: The NAND chip
@@ -1763,11 +1752,16 @@ EXPORT_SYMBOL_GPL(nand_write_data_op);
* @chip: The NAND chip
* @chipnr: Internal die id
*
+ * Save the timings data structure, then apply SDR timings mode 0 (see
+ * nand_reset_data_interface for details), do the reset operation, and
+ * apply back the previous timings.
+ *
* Returns 0 for success or negative error code otherwise
*/
int nand_reset(struct nand_chip *chip, int chipnr)
{
struct mtd_info *mtd = nand_to_mtd(chip);
+ struct nand_data_interface saved_data_intf = chip->data_interface;
int ret;
ret = nand_reset_data_interface(chip, chipnr);
@@ -1785,6 +1779,7 @@ int nand_reset(struct nand_chip *ch
[PATCH 0/5] Introduce the new NAND core interface: ->exec_op()
Hi, This series adds the implementation of the NAND framework ->exec_op() interface with all the related hooks and helpers. The reasons for adding it are explained in details in the commit log: "mtd: nand: add ->exec_op() implementation" Long story short: it will ease later expansion of the framework, as well as the implementation of new vendor specific commands, and should also ease driver development. A lot of comments are written to explain how to use the new API. Several NAND controller drivers are already/almost converted to ->exec_op(), in particular a rework of the Marvell NAND controller driver, and will follow. One can have a look at them as examples to understand how to implement or rework NAND controller drivers. A proper external documentation is being written and will later be submitted. Thank you, Miquèl Boris Brezillon (2): mtd: nand: provide several helpers to do common NAND operations mtd: nand: force drivers to explicitly send READ/PROG commands Miquel Raynal (3): mtd: nand: use usual return values for the ->erase() hook mtd: nand: use a static data_interface in the nand_chip structure mtd: nand: add ->exec_op() implementation drivers/mtd/nand/atmel/nand-controller.c |9 +- drivers/mtd/nand/bf5xx_nand.c |6 +- drivers/mtd/nand/brcmnand/brcmnand.c | 20 +- drivers/mtd/nand/cafe_nand.c | 20 +- drivers/mtd/nand/denali.c | 40 +- drivers/mtd/nand/diskonchip.c |4 +- drivers/mtd/nand/docg4.c | 21 +- drivers/mtd/nand/fsl_elbc_nand.c | 10 +- drivers/mtd/nand/fsl_ifc_nand.c |6 +- drivers/mtd/nand/fsmc_nand.c |5 +- drivers/mtd/nand/gpmi-nand/gpmi-nand.c| 77 +- drivers/mtd/nand/hisi504_nand.c |9 +- drivers/mtd/nand/jz4740_nand.c| 16 +- drivers/mtd/nand/lpc32xx_mlc.c|7 +- drivers/mtd/nand/lpc32xx_slc.c| 33 +- drivers/mtd/nand/mtk_nand.c | 25 +- drivers/mtd/nand/nand_base.c | 2161 ++--- drivers/mtd/nand/nand_hynix.c | 124 +- drivers/mtd/nand/nand_micron.c| 83 +- drivers/mtd/nand/nand_timings.c | 21 +- drivers/mtd/nand/omap2.c | 18 +- drivers/mtd/nand/pxa3xx_nand.c| 14 +- drivers/mtd/nand/qcom_nandc.c | 27 +- drivers/mtd/nand/r852.c | 11 +- drivers/mtd/nand/sh_flctl.c |6 +- drivers/mtd/nand/sunxi_nand.c | 97 +- drivers/mtd/nand/tango_nand.c | 27 +- drivers/mtd/nand/tmio_nand.c |5 +- drivers/mtd/nand/vf610_nfc.c |6 +- drivers/staging/mt29f_spinand/mt29f_spinand.c |5 +- include/linux/mtd/rawnand.h | 414 - 31 files changed, 2673 insertions(+), 654 deletions(-) -- 2.11.0 ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[PATCH 1/5] mtd: nand: use usual return values for the ->erase() hook
Avoid using specific defined values for checking returned status of the
->erase() hook. Instead, use usual negative error values on failure,
zero otherwise.
Signed-off-by: Miquel Raynal <miquel.ray...@free-electrons.com>
---
drivers/mtd/nand/denali.c| 2 +-
drivers/mtd/nand/docg4.c | 7 ++-
drivers/mtd/nand/nand_base.c | 2 +-
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 34008a02ddb0..3e19861a46c6 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -951,7 +951,7 @@ static int denali_erase(struct mtd_info *mtd, int page)
irq_status = denali_wait_for_irq(denali,
INTR__ERASE_COMP | INTR__ERASE_FAIL);
- return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL;
+ return irq_status & INTR__ERASE_COMP ? 0 : -EIO;
}
static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c
index 2436cbc71662..45c01b4b34c7 100644
--- a/drivers/mtd/nand/docg4.c
+++ b/drivers/mtd/nand/docg4.c
@@ -900,6 +900,7 @@ static int docg4_erase_block(struct mtd_info *mtd, int page)
struct docg4_priv *doc = nand_get_controller_data(nand);
void __iomem *docptr = doc->virtadr;
uint16_t g4_page;
+ int status;
dev_dbg(doc->dev, "%s: page %04x\n", __func__, page);
@@ -939,7 +940,11 @@ static int docg4_erase_block(struct mtd_info *mtd, int
page)
poll_status(doc);
write_nop(docptr);
- return nand->waitfunc(mtd, nand);
+ status = nand->waitfunc(mtd, nand);
+ if (status < 0)
+ return status;
+
+ return status & NAND_STATUS_FAIL ? -EIO : 0;
}
static int write_page(struct mtd_info *mtd, struct nand_chip *nand,
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 630048f5abdc..4d1f2bda6095 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -3077,7 +3077,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct
erase_info *instr,
status = chip->erase(mtd, page & chip->pagemask);
/* See if block erase succeeded */
- if (status & NAND_STATUS_FAIL) {
+ if (status) {
pr_debug("%s: failed erase, page 0x%08x\n",
__func__, page);
instr->state = MTD_ERASE_FAILED;
--
2.11.0
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Re: [RFC 05/12] dt-bindings: mtd: add Marvell NAND controller documentation
Hi Rob,
> > +Required properties:
> > +C'est faux, t'en a rajouté un y a pas longtps :).
> > +Je conseille de mettre ça sous forme de liste, genre
>
> Humm.
Oops!
>
> > +
> > +- compatible: can be one of the following:
> > +* "marvell,armada-8k-nand-controller"
> > +* "marvell,armada370-nand-controller"
> > +* "marvell,pxa3xx-nand-controller"
> > +* "marvell,armada-8k-nand" (deprecated)
> > +* "marvell,armada370-nand" (deprecated)
> > +* "marvell,pxa3xx-nand" (deprecated)
> > +- reg: shall contain registers location and length for data and
> > reg.
>
> 2 regions?
Just one, rephrased.
>
> > +- #address-cells: shall be set to 1. Encode the nand CS.
> > +- #size-cells: shall be set to 0.
> > +- interrupts: shall define the nand controller interrupt.
> > +- clocks: shall reference nand controller clocks.
>
> How many clocks?
Only one too: "reference the NAND controller clock".
>
> > +- marvell,system-controller: Set to retrieve the syscon node that
> > handles
> > + NAND controller related registers (only required with the
> > + "marvell,armada-8k-nand[-controller]" compatibles).
> > +
> > +Optional properties:
> > +- dmas: shall reference DMA channel associated to the NAND
> > controller. +- dma-names: shall be "rxtx".
> > +
> > +Optional children nodes:
> > +Children nodes represent the available NAND chips.
> > +
> > +Required properties:
> > +- reg: shall contain the native Chip Select ids (0-3)
> > +- marvell,rb: shall contain the native Ready/Busy ids (0-1)
> > +
> > +Optional properties:
> > +- marvell,nand-keep-config: orders the driver not to take the
> > timings
> > + from the core and leaving them completely untouched. Bootloader
> > + timings will then be used.
> > +- marvell,nand-enable-arbiter: only useful for PXA platforms, will
> > + enable bus arbiter between NFC and DFI bus (must be enabled for
> > + NFC operation)
>
> Why do you need this if it must be enabled?
That is right, there is no more need for it, also removed it from the
driver, just knowing the board with the compatible string is enough.
>
> > +- nand-on-flash-bbt: speed up the boot process by not discovering
> > all
> > + the bad blocks at each boot and reading directly an on flash
> > table. +- nand-ecc-mode: one of the supported ECC modes ("none",
> > "soft",
> > + "hw"). If not specified, hardware ECC will be used.
> > +- nand-ecc-algo: algorithm to use if previous choice was "soft"
> > + ("hamming" or "bch). This property may be added for hardware ECC
> > for
> > + clarification but will be ignored by the driver because ECC mode
> > is
> > + chosen depending on the page size and the strength required by
> > the
> > + NAND chip. This value may be overwritten with the
> > nand-ecc-strength
> > + property.
> > +- nand-ecc-strength: desired ECC strength.
> > +- nand-ecc-step-size: indication on the ECC step size. This has no
> > + effect and will be ignored by the driver when using hardware
> > + ECC. Because Marvell's NAND flash controller does use fixed
> > strength
> > + (1-bit for Hamming, 16-bit for BCH), the step size will shrink or
> > + grown in order to fit the required strength and the value
> > + updated. Step sizes are not completely random for all and follow
> > + certain patterns described in AN-379, "Marvell SoC NFC ECC".
>
> For standard properties, just reference nand.txt and add any
> constraints. Don't define what the property is again.
Ok.
>
> > +
> > +See Documentation/devicetree/bindings/mtd/nand.txt for more
> > details on +generic bindings.
> > +
> > +
> > +Example:
> > +nand_controller: nand-controller@d {
> > + compatible = "marvell,armada370-nand-controller";
> > + reg = <0xd 0x54>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + interrupts = ;
> > + clocks = < 0>;
> > + status = "okay";
>
> Don't show status in examples.
Ok.
>
> > +
> > + nand@0 {
> > + reg = <0>;
> > + marvell,rb = <0>;
> > + nand-ecc-mode = "hw";
> > + marvell,nand-keep-config;
> > + marvell,nand-enable-arbiter;
> > + nand-on-flash-bbt;
> > + nand-ecc-strength = <4>;
> > + nand-ecc-step-size = <512>;
> > +
> > + partitions {
> > + compatible = "fixed-partitions";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + partition@0 {
> > + label = "Rootfs";
> > + reg = <0x 0x4000>;
> > + };
> > + };
> > + };
> > +};
> > --
> > 2.11.0
> >
Thanks for the review,
Miquèl
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[RFC 07/12] ARM: dts: armada-370-xp: use reworked NAND controller driver
Change the bindings to use the reworked Marvell NAND controller driver.
Also adapt the nand controller node organization to distinguish which
property is relevant for the controller, and which one is NAND chip
specific. Expose the partitions as a subnode of the NAND chip.
Remove the 'marvell,nand-enable-arbiter' property, inefective with
Armada boards.
Signed-off-by: Miquel Raynal <miquel.ray...@free-electrons.com>
---
arch/arm/boot/dts/armada-370-db.dts| 56
arch/arm/boot/dts/armada-370-dlink-dns327l.dts | 119
arch/arm/boot/dts/armada-370-mirabox.dts | 50 ---
arch/arm/boot/dts/armada-370-netgear-rn102.dts | 89 ++--
arch/arm/boot/dts/armada-370-netgear-rn104.dts | 89 ++--
arch/arm/boot/dts/armada-370-rd.dts| 51 ---
arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi | 63 +
arch/arm/boot/dts/armada-370-xp.dtsi | 6 +-
arch/arm/boot/dts/armada-xp-db-dxbc2.dts | 1 -
arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 1 -
arch/arm/boot/dts/armada-xp-db.dts | 1 -
arch/arm/boot/dts/armada-xp-gp.dts | 1 -
arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts| 1 -
arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 155 +++--
arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 89 ++--
15 files changed, 420 insertions(+), 352 deletions(-)
diff --git a/arch/arm/boot/dts/armada-370-db.dts
b/arch/arm/boot/dts/armada-370-db.dts
index c4eef7323367..76c433c29731 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -142,33 +142,6 @@
usb@51000 {
status = "okay";
};
-
- nand@d {
- status = "okay";
- num-cs = <1>;
- marvell,nand-keep-config;
- marvell,nand-enable-arbiter;
- nand-on-flash-bbt;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "U-Boot";
- reg = <0 0x80>;
- };
- partition@80 {
- label = "Linux";
- reg = <0x80 0x80>;
- };
- partition@100 {
- label = "Filesystem";
- reg = <0x100 0x3f00>;
- };
- };
- };
};
};
@@ -276,3 +249,32 @@
};
};
+_controller {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ marvell,rb = <0>;
+ marvell,nand-keep-config;
+ nand-on-flash-bbt;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x80>;
+ };
+ partition@80 {
+ label = "Linux";
+ reg = <0x80 0x80>;
+ };
+ partition@100 {
+ label = "Filesystem";
+ reg = <0x100 0x3f00>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
index db7f3aa38670..0cc3285a40b3 100644
--- a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
+++ b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts
@@ -81,61 +81,6 @@
usb@5 {
status = "okay";
};
-
- nand@d {
- status = "okay";
- num-cs = <1>;
- marvell,nand-keep-config;
-
[RFC 12/12] ARM64: dts: marvell: use reworked NAND controller driver on Armada 7K/8K
Change the bindings to use the reworked Marvell NAND controller driver.
Also adapt the nand controller node organization to distinguish which
property is relevant for the controller, and which one is NAND chip
specific. Expose the partitions as a subnode of the NAND chip.
Remove the 'marvell,nand-enable-arbiter' property, inefective with
Armada boards.
Signed-off-by: Miquel Raynal <miquel.ray...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 47 +-
.../boot/dts/marvell/armada-cp110-master.dtsi | 6 +--
.../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 6 +--
3 files changed, 34 insertions(+), 25 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 3cb4e81f6415..cd0290613eea 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -144,32 +144,41 @@
};
};
-_nand {
+_nand_controller {
/*
* SPI on CPM and NAND have common pins on this board. We can
-* use only one at a time. To enable the NAND (whihch will
+* use only one at a time. To enable the NAND (which will
* disable the SPI), the "status = "okay";" line have to be
* added here.
*/
- num-cs = <1>;
pinctrl-0 = <_pins>, <_rb>;
pinctrl-names = "default";
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
- marvell,nand-enable-arbiter;
- nand-on-flash-bbt;
-
- partition@0 {
- label = "U-Boot";
- reg = <0 0x20>;
- };
- partition@20 {
- label = "Linux";
- reg = <0x20 0xe0>;
- };
- partition@100 {
- label = "Filesystem";
- reg = <0x100 0x3f00>;
+
+ nand@0 {
+ reg = <0>;
+ marvell,rb = <0>;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x20>;
+ };
+
+ partition@20 {
+ label = "Linux";
+ reg = <0x20 0xe0>;
+ };
+
+ partition@100 {
+ label = "Filesystem";
+ reg = <0x100 0x3f00>;
+ };
+
+ };
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index f203f7300194..c209f2f93b6c 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -268,14 +268,14 @@
status = "disabled";
};
- cpm_nand: nand@72 {
+ cpm_nand_controller: nand@72 {
/*
* Due to the limiation of the pin available
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
- compatible = "marvell,armada-8k-nand",
-"marvell,armada370-nand";
+ compatible =
"marvell,armada-8k-nand-controller",
+
"marvell,armada370-nand-controller";
reg = <0x72 0x54>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 7d78767d3024..22789485d77e 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -269,14 +269,14 @@
status = "disabled";
};
- cps_nand: nand@72 {
+ cps_nand_controller: nand@72 {
/*
* Due to the limiation of the pin available
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
-
[RFC 10/12] ARM: dts: armada-39x: use reworked NAND controller driver
Change the bindings to use the reworked Marvell NAND controller driver.
Also adapt the nand controller node organization to distinguish which
property is relevant for the controller, and which one is NAND chip
specific. Expose the partitions as a subnode of the NAND chip.
Remove the 'marvell,nand-enable-arbiter' property, inefective with
Armada boards.
Signed-off-by: Miquel Raynal <miquel.ray...@free-electrons.com>
---
arch/arm/boot/dts/armada-390-db.dts | 65 +
arch/arm/boot/dts/armada-395-gp.dts | 73 +++--
arch/arm/boot/dts/armada-398-db.dts | 59 +-
arch/arm/boot/dts/armada-39x.dtsi | 6 +--
4 files changed, 109 insertions(+), 94 deletions(-)
diff --git a/arch/arm/boot/dts/armada-390-db.dts
b/arch/arm/boot/dts/armada-390-db.dts
index c718a5242595..5a8b05da80f2 100644
--- a/arch/arm/boot/dts/armada-390-db.dts
+++ b/arch/arm/boot/dts/armada-390-db.dts
@@ -86,37 +86,6 @@
status = "okay";
};
- flash@d {
- status = "okay";
- pinctrl-0 = <_pins>;
- pinctrl-names = "default";
- num-cs = <1>;
- marvell,nand-keep-config;
- marvell,nand-enable-arbiter;
- nand-on-flash-bbt;
- nand-ecc-strength = <8>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "U-Boot";
- reg = <0 0x80>;
- };
- partition@80 {
- label = "Linux";
- reg = <0x80 0x80>;
- };
- partition@100 {
- label = "Filesystem";
- reg = <0x100 0x3f00>;
- };
- };
- };
-
/* CON98 */
usb3@f8000 {
status = "okay";
@@ -173,3 +142,37 @@
};
};
};
+
+_controller {
+ status = "okay";
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ nand@0 {
+ reg = <0>;
+ marvell,rb = <0>;
+ marvell,nand-keep-config;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x80>;
+ };
+ partition@80 {
+ label = "Linux";
+ reg = <0x80 0x80>;
+ };
+ partition@100 {
+ label = "Filesystem";
+ reg = <0x100 0x3f00>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/armada-395-gp.dts
b/arch/arm/boot/dts/armada-395-gp.dts
index ef491b524fd6..6261bc6ea3d0 100644
--- a/arch/arm/boot/dts/armada-395-gp.dts
+++ b/arch/arm/boot/dts/armada-395-gp.dts
@@ -88,41 +88,6 @@
status = "okay";
};
- flash@d {
- status = "okay";
- pinctrl-0 = <_pins>;
- pinctrl-names = "default";
- num-cs = <1>;
- marvell,nand-keep-config;
- marvell,nand-enable-arbiter;
- nand-on-flash-bbt;
- nand-ecc-strength = &
[RFC 08/12] ARM: dts: armada-375: use reworked NAND controller driver
Change the bindings to use the reworked Marvell NAND controller driver.
Also adapt the nand controller node organization to distinguish which
property is relevant for the controller, and which one is NAND chip
specific. Expose the partitions as a subnode of the NAND chip.
Remove the 'marvell,nand-enable-arbiter' property, inefective with
Armada boards.
Signed-off-by: Miquel Raynal <miquel.ray...@free-electrons.com>
---
arch/arm/boot/dts/armada-375-db.dts | 49 ++---
arch/arm/boot/dts/armada-375.dtsi | 6 ++---
2 files changed, 32 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/armada-375-db.dts
b/arch/arm/boot/dts/armada-375-db.dts
index bcdbb8ba1d65..42277a554063 100644
--- a/arch/arm/boot/dts/armada-375-db.dts
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -140,28 +140,37 @@
nr-ports = <2>;
};
- {
+_controller {
+ status = "okay";
pinctrl-0 = <_pins>;
pinctrl-names = "default";
- status = "okay";
- num-cs = <1>;
- marvell,nand-keep-config;
- marvell,nand-enable-arbiter;
- nand-on-flash-bbt;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
-
- partition@0 {
- label = "U-Boot";
- reg = <0 0x80>;
- };
- partition@80 {
- label = "Linux";
- reg = <0x80 0x80>;
- };
- partition@100 {
- label = "Filesystem";
- reg = <0x100 0x3f00>;
+
+ nand@0 {
+ reg = <0>;
+ marvell,rb = <0>;
+ marvell,nand-keep-config;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x80>;
+ };
+ partition@80 {
+ label = "Linux";
+ reg = <0x80 0x80>;
+ };
+ partition@100 {
+ label = "Filesystem";
+ reg = <0x100 0x3f00>;
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-375.dtsi
b/arch/arm/boot/dts/armada-375.dtsi
index 7225c7ce9a8d..db66b5f29834 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -539,11 +539,11 @@
status = "disabled";
};
- nand: nand@d {
- compatible = "marvell,armada370-nand";
+ nand_controller: nand-controller@d {
+ compatible =
"marvell,armada370-nand-controller";
reg = <0xd 0x54>;
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
interrupts = ;
clocks = < 11>;
status = "disabled";
--
2.11.0
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[RFC 01/12] mtd: nand: provide several helpers to do common NAND operations
From: Boris Brezillon <boris.brezil...@free-electrons.com>
This is part of the process of removing direct calls to ->cmdfunc()
outside of the core in order to introduce a better interface to execute
NAND operations.
Here we provide several helpers and make use of them to remove all
direct calls to ->cmdfunc(). This way, we can easily modify those
helpers to make use of the new ->exec_op() interface when available.
Signed-off-by: Boris Brezillon <boris.brezil...@free-electrons.com>
[miquel.ray...@free-electrons.com: rebased and fixed some conflicts]
Signed-off-by: Miquel Raynal <miquel.ray...@free-electrons.com>
---
drivers/mtd/nand/atmel/nand-controller.c | 2 +-
drivers/mtd/nand/brcmnand/brcmnand.c | 9 +-
drivers/mtd/nand/cafe_nand.c | 14 +-
drivers/mtd/nand/denali.c| 2 +-
drivers/mtd/nand/diskonchip.c| 4 +-
drivers/mtd/nand/docg4.c | 7 +-
drivers/mtd/nand/fsmc_nand.c | 5 +-
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 56 +-
drivers/mtd/nand/hisi504_nand.c | 3 +-
drivers/mtd/nand/jz4740_nand.c | 16 +-
drivers/mtd/nand/lpc32xx_mlc.c | 2 +-
drivers/mtd/nand/lpc32xx_slc.c | 22 +-
drivers/mtd/nand/mtk_nand.c | 11 +-
drivers/mtd/nand/nand_base.c | 956 ++-
drivers/mtd/nand/nand_hynix.c| 17 +-
drivers/mtd/nand/nand_micron.c | 17 +-
drivers/mtd/nand/omap2.c | 8 +-
drivers/mtd/nand/pxa3xx_nand.c | 8 +-
drivers/mtd/nand/qcom_nandc.c| 16 +-
drivers/mtd/nand/r852.c | 11 +-
drivers/mtd/nand/sunxi_nand.c| 67 +--
drivers/mtd/nand/tango_nand.c| 26 +-
drivers/mtd/nand/tmio_nand.c | 5 +-
include/linux/mtd/rawnand.h | 25 +
24 files changed, 943 insertions(+), 366 deletions(-)
diff --git a/drivers/mtd/nand/atmel/nand-controller.c
b/drivers/mtd/nand/atmel/nand-controller.c
index 29182160bb5f..0b2c82727b24 100644
--- a/drivers/mtd/nand/atmel/nand-controller.c
+++ b/drivers/mtd/nand/atmel/nand-controller.c
@@ -1000,7 +1000,7 @@ static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip
*chip, u8 *buf,
* to the non-optimized one.
*/
if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+ nand_read_page_op(chip, page, 0, NULL, 0);
return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
raw);
diff --git a/drivers/mtd/nand/brcmnand/brcmnand.c
b/drivers/mtd/nand/brcmnand/brcmnand.c
index e0eb51d8c012..3f441096a14c 100644
--- a/drivers/mtd/nand/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/brcmnand/brcmnand.c
@@ -1071,7 +1071,7 @@ static void brcmnand_wp(struct mtd_info *mtd, int wp)
return;
brcmnand_set_wp(ctrl, wp);
- chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
+ nand_status_op(chip, NULL);
/* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */
ret = bcmnand_ctrl_poll_status(ctrl,
NAND_CTRL_RDY |
@@ -1453,7 +1453,7 @@ static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
/* At FC_BYTES boundary, switch to next column */
if (host->last_byte > 0 && offs == 0)
- chip->cmdfunc(mtd, NAND_CMD_RNDOUT, addr, -1);
+ nand_change_read_column_op(chip, addr, NULL, 0, false);
ret = ctrl->flash_cache[offs];
break;
@@ -1689,7 +1689,7 @@ static int brcmstb_nand_verify_erased_page(struct
mtd_info *mtd,
sas = mtd->oobsize / chip->ecc.steps;
/* read without ecc for verification */
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+ nand_read_page_op(chip, page, 0, NULL, 0);
ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page);
if (ret)
return ret;
@@ -2369,12 +2369,11 @@ static int brcmnand_resume(struct device *dev)
list_for_each_entry(host, >host_list, node) {
struct nand_chip *chip = >chip;
- struct mtd_info *mtd = nand_to_mtd(chip);
brcmnand_save_restore_cs_config(host, 1);
/* Reset the chip, required by some chips after power-up */
- chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ nand_reset_op(chip);
}
return 0;
diff --git a/drivers/mtd/nand/cafe_nand.c b/drivers/mtd/nand/cafe_nand.c
index bc558c438a57..95c2cfa68b66 100644
--- a/drivers/mtd/nand/cafe_nand.c
+++ b/drivers/mtd/nand/cafe_nand.c
@@ -353,23 +353,15 @@ static void cafe_nand_bug(struct mtd_info *mtd)
static int cafe_nand_write_oob(struc
[RFC 05/12] dt-bindings: mtd: add Marvell NAND controller documentation
Document the bindings for the legacy and the new bindings relative to
Marvell NAND controller driver rework.
Signed-off-by: Miquel Raynal <miquel.ray...@free-electrons.com>
---
.../devicetree/bindings/mtd/marvell-nand.txt | 95 ++
1 file changed, 95 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/marvell-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/marvell-nand.txt
b/Documentation/devicetree/bindings/mtd/marvell-nand.txt
new file mode 100644
index ..ea99f426c03f
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/marvell-nand.txt
@@ -0,0 +1,95 @@
+Marvell NAND Flash Controller (NFC)
+
+Required properties:
+C'est faux, t'en a rajouté un y a pas longtps :).
+Je conseille de mettre ça sous forme de liste, genre
+
+- compatible: can be one of the following:
+* "marvell,armada-8k-nand-controller"
+* "marvell,armada370-nand-controller"
+* "marvell,pxa3xx-nand-controller"
+* "marvell,armada-8k-nand" (deprecated)
+* "marvell,armada370-nand" (deprecated)
+* "marvell,pxa3xx-nand" (deprecated)
+- reg: shall contain registers location and length for data and reg.
+- #address-cells: shall be set to 1. Encode the nand CS.
+- #size-cells: shall be set to 0.
+- interrupts: shall define the nand controller interrupt.
+- clocks: shall reference nand controller clocks.
+- marvell,system-controller: Set to retrieve the syscon node that handles
+ NAND controller related registers (only required with the
+ "marvell,armada-8k-nand[-controller]" compatibles).
+
+Optional properties:
+- dmas: shall reference DMA channel associated to the NAND controller.
+- dma-names: shall be "rxtx".
+
+Optional children nodes:
+Children nodes represent the available NAND chips.
+
+Required properties:
+- reg: shall contain the native Chip Select ids (0-3)
+- marvell,rb: shall contain the native Ready/Busy ids (0-1)
+
+Optional properties:
+- marvell,nand-keep-config: orders the driver not to take the timings
+ from the core and leaving them completely untouched. Bootloader
+ timings will then be used.
+- marvell,nand-enable-arbiter: only useful for PXA platforms, will
+ enable bus arbiter between NFC and DFI bus (must be enabled for
+ NFC operation)
+- nand-on-flash-bbt: speed up the boot process by not discovering all
+ the bad blocks at each boot and reading directly an on flash table.
+- nand-ecc-mode: one of the supported ECC modes ("none", "soft",
+ "hw"). If not specified, hardware ECC will be used.
+- nand-ecc-algo: algorithm to use if previous choice was "soft"
+ ("hamming" or "bch). This property may be added for hardware ECC for
+ clarification but will be ignored by the driver because ECC mode is
+ chosen depending on the page size and the strength required by the
+ NAND chip. This value may be overwritten with the nand-ecc-strength
+ property.
+- nand-ecc-strength: desired ECC strength.
+- nand-ecc-step-size: indication on the ECC step size. This has no
+ effect and will be ignored by the driver when using hardware
+ ECC. Because Marvell's NAND flash controller does use fixed strength
+ (1-bit for Hamming, 16-bit for BCH), the step size will shrink or
+ grown in order to fit the required strength and the value
+ updated. Step sizes are not completely random for all and follow
+ certain patterns described in AN-379, "Marvell SoC NFC ECC".
+
+See Documentation/devicetree/bindings/mtd/nand.txt for more details on
+generic bindings.
+
+
+Example:
+nand_controller: nand-controller@d {
+ compatible = "marvell,armada370-nand-controller";
+ reg = <0xd 0x54>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = ;
+ clocks = < 0>;
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ marvell,rb = <0>;
+ nand-ecc-mode = "hw";
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "Rootfs";
+ reg = <0x 0x4000>;
+ };
+ };
+ };
+};
--
2.11.0
___
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http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
[RFC 06/12] mtd: nand: add reworked Marvell NAND controller driver
Add marvell_nand driver which aims at replacing the existing pxa3xx_nand driver. The new driver intends to be easier to understand and follows the brand new NAND framework rules by implementing hooks for every pattern the controller might support and referencing them inside a parser object that will be given to the core at each ->exec_op() call. Raw accessors are implemented, useful to test/debug memory/filesystem corruptions. Userspace binaries contained in the mtd-utils package may now be used and their output trusted. Timings may not be kept from the bootloader anymore, the timings used for instance in U-Boot were not optimal and it supposed to have NAND support (and initialized) in the bootloader. Thanks to the improved timings, implementation of ONFI mode 5 support (with EDO managed by adding a delay on data sampling), merging the commands together and optimizing writes in the command registers, the new driver may achieve faster throughputs in both directions. Measurements show an improvement of about +23% read throughput and +24% write throughput. These measurements have been done with an Armada-385-DB-AP (4kiB NAND pages forced in 4-bit strength BCH ECC correction) using the userspace tool 'flash_speed' from the MTD test suite. Besides these important topics, the new driver addresses several unsolved known issues in the old driver which: - did not work with ECC soft neither with ECC none ; - relied on naked read/write (which is unchanged) while the NFCv1 embedded in the pxa3xx platforms do not implement it, so several NAND commands did not actually ever work without any notice (like reading the ONFI PARAM_PAGE or SET/GET_FEATURES) ; - wrote the OOB data correctly, but was not able to read it correctly past the first OOB data chunk ; - did not displayed ECC bytes ; - used device tree bindings that did not allow more than one NAND chip, and did not allow to choose the correct chip select if not incrementing from 0. Plus, the Ready/Busy line used had to be 0. Old device tree bindings are still supported but deprecated. A more hierarchical view has to be used to keep the controller and the NAND chip structures clearly separated both inside the device tree and also in the driver code. Signed-off-by: Miquel Raynal <miquel.ray...@free-electrons.com> --- drivers/mtd/nand/Kconfig| 11 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/marvell_nand.c | 2384 +++ 3 files changed, 2396 insertions(+) create mode 100644 drivers/mtd/nand/marvell_nand.c diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index bb48aafed9a2..8a64a18b9d26 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -323,6 +323,17 @@ config MTD_NAND_PXA3xx platforms (XP, 370, 375, 38x, 39x) and 64-bit Armada platforms (7K, 8K) (NFCv2). +config MTD_NAND_MARVELL + tristate "NAND controller support on Marvell boards" + depends on PXA3xx || ARCH_MMP || PLAT_ORION || ARCH_MVEBU || \ + (COMPILE_TEST && HAS_IOMEM) + help + This enables the NAND flash controller driver for Marvell boards, + including: + - PXA3xx processors (NFCv1) + - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2) + - 64-bit Aramda platforms (7k, 8k) (NFCv2) + config MTD_NAND_SLC_LPC32XX tristate "NXP LPC32xx SLC Controller" depends on ARCH_LPC32XX diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index ade5fc4c3819..828332dfe18c 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_MTD_NAND_OMAP2) += omap2_nand.o obj-$(CONFIG_MTD_NAND_OMAP_BCH_BUILD) += omap_elm.o obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o +obj-$(CONFIG_MTD_NAND_MARVELL) += marvell_nand.o obj-$(CONFIG_MTD_NAND_TMIO)+= tmio_nand.o obj-$(CONFIG_MTD_NAND_PLATFORM)+= plat_nand.o obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o diff --git a/drivers/mtd/nand/marvell_nand.c b/drivers/mtd/nand/marvell_nand.c new file mode 100644 index ..557817a6f4b6 --- /dev/null +++ b/drivers/mtd/nand/marvell_nand.c @@ -0,0 +1,2384 @@ +/* + * Marvell NAND flash controller driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Copyright (C) 2017 Marvell + * Author: Miquel RAYNAL <miquel.ray...@free-electrons.com> + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Data FIFO granularity, FIFO reads/writes must be a multiple of this length */ +#define FIFO_DEPTH 8 +#define FIFO_REP(x)(x / sizeof(u32)) +#define FIFO_DEPTH_32
[RFC 04/12] mtd: nand: add ->exec_op() implementation
Introduce the new way to control the NAND controller drivers by
implementing the ->exec_op() core helpers and allowing new drivers to
use it instead of relying on ->cmd_ctrl(), ->cmdfunc() and
->read/write_byte/word/buf().
The logic is now to send to the controller driver a list of
instructions. The driver shall use the parser added by this commit to
get the matching hook if any. The instructions may be split by the
parser in order to comply with the controller constraints filled in an
array of supported patterns.
Various helpers are also added to ease NAND controller drivers writing.
This new interface should really ease the support of new vendor specific
instructions.
Suggested-by: Boris Brezillon <boris.brezil...@free-electrons.com>
Signed-off-by: Miquel Raynal <miquel.ray...@free-electrons.com>
---
drivers/mtd/nand/denali.c | 93 +++-
drivers/mtd/nand/nand_base.c | 949 +++--
drivers/mtd/nand/nand_hynix.c | 91 +++-
drivers/mtd/nand/nand_micron.c | 32 +-
include/linux/mtd/rawnand.h| 366 +++-
5 files changed, 1448 insertions(+), 83 deletions(-)
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index e5f38359f6df..8f0f18d9d9cf 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -652,8 +652,6 @@ static void denali_oob_xfer(struct mtd_info *mtd, struct
nand_chip *chip,
int page, int write)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
- unsigned int start_cmd = write ? NAND_CMD_SEQIN : NAND_CMD_READ0;
- unsigned int rnd_cmd = write ? NAND_CMD_RNDIN : NAND_CMD_RNDOUT;
int writesize = mtd->writesize;
int oobsize = mtd->oobsize;
uint8_t *bufpoi = chip->oob_poi;
@@ -665,11 +663,22 @@ static void denali_oob_xfer(struct mtd_info *mtd, struct
nand_chip *chip,
int i, pos, len;
/* BBM at the beginning of the OOB area */
- chip->cmdfunc(mtd, start_cmd, writesize, page);
- if (write)
- chip->write_buf(mtd, bufpoi, oob_skip);
- else
- chip->read_buf(mtd, bufpoi, oob_skip);
+ if (chip->exec_op) {
+ if (write)
+ nand_prog_page_begin_op(chip, page, writesize, bufpoi,
+ oob_skip);
+ else
+ nand_read_page_op(chip, page, writesize, bufpoi,
+ oob_skip);
+ } else {
+ if (write) {
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, writesize, page);
+ chip->write_buf(mtd, bufpoi, oob_skip);
+ } else {
+ chip->cmdfunc(mtd, NAND_CMD_READ0, writesize, page);
+ chip->read_buf(mtd, bufpoi, oob_skip);
+ }
+ }
bufpoi += oob_skip;
/* OOB ECC */
@@ -682,30 +691,67 @@ static void denali_oob_xfer(struct mtd_info *mtd, struct
nand_chip *chip,
else if (pos + len > writesize)
len = writesize - pos;
- chip->cmdfunc(mtd, rnd_cmd, pos, -1);
- if (write)
- chip->write_buf(mtd, bufpoi, len);
- else
- chip->read_buf(mtd, bufpoi, len);
- bufpoi += len;
- if (len < ecc_bytes) {
- len = ecc_bytes - len;
- chip->cmdfunc(mtd, rnd_cmd, writesize + oob_skip, -1);
+ if (chip->exec_op) {
if (write)
- chip->write_buf(mtd, bufpoi, len);
+ nand_change_write_column_op(
+ chip, pos, bufpoi, len, false);
else
+ nand_change_read_column_op(
+ chip, pos, bufpoi, len, false);
+ } else {
+ if (write) {
+ chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
+ chip->write_buf(mtd, bufpoi, len);
+ } else {
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
chip->read_buf(mtd, bufpoi, len);
+ }
+ }
+ bufpoi += len;
+ if (len < ecc_bytes) {
+ len = ecc_bytes - len;
+ if (chip->exec_op) {
+ if (write)
+ nand_change_write_column_op(
+ chip, writesize + oob_skip,
+ bufpoi, len, false);
+ else
+ nan
[RFC 03/12] mtd: nand: use a static data_interface in the nand_chip structure
Change the data_interface field from the nand_chip structure, convert
the pointer to a static structure.
Also remove the nand_get_default_data_interface() function that become
useless and rename the onfi_init_data_interface() by
nand_fill_data_interface(), which is a more appropriate name because
applied timings are ONFI, no matter if the NAND actually is one.
This is needed before passing to ->exec_op() to avoid any race that
could lead to a panic (null pointer dereference) on the initialization
of the timings structure that will be used from the first reset
operation if the pointer to data_interface was not referenced yet.
Signed-off-by: Miquel Raynal <miquel.ray...@free-electrons.com>
---
drivers/mtd/nand/nand_base.c| 35 ++-
drivers/mtd/nand/nand_timings.c | 23 ++-
include/linux/mtd/rawnand.h | 9 ++---
3 files changed, 18 insertions(+), 49 deletions(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 318595c29053..bef20e06f0db 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -814,8 +814,8 @@ static void nand_ccs_delay(struct nand_chip *chip)
* Wait tCCS_min if it is correctly defined, otherwise wait 500ns
* (which should be safe for all NANDs).
*/
- if (chip->data_interface && chip->data_interface->timings.sdr.tCCS_min)
- ndelay(chip->data_interface->timings.sdr.tCCS_min / 1000);
+ if (chip->data_interface.timings.sdr.tCCS_min)
+ ndelay(chip->data_interface.timings.sdr.tCCS_min / 1000);
else
ndelay(500);
}
@@ -1107,7 +1107,6 @@ static int nand_wait(struct mtd_info *mtd, struct
nand_chip *chip)
static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
{
struct mtd_info *mtd = nand_to_mtd(chip);
- const struct nand_data_interface *conf;
int ret;
if (!chip->setup_data_interface)
@@ -1127,8 +1126,8 @@ static int nand_reset_data_interface(struct nand_chip
*chip, int chipnr)
* timings to timing mode 0.
*/
- conf = nand_get_default_data_interface();
- ret = chip->setup_data_interface(mtd, chipnr, conf);
+ nand_fill_data_interface(chip, 0);
+ ret = chip->setup_data_interface(mtd, chipnr, >data_interface);
if (ret)
pr_err("Failed to configure data interface to SDR timing mode
0\n");
@@ -1153,7 +1152,7 @@ static int nand_setup_data_interface(struct nand_chip
*chip, int chipnr)
struct mtd_info *mtd = nand_to_mtd(chip);
int ret;
- if (!chip->setup_data_interface || !chip->data_interface)
+ if (!chip->setup_data_interface)
return 0;
/*
@@ -1174,7 +1173,7 @@ static int nand_setup_data_interface(struct nand_chip
*chip, int chipnr)
goto err;
}
- ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface);
+ ret = chip->setup_data_interface(mtd, chipnr, >data_interface);
err:
return ret;
}
@@ -1214,21 +1213,16 @@ static int nand_init_data_interface(struct nand_chip
*chip)
modes = GENMASK(chip->onfi_timing_mode_default, 0);
}
- chip->data_interface = kzalloc(sizeof(*chip->data_interface),
- GFP_KERNEL);
- if (!chip->data_interface)
- return -ENOMEM;
for (mode = fls(modes) - 1; mode >= 0; mode--) {
- ret = onfi_init_data_interface(chip, chip->data_interface,
- NAND_SDR_IFACE, mode);
+ ret = nand_fill_data_interface(chip, mode);
if (ret)
continue;
/* Pass -1 to only */
ret = chip->setup_data_interface(mtd,
NAND_DATA_IFACE_CHECK_ONLY,
-chip->data_interface);
+>data_interface);
if (!ret) {
chip->onfi_timing_mode_default = mode;
break;
@@ -1238,11 +1232,6 @@ static int nand_init_data_interface(struct nand_chip
*chip)
return 0;
}
-static void nand_release_data_interface(struct nand_chip *chip)
-{
- kfree(chip->data_interface);
-}
-
/**
* nand_read_page_op - Do a READ PAGE operation
* @chip: The NAND chip
@@ -5567,7 +5556,7 @@ int nand_scan_tail(struct mtd_info *mtd)
chip->select_chip(mtd, -1);
if (ret)
- goto err_nand_data_iface_cleanup;
+ goto err_nand_manuf_cleanup;
}
/* Check, if we should skip the bad block table scan */
@@ -5577,12 +5566,10 @@ int nand_scan_tail(struct mtd_in
[RFC 00/12] Marvell NAND controller rework with ->exec_op()
Hi, This series adds the implementation of the NAND framework ->exec_op() interface with all the related hooks and helpers. The reasons for adding it are explained in details in the commit log "mtd: nand: add ->exec_op() implementation", but mostly it will ease later expansion of the framework, as well as the implementation of new vendor specific commands, and should also ease driver development. The series contains as well the reworked NAND controller driver from Marvell. A lot of comments are written to explain how to use the new API and the Marvell driver shows how to implement it. A proper external documentation is being written and will later be submitted. It also changes the device tree NAND node definition for all platforms referring to the Marvell driver to use the new bindings. They are more hierarchical and fit the real organization of the hardware, by having NAND partitions that are part of NAND chip nodes, themselves part of the NAND controller node. See the commit log of "mtd: nand: add reworked Marvell NAND controller driver" for details about why a completely new driver is needed. As this series changes several core functions and also directly touches multiple controller drivers, it would be great to have reviews and tests from the concerned maintainers. Only PXA3xx SoCs are not supported yet (explaining the RFC) as having a local board to test is really needed. Thank you, Miquèl Boris Brezillon (2): mtd: nand: provide several helpers to do common NAND operations mtd: nand: force drivers to explicitly send READ/PROG commands Miquel Raynal (10): mtd: nand: use a static data_interface in the nand_chip structure mtd: nand: add ->exec_op() implementation dt-bindings: mtd: add Marvell NAND controller documentation mtd: nand: add reworked Marvell NAND controller driver ARM: dts: armada-370-xp: use reworked NAND controller driver ARM: dts: armada-375: use reworked NAND controller driver ARM: dts: armada-38x: use reworked NAND controller driver ARM: dts: armada-39x: use reworked NAND controller driver ARM: dts: pxa: use reworked NAND controller driver ARM64: dts: marvell: use reworked NAND controller driver on Armada 7K/8K .../devicetree/bindings/mtd/marvell-nand.txt | 95 + arch/arm/boot/dts/armada-370-db.dts| 56 +- arch/arm/boot/dts/armada-370-dlink-dns327l.dts | 119 +- arch/arm/boot/dts/armada-370-mirabox.dts | 50 +- arch/arm/boot/dts/armada-370-netgear-rn102.dts | 89 +- arch/arm/boot/dts/armada-370-netgear-rn104.dts | 89 +- arch/arm/boot/dts/armada-370-rd.dts| 51 +- arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi | 63 +- arch/arm/boot/dts/armada-370-xp.dtsi |6 +- arch/arm/boot/dts/armada-375-db.dts| 49 +- arch/arm/boot/dts/armada-375.dtsi |6 +- arch/arm/boot/dts/armada-385-db-ap.dts | 68 +- arch/arm/boot/dts/armada-385-linksys-caiman.dts| 129 +- arch/arm/boot/dts/armada-385-linksys-cobra.dts | 129 +- arch/arm/boot/dts/armada-385-linksys-rango.dts | 141 +- arch/arm/boot/dts/armada-385-linksys-shelby.dts| 129 +- arch/arm/boot/dts/armada-385-linksys.dtsi | 15 +- arch/arm/boot/dts/armada-388-db.dts| 54 +- arch/arm/boot/dts/armada-38x.dtsi |6 +- arch/arm/boot/dts/armada-390-db.dts| 65 +- arch/arm/boot/dts/armada-395-gp.dts| 73 +- arch/arm/boot/dts/armada-398-db.dts| 59 +- arch/arm/boot/dts/armada-39x.dtsi |6 +- arch/arm/boot/dts/armada-xp-db-dxbc2.dts |1 - arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts |1 - arch/arm/boot/dts/armada-xp-db.dts |1 - arch/arm/boot/dts/armada-xp-gp.dts |1 - arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts|1 - arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 155 +- arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 89 +- arch/arm/boot/dts/pxa3xx.dtsi |6 +- arch/arm64/boot/dts/marvell/armada-7040-db.dts | 47 +- .../boot/dts/marvell/armada-cp110-master.dtsi |6 +- .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi |6 +- drivers/mtd/nand/Kconfig | 11 + drivers/mtd/nand/Makefile |1 + drivers/mtd/nand/atmel/nand-controller.c |9 +- drivers/mtd/nand/bf5xx_nand.c |6 +- drivers/mtd/nand/brcmnand/brcmnand.c | 20 +- drivers/mtd/nand/cafe_nand.c | 20 +- drivers/mtd/nand/denali.c | 109 +- drivers/mtd/nand/diskonchip.c |4 +- drivers/mtd/nand/docg4.c | 19 +- drivers/mtd/nand/fsl_elbc_nand.c |6 +- drivers/mtd/nand/fsl_ifc_nand.c
[RFC 09/12] ARM: dts: armada-38x: use reworked NAND controller driver
Change the bindings to use the reworked Marvell NAND controller driver.
Also adapt the nand controller node organization to distinguish which
property is relevant for the controller, and which one is NAND chip
specific. Expose the partitions as a subnode of the NAND chip.
Remove the 'marvell,nand-enable-arbiter' property, inefective with
Armada boards.
Signed-off-by: Miquel Raynal <miquel.ray...@free-electrons.com>
---
arch/arm/boot/dts/armada-385-db-ap.dts | 68 ++--
arch/arm/boot/dts/armada-385-linksys-caiman.dts | 129 +++---
arch/arm/boot/dts/armada-385-linksys-cobra.dts | 129 +++---
arch/arm/boot/dts/armada-385-linksys-rango.dts | 141
arch/arm/boot/dts/armada-385-linksys-shelby.dts | 129 +++---
arch/arm/boot/dts/armada-385-linksys.dtsi | 15 ++-
arch/arm/boot/dts/armada-388-db.dts | 54 +
arch/arm/boot/dts/armada-38x.dtsi | 6 +-
8 files changed, 353 insertions(+), 318 deletions(-)
diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts
b/arch/arm/boot/dts/armada-385-db-ap.dts
index 25d2d720dc0e..625691196acb 100644
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
@@ -166,39 +166,6 @@
status = "okay";
};
- nfc: flash@d {
- status = "okay";
- num-cs = <1>;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
- marvell,nand-keep-config;
- marvell,nand-enable-arbiter;
- nand-on-flash-bbt;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "U-Boot";
- reg = <0x 0x0080>;
- read-only;
- };
-
- partition@80 {
- label = "uImage";
- reg = <0x0080 0x0040>;
- read-only;
- };
-
- partition@c0 {
- label = "Root";
- reg = <0x00c0 0x3f40>;
- };
- };
- };
-
usb3@f {
status = "okay";
usb-phy = <_phy>;
@@ -263,3 +230,38 @@
spi-max-frequency = <5400>;
};
};
+
+_controller {
+ status = "okay";
+
+ nand@0 {
+ reg = <0>;
+ marvell,rb = <0>;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x 0x0080>;
+ read-only;
+ };
+
+ partition@80 {
+ label = "uImage";
+ reg = <0x0080 0x0040>;
+ read-only;
+ };
+
+ partition@c0 {
+ label = "Root";
+ reg = <0x00c0 0x3f40>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
index ee669ae61011..e769bcf7a9d1 100644
--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
@@ -105,67 +105,72 @@
{
/* 128MiB */
-
- partition@0 {
- label = "u-boot";
- reg = <0x000 0x20>; /* 2MiB */
- read-only;
-
[RFC 02/12] mtd: nand: force drivers to explicitly send READ/PROG commands
From: Boris Brezillon <boris.brezil...@free-electrons.com>
The core currently send the READ0 and SEQIN+PAGEPROG commands in
nand_do_read/write_ops(). This is inconsistent with
->read/write_oob[_raw]() hooks behavior which are expected to send
these commands.
There's already a flag (NAND_ECC_CUSTOM_PAGE_ACCESS) to inform the core
that a specific controller wants to send the READ/SEQIN+PAGEPROG
commands on its own, but it's an opt-in flag, and existing drivers are
unlikely to be updated to pass it.
Moreover, some controllers cannot dissociate the READ/PAGEPROG commands
from the associated data transfer and ECC engine activation, and
developers have to hack things in their ->cmdfunc() implementation to
handle such complex cases, or have to accept the perf penalty of sending
twice the same command.
To address this problem we are planning on adding a new interface which
is passed all information about a NAND operation (including the amount
of data to transfer) and replacing all calls to ->cmdfunc() to calls to
this new ->exec_op() hook. But, in order to do that, we need to have all
->cmdfunc() calls placed near their associated ->read/write_buf/byte()
calls.
Modify the core and relevant drivers to make NAND_ECC_CUSTOM_PAGE_ACCESS
the default case, and remove this flag.
Signed-off-by: Boris Brezillon <boris.brezil...@free-electrons.com>
[miquel.ray...@free-electrons.com: rebased and fixed some conflicts]
Signed-off-by: Miquel Raynal <miquel.ray...@free-electrons.com>
---
drivers/mtd/nand/atmel/nand-controller.c | 7 ++-
drivers/mtd/nand/bf5xx_nand.c | 6 ++-
drivers/mtd/nand/brcmnand/brcmnand.c | 13 +++--
drivers/mtd/nand/cafe_nand.c | 6 +--
drivers/mtd/nand/denali.c | 14 +-
drivers/mtd/nand/docg4.c | 12 +++--
drivers/mtd/nand/fsl_elbc_nand.c | 6 +--
drivers/mtd/nand/fsl_ifc_nand.c | 6 +--
drivers/mtd/nand/gpmi-nand/gpmi-nand.c| 30 ++--
drivers/mtd/nand/hisi504_nand.c | 6 +--
drivers/mtd/nand/lpc32xx_mlc.c| 5 +-
drivers/mtd/nand/lpc32xx_slc.c| 11 +++--
drivers/mtd/nand/mtk_nand.c | 10 ++--
drivers/mtd/nand/nand_base.c | 68 +--
drivers/mtd/nand/nand_micron.c| 1 -
drivers/mtd/nand/sh_flctl.c | 6 +--
drivers/mtd/nand/sunxi_nand.c | 34 +-
drivers/mtd/nand/tango_nand.c | 1 -
drivers/mtd/nand/vf610_nfc.c | 6 +--
drivers/staging/mt29f_spinand/mt29f_spinand.c | 7 ++-
include/linux/mtd/rawnand.h | 11 -
21 files changed, 142 insertions(+), 124 deletions(-)
diff --git a/drivers/mtd/nand/atmel/nand-controller.c
b/drivers/mtd/nand/atmel/nand-controller.c
index 0b2c82727b24..6add993ea1e0 100644
--- a/drivers/mtd/nand/atmel/nand-controller.c
+++ b/drivers/mtd/nand/atmel/nand-controller.c
@@ -841,6 +841,8 @@ static int atmel_nand_pmecc_write_pg(struct nand_chip
*chip, const u8 *buf,
struct atmel_nand *nand = to_atmel_nand(chip);
int ret;
+ nand_prog_page_begin_op(chip, page, 0, NULL, 0);
+
ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
if (ret)
return ret;
@@ -857,7 +859,7 @@ static int atmel_nand_pmecc_write_pg(struct nand_chip
*chip, const u8 *buf,
atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
- return 0;
+ return nand_prog_page_end_op(chip);
}
static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
@@ -881,6 +883,8 @@ static int atmel_nand_pmecc_read_pg(struct nand_chip *chip,
u8 *buf,
struct mtd_info *mtd = nand_to_mtd(chip);
int ret;
+ nand_read_page_op(chip, page, 0, NULL, 0);
+
ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
if (ret)
return ret;
@@ -1178,7 +1182,6 @@ static int atmel_hsmc_nand_ecc_init(struct atmel_nand
*nand)
chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
- chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
return 0;
}
diff --git a/drivers/mtd/nand/bf5xx_nand.c b/drivers/mtd/nand/bf5xx_nand.c
index 5655dca6ce43..87bbd177b3e5 100644
--- a/drivers/mtd/nand/bf5xx_nand.c
+++ b/drivers/mtd/nand/bf5xx_nand.c
@@ -572,6 +572,8 @@ static void bf5xx_nand_dma_write_buf(struct mtd_info *mtd,
static int bf5xx_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip
*chip,
uint8_t *buf, int oob_required, int page)
{
+ nand_read_page_op(chip, page, 0, NULL, 0);
+
bf5xx_nand_read_buf(mtd, buf, mtd->writesize);
bf5xx_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
@@
