hdmi phy configuration is platform specific, which can be adusted
according to the board to get the best SI
Signed-off-by: Andy Yan andy@rock-chips.com
---
Changes in v18: None
Changes in v17: None
Changes in v16: None
Changes in v15: None
Changes in v14: None
Changes in v13:
- split phy configuration from patch#4
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
drivers/gpu/drm/imx/imx-hdmi.c | 85 +++-
drivers/gpu/drm/imx/imx-hdmi.h | 29
drivers/gpu/drm/imx/imx-hdmi_pltfm.c | 57
3 files changed, 101 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/imx/imx-hdmi.c b/drivers/gpu/drm/imx/imx-hdmi.c
index d72f82c..409fb4f 100644
--- a/drivers/gpu/drm/imx/imx-hdmi.c
+++ b/drivers/gpu/drm/imx/imx-hdmi.c
@@ -713,76 +713,14 @@ static void imx_hdmi_phy_sel_interface_control(struct
imx_hdmi *hdmi, u8 enable)
HDMI_PHY_CONF0_SELDIPIF_MASK);
}
-enum {
- RES_8,
- RES_10,
- RES_12,
- RES_MAX,
-};
-
-struct mpll_config {
- unsigned long mpixelclock;
- struct {
- u16 cpce;
- u16 gmp;
- } res[RES_MAX];
-};
-
-static const struct mpll_config mpll_config[] = {
- {
- 4525, {
- { 0x01e0, 0x },
- { 0x21e1, 0x },
- { 0x41e2, 0x }
- },
- }, {
- 9250, {
- { 0x0140, 0x0005 },
- { 0x2141, 0x0005 },
- { 0x4142, 0x0005 },
- },
- }, {
- 14850, {
- { 0x00a0, 0x000a },
- { 0x20a1, 0x000a },
- { 0x40a2, 0x000a },
- },
- }, {
- ~0UL, {
- { 0x00a0, 0x000a },
- { 0x2001, 0x000f },
- { 0x4002, 0x000f },
- },
- }
-};
-
-struct curr_ctrl {
- unsigned long mpixelclock;
- u16 curr[RES_MAX];
-};
-
-static const struct curr_ctrl curr_ctrl[] = {
- /* pixelclk bpp8bpp10 bpp12 */
- {
-5400, { 0x091c, 0x091c, 0x06dc },
- }, {
-5840, { 0x091c, 0x06dc, 0x06dc },
- }, {
-7200, { 0x06dc, 0x06dc, 0x091c },
- }, {
-7425, { 0x06dc, 0x0b5c, 0x091c },
- }, {
- 11880, { 0x091c, 0x091c, 0x06dc },
- }, {
- 21600, { 0x06dc, 0x0b5c, 0x091c },
- }
-};
-
static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep,
unsigned char res, int cscon)
{
unsigned res_idx, i;
u8 val, msec;
+ const struct mpll_config *mpll_config = hdmi-plat_data-mpll_cfg;
+ const struct curr_ctrl *curr_ctrl = hdmi-plat_data-cur_ctr;
+ const struct sym_term *sym_term = hdmi-plat_data-sym_term;
if (prep)
return -EINVAL;
@@ -828,7 +766,7 @@ static int hdmi_phy_configure(struct imx_hdmi *hdmi,
unsigned char prep,
hdmi_phy_test_clear(hdmi, 0);
/* PLL/MPLL Cfg - always match on final entry */
- for (i = 0; i ARRAY_SIZE(mpll_config) - 1; i++)
+ for (i = 0; mpll_config[i].mpixelclock != (~0UL); i++)
if (hdmi-hdmi_data.video_mode.mpixelclock =
mpll_config[i].mpixelclock)
break;
@@ -836,12 +774,12 @@ static int hdmi_phy_configure(struct imx_hdmi *hdmi,
unsigned char prep,
hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].cpce, 0x06);
hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].gmp, 0x15);
- for (i = 0; i ARRAY_SIZE(curr_ctrl); i++)
+ for (i = 0; curr_ctrl[i].mpixelclock != (~0UL); i++)
if (hdmi-hdmi_data.video_mode.mpixelclock =
curr_ctrl[i].mpixelclock)
break;
- if (i = ARRAY_SIZE(curr_ctrl)) {
+ if (curr_ctrl[i].mpixelclock == (~0UL)) {
dev_err(hdmi-dev, Pixel clock %d - unsupported by HDMI\n,
hdmi-hdmi_data.video_mode.mpixelclock);
return -EINVAL;
@@ -852,10 +790,17 @@ static int hdmi_phy_configure(struct imx_hdmi *hdmi,
unsigned char prep,
hdmi_phy_i2c_write(hdmi, 0x, 0x13); /* PLLPHBYCTRL */
hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
+
+ for (i = 0; sym_term[i].mpixelclock != (~0UL); i++)
+ if (hdmi-hdmi_data.video_mode.mpixelclock =
+ sym_term[i].mpixelclock)
+ break;
+
/* RESISTANCE TERM 133Ohm Cfg */
- hdmi_phy_i2c_write(hdmi, 0x0005, 0x19); /* TXTERM */
+
