Re: [PATCH] imx-drm: ipuv3-crtc: Invert IPU DI0 clock polarity

2013-10-29 Thread Russell King - ARM Linux
On Tue, Oct 29, 2013 at 07:42:22PM -0200, Fabio Estevam wrote:
 From: Fabio Estevam fabio.este...@freescale.com
 
 sig_cfg.clk_pol controls the 'di0_polarity_disp_clk' bit of register
 IPUx_DI0_GENERAL through the following code in imx-drm/ipu-v3/ipu-di.c:
 
   if (!sig-clk_pol)
   di_gen |= DI_GEN_POLARITY_DISP_CLK;
 
 With 'di0_polarity_disp_clk' bit set we do not have stable HDMI output on 
 mx6solo: contours of pictures look jittery and the white colour does not
 appear really white.
 
 Russell King initially reported this problem at:
 http://www.spinics.net/lists/arm-kernel/msg279805.html

There's slightly more to this than that mail, and I have to raise the
issue about whether this is the correct fix or not.  See:

http://www.spinics.net/lists/arm-kernel/msg279902.html
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Re: [PATCH] imx-drm: ipuv3-crtc: Invert IPU DI0 clock polarity

2013-10-29 Thread Fabio Estevam
Hi Russell,

On Tue, Oct 29, 2013 at 9:25 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:

 There's slightly more to this than that mail, and I have to raise the
 issue about whether this is the correct fix or not.  See:

 http://www.spinics.net/lists/arm-kernel/msg279902.html

Today I also checked U-boot HDMI splash screen on mx6solo and it was
not stable either.

Using FSL kernel 4.1.0 as reference (and also the suggestion from
Sascha), I sent the following patch to U-boot that fixes the HDMI
output on mx6solo:
http://marc.info/?l=u-bootm=138306883309837w=2

Also noticed that the cubox-i U-boot has this workaround:
https://github.com/linux4kix/u-boot/commit/cc938e0c662092b96ffb32c2e8aac416a1b12e57

,which also results in bit 17 'di0_polarity_disp_clk' being cleared.

Looking at FSL kernel, they have the FB_SYNC_CLK_LAT_FALL flag to set bit17.

However this is only used at:
arch/arm/mach-mx6/board-mx6sl_arm2.c:
arch/arm/mach-mx6/board-mx6sl_evk.c:
arch/arm/mach-mx6/board-mx6sl_evk.c:

,which are all mx6sl boards and mx6sl does not have IPU.

Also tested on all the IPUv3 hardware I have access to and all of them
work fine with di0_polarity_disp_clk cleared.

Regards,

Fabio Estevam
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