[edk2] EDK2 build issues
Hello, Here are some observations I've encountered trying to utilize edk2 for certain builds. Part of the problem seems to be with implicit assumptions in how edk2 is used. I'm trying to build things using edk2 from a clean enviroment on an automated builder. i.e. there isn't a workspace that exists on one persons computer for the lifetime of development. 1. BaseTools can't build in parallel. The tests are racey which result in test failures. Because of this one has to build these in serial instead of in parallel. == FAIL: testHelp (TianoCompress.Tests) -- Traceback (most recent call last): File "/build/zoombini/tmp/portage/sys-boot/fsp-cnl-/work/fsp-cnl-/Edk2/BaseTools/Tests/TianoCompress.py", line 34, in testHelp self.assertTrue(result == 0) AssertionError: False is not true == FAIL: testRandomDataCycles (TianoCompress.Tests) -- Traceback (most recent call last): File "/build/zoombini/tmp/portage/sys-boot/fsp-cnl-/work/fsp-cnl-/Edk2/BaseTools/Tests/TianoCompress.py", line 65, in testRandomDataCycles self.compressionTestCycle(data) File "/build/zoombini/tmp/portage/sys-boot/fsp-cnl-/work/fsp-cnl-/Edk2/BaseTools/Tests/TianoCompress.py", line 44, in compressionTestCycle self.assertTrue(result == 0) AssertionError: False is not true In addition, it seems compilation even breaks trying to build a parser: VfrSyntax.cpp:53:1: error: expected class-name before '{' token {^M ^ VfrSyntax.cpp: In constructor 'CVfrDLGLexer::CVfrDLGLexer(DLGFileInput*)': VfrSyntax.cpp:55:36: error: class 'CVfrDLGLexer' does not have any field named 'VfrLexer' CVfrDLGLexer (DLGFileInput *F) : VfrLexer (F) {};^M ^ This just slows down builds needing to things serially. 2. It appears the BaseTools uses the ARCH environment variable. I'm not sure of the origins, but ARCH seems like a complete misnomer for the *host* you are trying to build tools on -- not the target. Trying to incorporate edk2 builds into a portage environment effectively breaks because of this as ARCH refers to target architecture -- not host builder's ARCH. 3. This more of an observation, but the tools definition seems to make quite the leap on how consistent compilers are of a certain version. e.g. GCC 4.9 can be built with all kinds of default options that edk2 implicitly assumes are set based on some distribution's default flags? And in order to extend toolchain support one needs to create a series of entries associated with a certain family. Barrier to entry is pretty high in teasing out where to put things in the ~8000 line tools_def.template. Thanks for the consideration. -Aaron ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] stdlib broken strncasecmp.c
I would submit a patch but over the years of fixes and enhancements, they don't go anywhere. Then a couple years later someone does a half-baked fix and I have to run merge resolution on svn. Anyway, the problem with that is the s1 compare to 0 should be before the s1++ (otherwise it matches when the s1 string is shorter than the s2 string). ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
Re: [edk2] [PATCH 2/4] OvmfPkg/Sec/Ia32: seed the temporary RAM with PcdInitValueInTempStack
On 11/10/17 19:11, Laszlo Ersek wrote: > On 11/10/17 16:56, Ard Biesheuvel wrote: >> On 10 November 2017 at 15:49, Laszlo Ersekwrote: >>> This allows the PEI core to report the maximum temporary SEC/PEI stack >>> usage on the DEBUG_INFO level, in the PeiCheckAndSwitchStack() function >>> [MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c]: >>> >>> * Normal boot: >>> Temp Stack : BaseAddress=0x814000 Length=0x4000 Temp Heap : BaseAddress=0x81 Length=0x4000 Total temporary memory:32768 bytes. temporary memory stack ever used: 3664 bytes. < temporary memory heap used for HobList: 5904 bytes. temporary memory heap occupied by memory pages: 0 bytes. >>> >>> * S3 resume (with PEI decompression / SMM): >>> Temp Stack : BaseAddress=0x814000 Length=0x4000 Temp Heap : BaseAddress=0x81 Length=0x4000 Total temporary memory:32768 bytes. temporary memory stack ever used: 3428 bytes. < temporary memory heap used for HobList: 4816 bytes. temporary memory heap occupied by memory pages: 0 bytes. >>> >>> I unit-tested this change by transitorily adding an infinite loop right >>> after the "rep stosd", and dumping the guest's temp SEC/PEI RAM (32KB >>> currently) while the guest was stuck in the loop. The dump includes one >>> dword from before and after the temp SEC/PEI RAM: >>> $ virsh qemu-monitor-command GUEST_NAME --hmp 'xp /8194wx 0x80FFFC' 0080fffc: 0x 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 0081000c: 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 ... 00817fec: 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 00817ffc: 0x5aa55aa5 0x >>> >>> Cc: Ard Biesheuvel >>> Cc: Jordan Justen >>> Cc: Ruiyu Ni >>> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=747 >>> Contributed-under: TianoCore Contribution Agreement 1.1 >>> Signed-off-by: Laszlo Ersek >>> --- >>> OvmfPkg/Sec/SecMain.inf| 1 + >>> OvmfPkg/Sec/Ia32/SecEntry.nasm | 13 + >>> 2 files changed, 14 insertions(+) >>> >>> diff --git a/OvmfPkg/Sec/SecMain.inf b/OvmfPkg/Sec/SecMain.inf >>> index 711b59530907..6051cb3c6c4c 100644 >>> --- a/OvmfPkg/Sec/SecMain.inf >>> +++ b/OvmfPkg/Sec/SecMain.inf >>> @@ -71,6 +71,7 @@ [Pcd] >>>gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress >>>gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize >>>gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd >>> + gEfiMdeModulePkgTokenSpaceGuid.PcdInitValueInTempStack >>> >>> [FeaturePcd] >>>gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire >>> diff --git a/OvmfPkg/Sec/Ia32/SecEntry.nasm b/OvmfPkg/Sec/Ia32/SecEntry.nasm >>> index 54d074e621f6..1d426fafa888 100644 >>> --- a/OvmfPkg/Sec/Ia32/SecEntry.nasm >>> +++ b/OvmfPkg/Sec/Ia32/SecEntry.nasm >>> @@ -29,6 +29,7 @@ extern ASM_PFX(SecCoreStartupWithStack) >>> ; @param[in] EAX Initial value of the EAX register (BIST: Built-in Self >>> Test) >>> ; @param[in] DI'BP': boot-strap processor, or 'AP': application >>> processor >>> ; @param[in] EBP Pointer to the start of the Boot Firmware Volume >>> +; @param[in] ESSet to LINEAR_SEL in TransitionFromReal16To32BitFlat >> >> What does this mean? Does it belong in this patch? (Knowing you, and >> noticing that the next patch adds it to the x86 version of this code >> as well, I am sure it probably does, but I just need you to explain it >> to me :-)) > > See the STOSD instruction in the Intel SDM, or just on the web: > > http://x86.renejeschke.de/html/file_module_x86_id_306.html > >> Stores a byte, word, or doubleword from the AL, AX, or EAX register, >> respectively, into the destination operand. The destination operand is >> a memory location, the address of which is read from either the ES:EDI >> or the ES:DI registers (depending on the address-size attribute of the >> instruction, 32 or 16, respectively). The ES segment cannot be >> overridden with a segment override prefix. > > It means that whatever we put in EDI, it will be relative to the segment > "identified by" ES. (See the code comment near "mov edi": "base address, > relative to ES".) > > Above I put "identified by" in quotes, because the definition of > "identified by" depends on the mode the processor is in. > > (Instead of a botched attempt at writing up x86 segmentation (plus, > optionally, paging) generally :) , I'll just leave these references > here: > > * Intel SDM: 2.2 MODES OF OPERATION; Figure 2-3. Transitions Among the > Processor's Operating Modes > > * https://en.wikipedia.org/wiki/Unreal_mode > > * https://en.wikipedia.org/wiki/X86_memory_segmentation#80286_protected_mode > > * https://en.wikipedia.org/wiki/X86_memory_segmentation#80386_protected_mode > ) > > So using STOSD and ES:EDI as an example, here's a hugely inaccurate list > of possible
Re: [edk2] [PATCH 2/4] OvmfPkg/Sec/Ia32: seed the temporary RAM with PcdInitValueInTempStack
On 11/10/17 16:56, Ard Biesheuvel wrote: > On 10 November 2017 at 15:49, Laszlo Ersekwrote: >> This allows the PEI core to report the maximum temporary SEC/PEI stack >> usage on the DEBUG_INFO level, in the PeiCheckAndSwitchStack() function >> [MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c]: >> >> * Normal boot: >> >>> Temp Stack : BaseAddress=0x814000 Length=0x4000 >>> Temp Heap : BaseAddress=0x81 Length=0x4000 >>> Total temporary memory:32768 bytes. >>> temporary memory stack ever used: 3664 bytes. < >>> temporary memory heap used for HobList: 5904 bytes. >>> temporary memory heap occupied by memory pages: 0 bytes. >> >> * S3 resume (with PEI decompression / SMM): >> >>> Temp Stack : BaseAddress=0x814000 Length=0x4000 >>> Temp Heap : BaseAddress=0x81 Length=0x4000 >>> Total temporary memory:32768 bytes. >>> temporary memory stack ever used: 3428 bytes. < >>> temporary memory heap used for HobList: 4816 bytes. >>> temporary memory heap occupied by memory pages: 0 bytes. >> >> I unit-tested this change by transitorily adding an infinite loop right >> after the "rep stosd", and dumping the guest's temp SEC/PEI RAM (32KB >> currently) while the guest was stuck in the loop. The dump includes one >> dword from before and after the temp SEC/PEI RAM: >> >>> $ virsh qemu-monitor-command GUEST_NAME --hmp 'xp /8194wx 0x80FFFC' >>> >>> 0080fffc: 0x 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 >>> 0081000c: 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 >>> ... >>> 00817fec: 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 >>> 00817ffc: 0x5aa55aa5 0x >> >> Cc: Ard Biesheuvel >> Cc: Jordan Justen >> Cc: Ruiyu Ni >> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=747 >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Laszlo Ersek >> --- >> OvmfPkg/Sec/SecMain.inf| 1 + >> OvmfPkg/Sec/Ia32/SecEntry.nasm | 13 + >> 2 files changed, 14 insertions(+) >> >> diff --git a/OvmfPkg/Sec/SecMain.inf b/OvmfPkg/Sec/SecMain.inf >> index 711b59530907..6051cb3c6c4c 100644 >> --- a/OvmfPkg/Sec/SecMain.inf >> +++ b/OvmfPkg/Sec/SecMain.inf >> @@ -71,6 +71,7 @@ [Pcd] >>gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress >>gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize >>gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd >> + gEfiMdeModulePkgTokenSpaceGuid.PcdInitValueInTempStack >> >> [FeaturePcd] >>gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire >> diff --git a/OvmfPkg/Sec/Ia32/SecEntry.nasm b/OvmfPkg/Sec/Ia32/SecEntry.nasm >> index 54d074e621f6..1d426fafa888 100644 >> --- a/OvmfPkg/Sec/Ia32/SecEntry.nasm >> +++ b/OvmfPkg/Sec/Ia32/SecEntry.nasm >> @@ -29,6 +29,7 @@ extern ASM_PFX(SecCoreStartupWithStack) >> ; @param[in] EAX Initial value of the EAX register (BIST: Built-in Self >> Test) >> ; @param[in] DI'BP': boot-strap processor, or 'AP': application >> processor >> ; @param[in] EBP Pointer to the start of the Boot Firmware Volume >> +; @param[in] ESSet to LINEAR_SEL in TransitionFromReal16To32BitFlat > > What does this mean? Does it belong in this patch? (Knowing you, and > noticing that the next patch adds it to the x86 version of this code > as well, I am sure it probably does, but I just need you to explain it > to me :-)) See the STOSD instruction in the Intel SDM, or just on the web: http://x86.renejeschke.de/html/file_module_x86_id_306.html > Stores a byte, word, or doubleword from the AL, AX, or EAX register, > respectively, into the destination operand. The destination operand is > a memory location, the address of which is read from either the ES:EDI > or the ES:DI registers (depending on the address-size attribute of the > instruction, 32 or 16, respectively). The ES segment cannot be > overridden with a segment override prefix. It means that whatever we put in EDI, it will be relative to the segment "identified by" ES. (See the code comment near "mov edi": "base address, relative to ES".) Above I put "identified by" in quotes, because the definition of "identified by" depends on the mode the processor is in. (Instead of a botched attempt at writing up x86 segmentation (plus, optionally, paging) generally :) , I'll just leave these references here: * Intel SDM: 2.2 MODES OF OPERATION; Figure 2-3. Transitions Among the Processor's Operating Modes * https://en.wikipedia.org/wiki/Unreal_mode * https://en.wikipedia.org/wiki/X86_memory_segmentation#80286_protected_mode * https://en.wikipedia.org/wiki/X86_memory_segmentation#80386_protected_mode ) So using STOSD and ES:EDI as an example, here's a hugely inaccurate list of possible address calculations, dependent on processor mode: * real mode: physical_address = ES * 0x10 + DI E.g., A000:1234 means physical address A1234. * big real mode (segmentation
Re: [edk2] [PATCH 2/4] OvmfPkg/Sec/Ia32: seed the temporary RAM with PcdInitValueInTempStack
On 10 November 2017 at 15:49, Laszlo Ersekwrote: > This allows the PEI core to report the maximum temporary SEC/PEI stack > usage on the DEBUG_INFO level, in the PeiCheckAndSwitchStack() function > [MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c]: > > * Normal boot: > >> Temp Stack : BaseAddress=0x814000 Length=0x4000 >> Temp Heap : BaseAddress=0x81 Length=0x4000 >> Total temporary memory:32768 bytes. >> temporary memory stack ever used: 3664 bytes. < >> temporary memory heap used for HobList: 5904 bytes. >> temporary memory heap occupied by memory pages: 0 bytes. > > * S3 resume (with PEI decompression / SMM): > >> Temp Stack : BaseAddress=0x814000 Length=0x4000 >> Temp Heap : BaseAddress=0x81 Length=0x4000 >> Total temporary memory:32768 bytes. >> temporary memory stack ever used: 3428 bytes. < >> temporary memory heap used for HobList: 4816 bytes. >> temporary memory heap occupied by memory pages: 0 bytes. > > I unit-tested this change by transitorily adding an infinite loop right > after the "rep stosd", and dumping the guest's temp SEC/PEI RAM (32KB > currently) while the guest was stuck in the loop. The dump includes one > dword from before and after the temp SEC/PEI RAM: > >> $ virsh qemu-monitor-command GUEST_NAME --hmp 'xp /8194wx 0x80FFFC' >> >> 0080fffc: 0x 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 >> 0081000c: 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 >> ... >> 00817fec: 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 >> 00817ffc: 0x5aa55aa5 0x > > Cc: Ard Biesheuvel > Cc: Jordan Justen > Cc: Ruiyu Ni > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=747 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Laszlo Ersek > --- > OvmfPkg/Sec/SecMain.inf| 1 + > OvmfPkg/Sec/Ia32/SecEntry.nasm | 13 + > 2 files changed, 14 insertions(+) > > diff --git a/OvmfPkg/Sec/SecMain.inf b/OvmfPkg/Sec/SecMain.inf > index 711b59530907..6051cb3c6c4c 100644 > --- a/OvmfPkg/Sec/SecMain.inf > +++ b/OvmfPkg/Sec/SecMain.inf > @@ -71,6 +71,7 @@ [Pcd] >gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress >gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize >gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd > + gEfiMdeModulePkgTokenSpaceGuid.PcdInitValueInTempStack > > [FeaturePcd] >gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire > diff --git a/OvmfPkg/Sec/Ia32/SecEntry.nasm b/OvmfPkg/Sec/Ia32/SecEntry.nasm > index 54d074e621f6..1d426fafa888 100644 > --- a/OvmfPkg/Sec/Ia32/SecEntry.nasm > +++ b/OvmfPkg/Sec/Ia32/SecEntry.nasm > @@ -29,6 +29,7 @@ extern ASM_PFX(SecCoreStartupWithStack) > ; @param[in] EAX Initial value of the EAX register (BIST: Built-in Self > Test) > ; @param[in] DI'BP': boot-strap processor, or 'AP': application > processor > ; @param[in] EBP Pointer to the start of the Boot Firmware Volume > +; @param[in] ESSet to LINEAR_SEL in TransitionFromReal16To32BitFlat What does this mean? Does it belong in this patch? (Knowing you, and noticing that the next patch adds it to the x86 version of this code as well, I am sure it probably does, but I just need you to explain it to me :-)) > ; > ; @return None This routine does not return > ; > @@ -44,6 +45,18 @@ ASM_PFX(_ModuleEntryPoint): > mov esp, ebx > nop > > +; > +; Fill the temporary RAM with the initial stack value. > +; The loop below will seed the heap as well, but that's harmless. > +; > +mov eax, FixedPcdGet32 (PcdInitValueInTempStack) ; dword to store > +mov edi, FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) ; base address, > + ; relative to ES > +mov ecx, FixedPcdGet32 (PcdOvmfSecPeiTempRamSize) ; byte count > +shr ecx, 2; dword count > +cld ; store from base > up > +rep stosd > + > ; > ; Setup parameters and call SecCoreStartupWithStack > ; [esp] return address for call > -- > 2.14.1.3.gb7cf6e02401b > > ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 4/4] OvmfPkg: restore temporary SEC/PEI RAM size to 64KB
(1) In the PEI phase, the PCD database is maintained in a GUID HOB. In OVMF, we load the PCD PEIM before any other PEIMs (using APRIORI PEI), so that all other PEIMs can use dynamic PCDs. Consequently, - the PCD GUID HOB is initially allocated from the temporary SEC/PEI heap, - whenever we introduce a dynamic PCD to a PEIM built into OVMF such that the PCD is new to OVMF's whole PEI phase, the PCD GUID HOB (and its temporary heap footprint) grow. I've noticed that, if we add just one more dynamic PCD to the PEI phase, then in the X64 build, - we get very close to the half of the temporary heap (i.e., 8192 bytes), - obscure PEI phase hangs or DXE core initialization failures (ASSERTs) occur. The symptoms vary between the FD_SIZE_2MB and FD_SIZE_4MB builds of X64 OVMF. (2) I've found that commit 2bbd7e2fbd4b ("UefiCpuPkg/MtrrLib: Update algorithm to calculate optimal settings", 2017-09-27) introduced a large (16KB) stack allocation: > The patch changes existing MtrrSetMemoryAttributeInMtrrSettings() and > MtrrSetMemoryAttribute() to use the 4-page stack buffer for calculation. > ... > +#define SCRATCH_BUFFER_SIZE (4 * SIZE_4KB) > ... > @@ -2207,17 +2462,66 @@ MtrrSetMemoryAttributeInMtrrSettings ( > ... > + UINT8 Scratch[SCRATCH_BUFFER_SIZE]; (3) OVMF's temp SEC/PEI RAM size has been 32KB ever since commit 7cb6b0e06809 ("OvmfPkg: Move SEC/PEI Temporary RAM from 0x7 to 0x81", 2014-01-21) Of that, the upper 16KB half is stack (growing down), and the lower 16KB half is heap. Thus, OvmfPkg/PlatformPei's calls to "UefiCpuPkg/Library/MtrrLib", in QemuInitializeRam(), cause the Scratch array to overflow the entire stack (heading towards lower addresses), and corrupt the heap below the stack. It turns out that the total stack demand is about 24KB, so the overflow is able to corrupt the upper 8KB of the heap. If that part of the heap is actually used (for example because we grow the PCD GUID HOB sufficiently), mayhem ensues. (4) Right after commit 7cb6b0e06809 (see above), there would be no room left above the 32KB temp SEC/PEI RAM. However, given more recent commits 45d870815156 ("OvmfPkg/PlatformPei: rebase and resize the permanent PEI memory for S3", 2016-07-13) 6b04cca4d697 ("OvmfPkg: remove PcdS3AcpiReservedMemoryBase, PcdS3AcpiReservedMemorySize", 2016-07-12) we can now restore the temp SEC/PEI RAM size to the original (pre-7cb6b0e06809) 64KB. This will allow for a 32KB temp SEC/PEI stack, which accommodates the ~24KB demand mentioned in (3). (Prior patches in this series will let us monitor the stack usage in the future.) Cc: Ard BiesheuvelCc: Jordan Justen Cc: Ruiyu Ni Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=747 Ref: a49cc089-12ae-a887-a4d6-4dc509233a74@redhat.com">http://mid.mail-archive.com/a49cc089-12ae-a887-a4d6-4dc509233a74@redhat.com Ref: 03e369bb-77c4-0134-258f-bdae62cbc8c5@redhat.com">http://mid.mail-archive.com/03e369bb-77c4-0134-258f-bdae62cbc8c5@redhat.com Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek --- OvmfPkg/OvmfPkgIa32.fdf| 2 +- OvmfPkg/OvmfPkgIa32X64.fdf | 2 +- OvmfPkg/OvmfPkgX64.fdf | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/OvmfPkg/OvmfPkgIa32.fdf b/OvmfPkg/OvmfPkgIa32.fdf index 751522411857..06a439f8cba5 100644 --- a/OvmfPkg/OvmfPkgIa32.fdf +++ b/OvmfPkg/OvmfPkgIa32.fdf @@ -82,7 +82,7 @@ [FD.MEMFD] 0x007000|0x001000 gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize -0x01|0x008000 +0x01|0x01 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize 0x02|0x0E diff --git a/OvmfPkg/OvmfPkgIa32X64.fdf b/OvmfPkg/OvmfPkgIa32X64.fdf index f1a2044fb716..ced4c5639f39 100644 --- a/OvmfPkg/OvmfPkgIa32X64.fdf +++ b/OvmfPkg/OvmfPkgIa32X64.fdf @@ -82,7 +82,7 @@ [FD.MEMFD] 0x007000|0x001000 gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize -0x01|0x008000 +0x01|0x01 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize 0x02|0x0E diff --git a/OvmfPkg/OvmfPkgX64.fdf b/OvmfPkg/OvmfPkgX64.fdf index 32000a3b934c..62dd58f6e47a 100644 --- a/OvmfPkg/OvmfPkgX64.fdf +++ b/OvmfPkg/OvmfPkgX64.fdf @@ -82,7 +82,7 @@ [FD.MEMFD] 0x007000|0x001000 gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize -0x01|0x008000 +0x01|0x01
[edk2] [PATCH 3/4] OvmfPkg/Sec/X64: seed the temporary RAM with PcdInitValueInTempStack
This allows the PEI core to report the maximum temporary SEC/PEI stack usage on the DEBUG_INFO level, in the PeiCheckAndSwitchStack() function [MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c]: * Normal boot: > Temp Stack : BaseAddress=0x814000 Length=0x4000 > Temp Heap : BaseAddress=0x81 Length=0x4000 > Total temporary memory:32768 bytes. > temporary memory stack ever used: 5080 bytes. < > temporary memory heap used for HobList: 8080 bytes. > temporary memory heap occupied by memory pages: 0 bytes. * S3 resume (no SMM / PEI decompression) > Temp Stack : BaseAddress=0x814000 Length=0x4000 > Temp Heap : BaseAddress=0x81 Length=0x4000 > Total temporary memory:32768 bytes. > temporary memory stack ever used: 5048 bytes. < > temporary memory heap used for HobList: 7112 bytes. > temporary memory heap occupied by memory pages: 0 bytes. I unit-tested this change by transitorily adding an infinite loop right after the "rep stosq", and dumping the guest's temp SEC/PEI RAM (32KB currently) while the guest was stuck in the loop. The dump includes one dword from before and after the temp SEC/PEI RAM: > $ virsh qemu-monitor-command GUEST_NAME --hmp 'xp /8194wx 0x80FFFC' > > 0080fffc: 0x 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 > 0081000c: 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 > ... > 00817fec: 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 > 00817ffc: 0x5aa55aa5 0x Cc: Ard BiesheuvelCc: Jordan Justen Cc: Ruiyu Ni Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=747 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek --- OvmfPkg/Sec/X64/SecEntry.nasm | 15 +++ 1 file changed, 15 insertions(+) diff --git a/OvmfPkg/Sec/X64/SecEntry.nasm b/OvmfPkg/Sec/X64/SecEntry.nasm index f40427aa8e04..686008f41e15 100644 --- a/OvmfPkg/Sec/X64/SecEntry.nasm +++ b/OvmfPkg/Sec/X64/SecEntry.nasm @@ -30,6 +30,7 @@ extern ASM_PFX(SecCoreStartupWithStack) ; @param[in] RAX Initial value of the EAX register (BIST: Built-in Self Test) ; @param[in] DI'BP': boot-strap processor, or 'AP': application processor ; @param[in] RBP Pointer to the start of the Boot Firmware Volume +; @param[in] ESSet to LINEAR_SEL in TransitionFromReal16To32BitFlat ; ; @return None This routine does not return ; @@ -44,6 +45,20 @@ ASM_PFX(_ModuleEntryPoint): mov rsp, SEC_TOP_OF_STACK nop +; +; Fill the temporary RAM with the initial stack value. +; The loop below will seed the heap as well, but that's harmless. +; +mov rax, FixedPcdGet32 (PcdInitValueInTempStack) ; dword to store +shl rax, 32 +or rax, FixedPcdGet32 (PcdInitValueInTempStack) ; qword to store +mov rdi, FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) ; base address, + ; relative to ES +mov rcx, FixedPcdGet32 (PcdOvmfSecPeiTempRamSize) ; byte count +shr rcx, 3; qword count +cld ; store from base up +rep stosq + ; ; Setup parameters and call SecCoreStartupWithStack ; rcx: BootFirmwareVolumePtr -- 2.14.1.3.gb7cf6e02401b ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 2/4] OvmfPkg/Sec/Ia32: seed the temporary RAM with PcdInitValueInTempStack
This allows the PEI core to report the maximum temporary SEC/PEI stack usage on the DEBUG_INFO level, in the PeiCheckAndSwitchStack() function [MdeModulePkg/Core/Pei/Dispatcher/Dispatcher.c]: * Normal boot: > Temp Stack : BaseAddress=0x814000 Length=0x4000 > Temp Heap : BaseAddress=0x81 Length=0x4000 > Total temporary memory:32768 bytes. > temporary memory stack ever used: 3664 bytes. < > temporary memory heap used for HobList: 5904 bytes. > temporary memory heap occupied by memory pages: 0 bytes. * S3 resume (with PEI decompression / SMM): > Temp Stack : BaseAddress=0x814000 Length=0x4000 > Temp Heap : BaseAddress=0x81 Length=0x4000 > Total temporary memory:32768 bytes. > temporary memory stack ever used: 3428 bytes. < > temporary memory heap used for HobList: 4816 bytes. > temporary memory heap occupied by memory pages: 0 bytes. I unit-tested this change by transitorily adding an infinite loop right after the "rep stosd", and dumping the guest's temp SEC/PEI RAM (32KB currently) while the guest was stuck in the loop. The dump includes one dword from before and after the temp SEC/PEI RAM: > $ virsh qemu-monitor-command GUEST_NAME --hmp 'xp /8194wx 0x80FFFC' > > 0080fffc: 0x 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 > 0081000c: 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 > ... > 00817fec: 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 0x5aa55aa5 > 00817ffc: 0x5aa55aa5 0x Cc: Ard BiesheuvelCc: Jordan Justen Cc: Ruiyu Ni Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=747 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek --- OvmfPkg/Sec/SecMain.inf| 1 + OvmfPkg/Sec/Ia32/SecEntry.nasm | 13 + 2 files changed, 14 insertions(+) diff --git a/OvmfPkg/Sec/SecMain.inf b/OvmfPkg/Sec/SecMain.inf index 711b59530907..6051cb3c6c4c 100644 --- a/OvmfPkg/Sec/SecMain.inf +++ b/OvmfPkg/Sec/SecMain.inf @@ -71,6 +71,7 @@ [Pcd] gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd + gEfiMdeModulePkgTokenSpaceGuid.PcdInitValueInTempStack [FeaturePcd] gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire diff --git a/OvmfPkg/Sec/Ia32/SecEntry.nasm b/OvmfPkg/Sec/Ia32/SecEntry.nasm index 54d074e621f6..1d426fafa888 100644 --- a/OvmfPkg/Sec/Ia32/SecEntry.nasm +++ b/OvmfPkg/Sec/Ia32/SecEntry.nasm @@ -29,6 +29,7 @@ extern ASM_PFX(SecCoreStartupWithStack) ; @param[in] EAX Initial value of the EAX register (BIST: Built-in Self Test) ; @param[in] DI'BP': boot-strap processor, or 'AP': application processor ; @param[in] EBP Pointer to the start of the Boot Firmware Volume +; @param[in] ESSet to LINEAR_SEL in TransitionFromReal16To32BitFlat ; ; @return None This routine does not return ; @@ -44,6 +45,18 @@ ASM_PFX(_ModuleEntryPoint): mov esp, ebx nop +; +; Fill the temporary RAM with the initial stack value. +; The loop below will seed the heap as well, but that's harmless. +; +mov eax, FixedPcdGet32 (PcdInitValueInTempStack) ; dword to store +mov edi, FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) ; base address, + ; relative to ES +mov ecx, FixedPcdGet32 (PcdOvmfSecPeiTempRamSize) ; byte count +shr ecx, 2; dword count +cld ; store from base up +rep stosd + ; ; Setup parameters and call SecCoreStartupWithStack ; [esp] return address for call -- 2.14.1.3.gb7cf6e02401b ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 1/4] OvmfPkg/Sec/Ia32: free up EAX for other uses while setting up the stack
Currently EAX is used as an intermediary in setting ESP to SEC_TOP_OF_STACK, and in passing SEC_TOP_OF_STACK to SecCoreStartupWithStack() as the "TopOfCurrentStack" argument. In a later patch we'll use EAX differently, so replace it with EBX under the current use. Cc: Ard BiesheuvelCc: Jordan Justen Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek --- OvmfPkg/Sec/Ia32/SecEntry.nasm | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/OvmfPkg/Sec/Ia32/SecEntry.nasm b/OvmfPkg/Sec/Ia32/SecEntry.nasm index 7fee1c2b2e4f..54d074e621f6 100644 --- a/OvmfPkg/Sec/Ia32/SecEntry.nasm +++ b/OvmfPkg/Sec/Ia32/SecEntry.nasm @@ -40,8 +40,8 @@ ASM_PFX(_ModuleEntryPoint): ; %define SEC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + \ FixedPcdGet32 (PcdOvmfSecPeiTempRamSize)) -mov eax, SEC_TOP_OF_STACK -mov esp, eax +mov ebx, SEC_TOP_OF_STACK +mov esp, ebx nop ; @@ -50,7 +50,7 @@ ASM_PFX(_ModuleEntryPoint): ; [esp+4] BootFirmwareVolumePtr ; [esp+8] TopOfCurrentStack ; -pusheax +pushebx pushebp callASM_PFX(SecCoreStartupWithStack) -- 2.14.1.3.gb7cf6e02401b ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
Re: [edk2] [PATCH 3/4] UefiCpuPkg/MtrrLib: Update algorithm to calculate optimal settings
Hi Ray, On 11/10/17 01:52, Ni, Ruiyu wrote: > > >> -Original Message- >> From: Laszlo Ersek [mailto:ler...@redhat.com] >> Sent: Thursday, November 9, 2017 9:16 PM >> To: Ni, Ruiyu; Justen, Jordan L >> ; Jeff Fan >> Cc: Kinney, Michael D ; edk2-devel@lists.01.org; >> Yao, Jiewen ; Dong, Eric ; Ard >> Biesheuvel >> Subject: Re: [edk2] [PATCH 3/4] UefiCpuPkg/MtrrLib: Update algorithm to >> calculate optimal settings >> (1b) is an option we may or may not want to exercise in OVMF. I have the >> patches ready for enlarging the temp SEC/PEI RAM (and as part of that, the >> temp stack), which is one alternative. However, because OVMF's PEI phase runs >> from RAM (and not flash), the other alternative is just to add a >> sufficiently large >> static UINT8 array to PlatformPei, and pass that as scratch space to MtrrLib. >> Is my understanding correct that MtrrSetMemoryAttribute() is the only >> function >> that is affected? > > 1. yes. Only MtrrSetMemoryAttribute() call in OVMF is affected. >> (3) Is my understanding correct that >> MtrrSetMemoryAttributesInMtrrSettings() should be used like this: >> >> (3a) start with MtrrGetAllMtrrs() >> >> (3b) collect all *foreseeable* MtrrSetMemoryAttribute() calls into an >> array of MTRR_MEMORY_RANGE elements >> >> (3c) Perform a batch update on the output of (3a) by calling >> MtrrSetMemoryAttributesInMtrrSettings(). For this, the array from >> (3b), plus a caller-allocated scratch space, have to be passed in,. >> >> (3d) Finally, call MtrrSetAllMtrrs(). >> >> Is this correct? > > 2. yes. In summary, there are three ways to call this new API. The first way > is what > you described. The second way is a bit change to (3a), ZeroMem() is > called > instead of MtrrGetAllMtrrs() to initialize the MTRR. The third way is to > call > this new API using NULL MtrrSetting, which cause the API itself to > retrieve > the current MTRR settings from CPU, apply the new setting, write to CPU. > But the third way doesn't support batch setting. > >> >> I think we could use this. Jordan, which alternative do you prefer; larger >> stack >> and unchanged code in PlatformPei, or same stack and updated code in >> PlatformPei? >> >> >> (4) Ray: would it be possible to expose SCRATCH_BUFFER_SIZE (with a new >> name MTRR_SCRATCH_BUFFER_SIZE) in the library class header? I see the new >> RETURN_BUFFER_TOO_SMALL status codes, and I don't really want to deal with >> them. The library class header should provide clients with a size macro that >> *guarantees* that RETURN_BUFFER_TOO_SMALL will not occur. >> >> Practically speaking, I would use MTRR_SCRATCH_BUFFER_SIZE in the definition >> of the static UINT8 array in PlatformPei. (If Jordan prefers this >> alternative to the >> larger temp stack.) > > 3. Not quite correct. Because even when pass in the scratch buffer whose size > equal > to MTRR_SCRATCH_BUFFER_SIZE, the BUFFER_TOO_SMALL could be returned. > That's why the BUFFER_TOO_SMALL status is invented. It requires caller to > re-supply > the enough scratch buffer for calculation. > As such, I do not think exposing SCRATCH_BUFFER_SIZE helps. > When implementing the code, I tried to find out the maximum scratch > buffer size but > found that the maximum could be up to 256KB. I cannot use such large > stack because > as Jordan said, MSVC will inject some code results in unresolved symbol > in EDKII code. > And DxeIpl only allocates 128KB stack for whole DXE phase. Thank you very much for the explanation! I have an untested prototype for (1b), using a 16KB static array as MtrrLib scratch space, in OvmfPkg/PlatformPei. In the compressed FVMAIN_COMPACT volume, its size impact is 320 bytes only. (For illustration, I'm attaching this "proof of concept".) However, after some more thinking, I dislike this approach. First, I'd like to keep this added complexity out of PlatformPei, if possible. Second, a 16KB growth in PEIFV (current total size: 896 KB) just to preserve the "status quo" is not really nice; we could use that space for including executable code and related static data. Third, this scratch space cannot be used for any other purpose. A larger temp stack is generally available to other functions in PlatformPei, and to all other PEIMs as well. In particular, if OVMF included a PEIM in the future that used the traditional MtrrSetMemoryAttribute() API, then PlatformPei's dedicated scratch space could not be shared by that PEIM. So, I'll go ahead and post the variant that grows the temp SEC/PEI RAM for OVMF. Thanks! Laszlo From 796092bd81390a7f398ca923c509838d36d4b97d Mon Sep 17 00:00:00 2001 From: Laszlo Ersek Date: Fri, 10 Nov 2017 14:56:09 +0100 Subject: [PATCH] OvmfPkg/PlatformPei: manage MtrrLib scratch
[edk2] [PATCH edk2-platforms v4 29/34] Silicon/SynQuacer: implement 'clear NVRAM' feature using a DIP switch
Ordinary computers typically have a physical switch or jumper on the board that allows non-volatile settings to be cleared. Let's implement the same using DIP switch #1 on block #3, and clear the EFI variable store if it is set to ON at boot time. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel--- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 4 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 4 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 1 + Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c | 25 +++- Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf | 6 + Silicon/Socionext/SynQuacer/SynQuacer.dec | 2 ++ 6 files changed, 41 insertions(+), 1 deletion(-) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index 10d070773cdc..af978db2c034 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -381,6 +381,9 @@ [PcdsFixedAtBuild.common] gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4f524e4c # LNRO gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|1 + # set DIP switch DSW3-PIN1 to clear the varstore + gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0 + [PcdsPatchableInModule] gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 @@ -418,6 +421,7 @@ [Components.common] MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf MdeModulePkg/Universal/Variable/Pei/VariablePei.inf MdeModulePkg/Universal/CapsulePei/CapsulePei.inf + Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index 4630d78bce93..4034bcfe82c5 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -369,6 +369,9 @@ [PcdsFixedAtBuild.common] gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0842 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x0001 + # set DIP switch DSW3-PIN1 to clear the varstore + gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0 + [PcdsPatchableInModule] gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 @@ -406,6 +409,7 @@ [Components.common] MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf MdeModulePkg/Universal/Variable/Pei/VariablePei.inf MdeModulePkg/Universal/CapsulePei/CapsulePei.inf + Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf index 365085c8f243..4577bd316a1f 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf @@ -248,6 +248,7 @@ [FV.FVMAIN_COMPACT] INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf + INF Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf INF RuleOverride = FMP_IMAGE_DESC Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c index 358dd5a91f08..bd8ee7a368f5 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c @@ -21,6 +21,7 @@ #include #include #include +#include #include STATIC @@ -103,10 +104,32 @@ PlatformPeim ( VOID ) { - EFI_STATUS Status; + EMBEDDED_GPIO_PPI *Gpio; + EFI_STATUS Status; + UINTN Value; ASSERT (mDramInfo->NumRegions > 0); + Status = PeiServicesLocatePpi (, 0, NULL, + (VOID **)); + ASSERT_EFI_ERROR
[edk2] [PATCH edk2-platforms v4 34/34] Platform/SynQuacerEvalBoard: add eMMC driver stack
Add the drivers required to use the onboard eMMC on the SynQuacer Evaluation Board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel--- NOTE: this depends on an upstream EDK2 change that is currently still under discussion Platform/Socionext/DeveloperBox/DeveloperBox.dsc| 1 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc| 8 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf| 7 + Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 204 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 12 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 37 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 5 + 7 files changed, 266 insertions(+), 8 deletions(-) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index cd4eb79b35bf..1a09f727b31f 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -177,6 +177,7 @@ [LibraryClasses.common.DXE_DRIVER] # PciSegmentLib|Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/SynQuacerPciSegmentLib.inf PciHostBridgeLib|Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf [LibraryClasses.common.UEFI_APPLICATION] PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index 4034bcfe82c5..20b719794d06 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -176,6 +176,7 @@ [LibraryClasses.common.DXE_DRIVER] # PciSegmentLib|Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/SynQuacerPciSegmentLib.inf PciHostBridgeLib|Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf [LibraryClasses.common.UEFI_APPLICATION] PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf @@ -529,6 +530,13 @@ [Components.common] MdeModulePkg/Universal/EbcDxe/EbcDxe.inf # + # eMMC support + # + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf + MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf + + # # AHCI Support # MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf index 4577bd316a1f..1599f8953008 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf @@ -149,6 +149,13 @@ [FV.FvMain] INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf # + # eMMC support + # + INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + INF MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf + INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf + + # # AHCI Support # INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c new file mode 100644 index ..4c7713d78fa3 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c @@ -0,0 +1,204 @@ + /** @file + SynQuacer DXE platform driver - eMMC support + + Copyright (c) 2017, Linaro, Ltd. All rights reserved. + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#include "PlatformDxe.h" + +// F_SDH30 extended Controller registers +#define F_SDH30_AHB_CONFIG0x100 +#define F_SDH30_AHB_BIGEDBIT6 +#define F_SDH30_BUSLOCK_DMA BIT5 +#define F_SDH30_BUSLOCK_EN BIT4 +#define F_SDH30_SIN BIT3 +#define F_SDH30_AHB_INCR_16 BIT2 +#define F_SDH30_AHB_INCR_8 BIT1 +#define F_SDH30_AHB_INCR_4 BIT0 + +#define F_SDH30_TUNING_SETTING0x108 +#define F_SDH30_CMD_CHK_DIS BIT16 + +#define F_SDH30_IO_CONTROL2 0x114
[edk2] [PATCH edk2-platforms v4 33/34] Platform/DeveloperBox: add description of power button to DT
Add the power button as a gpio-keys KEY_POWER button, and mark it as a wakeup source so it can be used under the OS both as a 'sleep' and as a 'wake' button. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel--- Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | 14 ++ 1 file changed, 14 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts index 6ae7d5f300b6..d2cd7ef90e6f 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts @@ -15,9 +15,23 @@ #include "SynQuacer.dtsi" +#define KEY_POWER 116 + / { model = "Socionext Developer Box"; compatible = "socionext,developer-box", "socionext,synquacer"; + +gpio-keys { +compatible = "gpio-keys"; +interrupt-parent = <>; + +power { +label = "Power Button"; +linux,code = ; +interrupts = ; +wakeup-source; +}; +}; }; { -- 2.11.0 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH edk2-platforms v4 31/34] Silicon/Socionext: implement I2C master protocol for SynQuacer I2C
Add a driver that produces the I2C master protocol on top of the I2C controllers that are implemented in the SynQuacer Socionext SoC. Note that this supports two modes simultaneously: I2C controllers that are only usable at boot time, and usable via the I2C protocol stack, and I2C controllers that are dedicated for the RTC or other runtime components. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel--- Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/ComponentName.c | 185 ++ Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/DriverBinding.c | 238 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c | 586 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.h | 162 ++ Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf | 59 ++ Silicon/Socionext/SynQuacer/SynQuacer.dec | 5 + 6 files changed, 1235 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/ComponentName.c b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/ComponentName.c new file mode 100644 index ..8d7aa417505b --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/ComponentName.c @@ -0,0 +1,185 @@ +/** @file + + Copyright (c) 2017, Linaro Ltd. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "SynQuacerI2cDxe.h" + +STATIC EFI_UNICODE_STRING_TABLE mSynQuacerI2cDriverNameTable[] = { + { +"en", +(CHAR16 *)L"Socionext SynQuacer I2C Driver" + }, + { } +}; + +STATIC EFI_UNICODE_STRING_TABLE mSynQuacerI2cControllerNameTable[] = { + { +"en", +(CHAR16 *)L"Socionext SynQuacer I2C Controller" + }, + { } +}; + +/** + Retrieves a Unicode string that is the user readable name of the driver. + + This function retrieves the user readable name of a driver in the form of a + Unicode string. If the driver specified by This has a user readable name in + the language specified by Language, then a pointer to the driver name is + returned in DriverName, and EFI_SUCCESS is returned. If the driver specified + by This does not support the language specified by Language, + then EFI_UNSUPPORTED is returned. + + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or +EFI_COMPONENT_NAME_PROTOCOL instance. + + @param Language[in] A pointer to a Null-terminated ASCII string +array indicating the language. This is the +language of the driver name that the caller is +requesting, and it must match one of the +languages specified in SupportedLanguages. The +number of languages supported by a driver is up +to the driver writer. Language is specified +in RFC 4646 or ISO 639-2 language code format. + + @param DriverName[out] A pointer to the Unicode string to return. +This Unicode string is the name of the +driver specified by This in the language +specified by Language. + + @retval EFI_SUCCESS The Unicode string for the Driver specified by +This and the language specified by Language was +returned in DriverName. + + @retval EFI_INVALID_PARAMETER Language is NULL. + + @retval EFI_INVALID_PARAMETER DriverName is NULL. + + @retval EFI_UNSUPPORTED The driver specified by This does not support +the language specified by Language. + +**/ +STATIC +EFI_STATUS +EFIAPI +SynQuacerI2cGetDriverName ( + IN EFI_COMPONENT_NAME2_PROTOCOL *This, + IN CHAR8 *Language, + OUT CHAR16**DriverName + ) +{ + return LookupUnicodeString2 (Language, + This->SupportedLanguages, + mSynQuacerI2cDriverNameTable, + DriverName, + FALSE); +} + +/** + Retrieves a Unicode string that is the user readable name of the controller + that is being managed by a driver. + + This function retrieves the user readable name of the controller specified by + ControllerHandle and ChildHandle in the form of a Unicode string. If the + driver
[edk2] [PATCH edk2-platforms v4 28/34] Silicon/SynQuacer: implement PEIM that exposes GPIO PPI
In order to be able to sample the state of the DIP switches at early boot on the Developer Box platform, implement the GPIO PPI based on the GPIO block that is implemented in the SynQuacer SoC. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel--- Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.c | 203 Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf | 47 + 2 files changed, 250 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.c b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.c new file mode 100644 index ..24d08b4e5899 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.c @@ -0,0 +1,203 @@ +/** @file + + Copyright (c) 2017, Linaro, Ltd. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include + +#define PDR(x)(SYNQUACER_GPIO_BASE + 4 * (GPIO_PIN (x) >> 3)) +#define DDR(x)(SYNQUACER_GPIO_BASE + 0x10 + 4 * (GPIO_PIN (x) >> 3)) +#define PFR(x)(SYNQUACER_GPIO_BASE + 0x20 + 4 * (GPIO_PIN (x) >> 3)) + +#define GPIO_BIT(x) (1U << (GPIO_PIN (x) % 8)) + +STATIC CONST UINTN mGpioPinCount = 32; + +/** + + Gets the state of a GPIO pin + + @param This Pointer to protocol + @param Gpio Which pin to read + @param Value State of the pin + + @retval EFI_SUCCESS GPIO state returned in Value + @retval EFI_INVALID_PARAMETER Value is NULL + @retval EFI_NOT_FOUND Pin does not exit + +**/ +STATIC +EFI_STATUS +EFIAPI +GpioGet ( + IN EMBEDDED_GPIO_PPI *This, + IN EMBEDDED_GPIO_PIN Gpio, + OUT UINTN *Value + ) +{ + if (Value == NULL) { +return EFI_INVALID_PARAMETER; + } + if (GPIO_PORT (Gpio) > 0 || GPIO_PIN (Gpio) >= mGpioPinCount) { +return EFI_NOT_FOUND; + } + + *Value = ((MmioRead32 (PDR (GPIO_PIN (Gpio))) & GPIO_BIT (Gpio)) != 0); + + return EFI_SUCCESS; +} + +/** + + Sets the state of a GPIO pin + + @param This Pointer to protocol + @param Gpio Which pin to modify + @param Mode Mode to set + + @retval EFI_SUCCESS GPIO set as requested + @retval EFI_INVALID_PARAMETER Invalid mode + @retval EFI_NOT_FOUND Pin does not exit + +**/ +STATIC +EFI_STATUS +EFIAPI +GpioSet ( + IN EMBEDDED_GPIO_PPI *This, + IN EMBEDDED_GPIO_PIN Gpio, + IN EMBEDDED_GPIO_MODE Mode + ) +{ + if (GPIO_PORT (Gpio) > 0 || GPIO_PIN (Gpio) >= mGpioPinCount) { +return EFI_NOT_FOUND; + } + + switch (Mode) { + case GPIO_MODE_INPUT: +MmioAnd32 (DDR (GPIO_PIN (Gpio)), ~GPIO_BIT (Gpio)); +break; + + case GPIO_MODE_OUTPUT_0: +MmioOr32 (DDR (GPIO_PIN (Gpio)), GPIO_BIT (Gpio)); +MmioAnd32 (PDR (GPIO_PIN (Gpio)), ~GPIO_BIT (Gpio)); +break; + + case GPIO_MODE_OUTPUT_1: +MmioOr32 (DDR (GPIO_PIN (Gpio)), GPIO_BIT (Gpio)); +MmioOr32 (PDR (GPIO_PIN (Gpio)), GPIO_BIT (Gpio)); +break; + + default: +return EFI_INVALID_PARAMETER; + } + return EFI_SUCCESS; +} + + +/** + + Gets the mode (function) of a GPIO pin + + @param This Pointer to protocol + @param Gpio Which pin + @param Mode Pointer to output mode value + + @retval EFI_SUCCESS Mode value retrieved + @retval EFI_INVALID_PARAMETER Mode is NULL + @retval EFI_NOT_FOUND Pin does not exit + +**/ +STATIC +EFI_STATUS +EFIAPI +GpioGetMode ( + IN EMBEDDED_GPIO_PPI *This, + IN EMBEDDED_GPIO_PIN Gpio, + OUT EMBEDDED_GPIO_MODE*Mode + ) +{ + if (Mode == NULL) { +return EFI_INVALID_PARAMETER; + } + if (GPIO_PORT (Gpio) > 0 || GPIO_PIN (Gpio) >= mGpioPinCount) { +return EFI_NOT_FOUND; + } + + if (!(MmioRead32 (DDR (GPIO_PIN (Gpio))) & GPIO_BIT (Gpio))) { +*Mode = GPIO_MODE_INPUT; + } else if (!(MmioRead32 (PDR (GPIO_PIN (Gpio))) & GPIO_BIT (Gpio))) { +*Mode = GPIO_MODE_OUTPUT_0; + } else { +*Mode = GPIO_MODE_OUTPUT_1; + } + return EFI_SUCCESS; +} + + +/** + + Sets the pull-up / pull-down resistor of a GPIO pin + + @param This Pointer to PPI + @param Gpio Port/pin index + @param Pull The pullup/pulldown mode to set + + @retval EFI_SUCCESS Mode was set + @retval EFI_NOT_FOUND Pin does not exist + @retval EFI_UNSUPPORTED
[edk2] [PATCH edk2-platforms v4 27/34] Silicon/SynQuacerMemoryInitPeiLib: ignore capsules when clearing NVRAM
In preparation of adding support for setting a DIP switch to clear the EFI variable store, update the early capsule handling logic to take the boot mode into account. This is necessary for two reasons: - we override the boot mode when a capsule is detected, - the capsule detection itself involves reading a EFI variable, which we shouldn't be doing if the varstore may be in a bad state. So factor out the initial capsule check (to keep the code understandable) and only perform it if we are not booting in 'clear NVRAM' mode. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel--- Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 68 +--- 1 file changed, 45 insertions(+), 23 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c index b44c58d61062..63c441872da7 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c @@ -170,6 +170,44 @@ DeclareDram ( return EFI_SUCCESS; } +STATIC +BOOLEAN +CheckCapsule ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CAPSULE_PPI *Capsule, + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, + OUT VOID **CapsuleBuffer, + OUT UINTN *CapsuleBufferLength + ) +{ + EFI_STATUSStatus; + + Status = Capsule->CheckCapsuleUpdate (PeiServices); + if (!EFI_ERROR (Status)) { + +// +// Coalesce the capsule into unused memory. CreateState() below will copy +// it to a properly allocated buffer. +// +*CapsuleBuffer = (VOID *)PcdGet64 (PcdSystemMemoryBase); +*CapsuleBufferLength = UefiMemoryBase - PcdGet64 (PcdSystemMemoryBase); + +PeiServicesSetBootMode (BOOT_ON_FLASH_UPDATE); + +Status = Capsule->Coalesce (PeiServices, CapsuleBuffer, +CapsuleBufferLength); +if (!EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "%a: Coalesced capsule @ %p (0x%lx)\n", +__FUNCTION__, *CapsuleBuffer, *CapsuleBufferLength)); + return TRUE; +} else { + DEBUG ((DEBUG_WARN, "%a: failed to coalesce() capsule (Status == %r)\n", +__FUNCTION__, Status)); +} + } + return FALSE; +} + EFI_STATUS EFIAPI MemoryPeim ( @@ -184,6 +222,7 @@ MemoryPeim ( VOID *CapsuleBuffer; UINTN CapsuleBufferLength; BOOLEAN HaveCapsule; + EFI_BOOT_MODE BootMode; Status = DeclareDram (); ASSERT_EFI_ERROR (Status); @@ -199,31 +238,14 @@ MemoryPeim ( ASSERT_EFI_ERROR (Status); // - // Check for persistent capsules + // Check for persistent capsules, unless we are booting with default + // settings. // HaveCapsule = FALSE; - Status = Capsule->CheckCapsuleUpdate (PeiServices); - if (!EFI_ERROR (Status)) { - -// -// Coalesce the capsule into unused memory. CreateState() below will copy -// it to a properly allocated buffer. -// -CapsuleBuffer = (VOID *)PcdGet64 (PcdSystemMemoryBase); -CapsuleBufferLength = UefiMemoryBase - PcdGet64 (PcdSystemMemoryBase); - -PeiServicesSetBootMode (BOOT_ON_FLASH_UPDATE); - -Status = Capsule->Coalesce (PeiServices, , - ); -if (!EFI_ERROR (Status)) { - DEBUG ((DEBUG_INFO, "%a: Coalesced capsule @ %p (0x%lx)\n", -__FUNCTION__, CapsuleBuffer, CapsuleBufferLength)); - HaveCapsule = TRUE; -} else { - DEBUG ((DEBUG_WARN, "%a: failed to coalesce() capsule (Status == %r)\n", -__FUNCTION__, Status)); -} + Status = PeiServicesGetBootMode (); + if (!EFI_ERROR (Status) && BootMode != BOOT_WITH_DEFAULT_SETTINGS) { +HaveCapsule = CheckCapsule (PeiServices, Capsule, UefiMemoryBase, +, ); } Status = ArmConfigureMmu (VirtualMemoryTable, NULL, NULL); -- 2.11.0 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH edk2-platforms v4 26/34] Silicon/SynQuacer: add DT description of the SDHCI controller
Describe the SynQuacer SoC's eMMC controller in DT so the OS can attach to it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel--- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 26 1 file changed, 26 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index e72db377bc39..cf06acc75297 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -532,4 +532,30 @@ #interrupt-cells = <3>; socionext,spi-base = <112>; }; + +clk_alw_b_0: bclk200 { +compatible = "fixed-clock"; +#clock-cells = <0>; +clock-frequency = <2>; +clock-output-names = "sd_bclk"; +}; + +clk_alw_c_0: sd4clk800 { +compatible = "fixed-clock"; +#clock-cells = <0>; +clock-frequency = <8>; +clock-output-names = "sd_sd4clk"; +}; + +sdhci@5230 { +compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0"; +reg = <0 0x5230 0x0 0x1000>; +interrupts = , + ; +bus-width = <8>; +cap-mmc-highspeed; +fujitsu,cmd-dat-delay-select; +clocks = <_alw_c_0 _alw_b_0>; +clock-names = "core", "iface"; +}; }; -- 2.11.0 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH edk2-platforms v4 24/34] Silicon/SynQuacer: add description of GPIO block to device tree
Add a description of the SoCs GPIO controller as well as a description of DIP switch block #3, which is wired to GPIOs 0 - 7, both on the evaluation board as well as the Developer Box. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- v4: replace pin 'hogs' with descriptive names of all the pins, including PD8 which has been repurposed as the power button on v0.2 of the schematics Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | 11 +++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 12 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 11 +++ 3 files changed, 34 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts index 9e0acd593311..6ae7d5f300b6 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts @@ -19,3 +19,14 @@ model = "Socionext Developer Box"; compatible = "socionext,developer-box", "socionext,synquacer"; }; + + { +gpio-line-names = "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3","DSW3-PIN4", + "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7","DSW3-PIN8", + "PSIN#", "PWROFF#","GPIO-A", "GPIO-B", + "GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT", + "PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F", + "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J", + "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27", + "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31"; +}; diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index f89e722219ad..966952b9a224 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -21,6 +21,9 @@ #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 +#define GPIO_ACTIVE_HIGH0 +#define GPIO_ACTIVE_LOW 1 + / { #address-cells = <2>; #size-cells = <2>; @@ -511,4 +514,13 @@ msi-map = <0x0 0x1 0x7f00>; dma-coherent; }; + +gpio: gpio@5100 { +compatible = "socionext,synquacer-gpio", "fujitsu,mb86s70-gpio"; +reg = <0x0 0x5100 0x0 0x100>; +gpio-controller; +#gpio-cells = <2>; +clocks = <_apb>; +base = <0>; +}; }; diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts index cda72fdf2f99..7de7db182b27 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts @@ -19,3 +19,14 @@ model = "SynQuacer Evaluation Board"; compatible = "socionext,synquacer-eval-board", "socionext,synquacer"; }; + + { +gpio-line-names = "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3","DSW3-PIN4", + "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7","DSW3-PIN8", + "PEC-PD8","PEC-PD9","PEC-PD10", "PEC-PD11", + "NC", "NC", "PCIE1EXTINT", "PCIE0EXTINT", + "PHY_P2_2", "PHY_P1_2", "NC", "NC", + "NC", "NC", "NC", "NC", + "NC", "NC", "PEC-PD26", "PEC-PD27", + "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31"; +}; -- 2.11.0 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH edk2-platforms v4 22/34] Platform/Socionext: add support for Socionext Developer Box rev 0.1
This adds support for the first working sample of the MZSC2AM board, revision 0.1 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 613 Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 455 +++ Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 46 ++ Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 68 +++ Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc | 80 +++ Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 25 + Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | 21 + Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.inf | 33 ++ 8 files changed, 1341 insertions(+) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc new file mode 100644 index ..676a9e71fa8a --- /dev/null +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -0,0 +1,613 @@ +# +# Copyright (c) 2013-2014, ARM Limited. All rights reserved. +# Copyright (c) 2017, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + + +# +# Defines Section - statements that will be processed to create a Makefile. +# + +[Defines] + PLATFORM_NAME = DeveloperBox + PLATFORM_GUID = d32612b4-e1c5-431f-823a-fa1aa7b9deb7 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001B + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES= AARCH64|ARM + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Socionext/DeveloperBox/DeveloperBox.fdf + +[BuildOptions] + RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=0 + +[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION] + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000 + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x1 + +[LibraryClasses.common] + ArmPlatformLib|Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacerLib.inf + ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + +!if $(TARGET) == RELEASE + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + + BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf + + # Networking Requirements + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf + + # ARM Architectural Libraries + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf +
[edk2] [PATCH edk2-platforms v4 25/34] Silicon/SynQuacer: add description of EXIU to the device tree
Add a DT node for the external interrupt unit (EXIU), which handles interrupts from GPIO lines. We need OS support for this for things like PHY interrupts and a 'wake' button. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 9 + 1 file changed, 9 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 966952b9a224..e72db377bc39 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -523,4 +523,13 @@ clocks = <_apb>; base = <0>; }; + +exiu: interrupt-controller@510c { +compatible = "socionext,synquacer-exiu"; +reg = <0x0 0x510c 0x0 0x20>; +interrupt-controller; +interrupt-parent = <>; +#interrupt-cells = <3>; +socionext,spi-base = <112>; +}; }; -- 2.11.0 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH edk2-platforms v4 21/34] Silicon/SynQuacerPciHostBridgeLib: add workaround to support 32-bit only cards
Implement workaround suggested by Socionext to get legacy endpoints with 32-bit BARs working. This fixes the issue on Developer Box with the onboard ASM1061 SATA controller. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index b5bfea8e0e75..1bbef5b6cf98 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -32,10 +32,13 @@ #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5 +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_THBIT12 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31 #define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODEBIT28 +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT0xF +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT0xFF #define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C #define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910 @@ -297,8 +300,9 @@ PciInitController ( RootBridge->Mem.Base, RootBridge->Mem.Base, RootBridge->Mem.Limit - RootBridge->Mem.Base + 1, -IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM, -0); +IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | +IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH, +IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT); // Region 1: Type 0 config space ConfigureWindow (DbiBase, 1, -- 2.11.0 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH edk2-platforms v4 23/34] Platform/DeveloperBox: add ConsolePrefDxe driver
In order to improve the 'out of the box' experience when booting this system with a monitor and keyboard attached, include the serial console preference driver that prevents the installer GUI to only appear on the serial port in this case. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 8 Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 5 + 2 files changed, 13 insertions(+) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index 676a9e71fa8a..10d070773cdc 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -600,6 +600,14 @@ [Components.common] } # + # Console preference selection + # + EmbeddedPkg/Drivers/ConsolePrefDxe/ConsolePrefDxe.inf { + + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + } + + # # DT support # Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.inf diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf index 83e8a01cfb18..6cc523fac4f3 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf @@ -210,6 +210,11 @@ [FV.FvMain] INF Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf # + # Console preference selection + # + INF EmbeddedPkg/Drivers/ConsolePrefDxe/ConsolePrefDxe.inf + + # # DT support # INF RuleOverride = DTB Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.inf -- 2.11.0 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH edk2-platforms v4 17/34] SynQuacer/SynQuacerMemoryInitPeiLib: add capsule support
Add support for dealing with capsules left in memory by the OS before reboot. This needs to be done early, before the memory is reused, which is why the initial handling must reside here. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 52 Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf | 4 +- 2 files changed, 55 insertions(+), 1 deletion(-) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c index b682d631d0c2..b44c58d61062 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c @@ -22,10 +22,12 @@ #include #include #include +#include #include #include +#include #include #define ARM_MEMORY_REGION(Base, Size) \ @@ -177,6 +179,11 @@ MemoryPeim ( { EFI_STATUSStatus; ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + EFI_PEI_SERVICES **PeiServices; + PEI_CAPSULE_PPI *Capsule; + VOID *CapsuleBuffer; + UINTN CapsuleBufferLength; + BOOLEAN HaveCapsule; Status = DeclareDram (); ASSERT_EFI_ERROR (Status); @@ -184,12 +191,57 @@ MemoryPeim ( return Status; } + PeiServices = (EFI_PEI_SERVICES **) GetPeiServicesTablePointer (); + ASSERT (PeiServices != NULL); + + Status = PeiServicesLocatePpi (, 0, NULL, + (VOID **)); + ASSERT_EFI_ERROR (Status); + + // + // Check for persistent capsules + // + HaveCapsule = FALSE; + Status = Capsule->CheckCapsuleUpdate (PeiServices); + if (!EFI_ERROR (Status)) { + +// +// Coalesce the capsule into unused memory. CreateState() below will copy +// it to a properly allocated buffer. +// +CapsuleBuffer = (VOID *)PcdGet64 (PcdSystemMemoryBase); +CapsuleBufferLength = UefiMemoryBase - PcdGet64 (PcdSystemMemoryBase); + +PeiServicesSetBootMode (BOOT_ON_FLASH_UPDATE); + +Status = Capsule->Coalesce (PeiServices, , + ); +if (!EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "%a: Coalesced capsule @ %p (0x%lx)\n", +__FUNCTION__, CapsuleBuffer, CapsuleBufferLength)); + HaveCapsule = TRUE; +} else { + DEBUG ((DEBUG_WARN, "%a: failed to coalesce() capsule (Status == %r)\n", +__FUNCTION__, Status)); +} + } + Status = ArmConfigureMmu (VirtualMemoryTable, NULL, NULL); ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { return Status; } + if (HaveCapsule) { +Status = Capsule->CreateState (PeiServices, CapsuleBuffer, +CapsuleBufferLength); + +if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: Capsule->CreateState failed (Status == %r)\n", +__FUNCTION__, Status)); +} + } + if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) { // Optional feature that helps prevent EFI memory map fragmentation. BuildMemoryTypeInformationHob (); diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf index db3e3b3792e4..6c3420a525d6 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf @@ -39,6 +39,7 @@ [LibraryClasses] DebugLib MemoryAllocationLib PeiServicesLib + PeiServicesTablePointerLib [FeaturePcd] gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob @@ -62,7 +63,8 @@ [Pcd] gArmTokenSpaceGuid.PcdSystemMemoryBase [Ppis] + gPeiCapsulePpiGuid## CONSUMES gSynQuacerDramInfoPpiGuid ## CONSUMES [Depex] - gSynQuacerDramInfoPpiGuid + gPeiCapsulePpiGuid AND gSynQuacerDramInfoPpiGuid -- 2.11.0 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH edk2-platforms v4 20/34] Platform/SynQuacerEvalBoard: add signed capsule update support
Add all the boilerplate to make the SPI NOR image updateable using signed capsules and the FMP protocol. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 20 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 86 Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 46 +++ Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 68 Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc | 80 ++ Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 25 ++ 6 files changed, 325 insertions(+) diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index 0f60bb65a11b..4630d78bce93 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -120,6 +120,10 @@ [LibraryClasses.common] NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf [LibraryClasses.common.SEC] @@ -157,7 +161,15 @@ [LibraryClasses.common.DXE_DRIVER] DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + + # + # Firmware update + # CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf + EdkiiSystemCapsuleLib|SignedCapsulePkg/Library/EdkiiSystemCapsuleLib/EdkiiSystemCapsuleLib.inf + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf + PlatformFlashAccessLib|Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.inf + IniParsingLib|SignedCapsulePkg/Library/IniParsingLib/IniParsingLib.inf # # PCI @@ -575,3 +587,11 @@ [Components.common] # DT support # Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf + + # + # Firmware update + # + Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf + MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf index 80cbcdad18aa..365085c8f243 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf @@ -209,6 +209,16 @@ [FV.FvMain] # INF RuleOverride = DTB Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf + # + # Firmware update + # + INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf + INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf + FILE FREEFORM = PCD(gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiPkcs7TestPublicKeyFileGuid) { + SECTION RAW = BaseTools/Source/Python/Pkcs7Sign/TestRoot.cer + SECTION UI = "Pkcs7TestRoot" + } + [FV.FVMAIN_COMPACT] FvAlignment= 16 BlockSize = 0x1 @@ -238,6 +248,7 @@ [FV.FVMAIN_COMPACT] INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf + INF RuleOverride = FMP_IMAGE_DESC Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { @@ -246,6 +257,72 @@ [FV.FVMAIN_COMPACT] } } +[FV.CapsuleDispatchFv] +FvAlignment= 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS= TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS= TRUE +READ_LOCK_CAP = TRUE
[edk2] [PATCH edk2-platforms v4 19/34] Socionext/SynQuacerEvalBoard: switch to execute in place
Now that we switched to PrePeiCore, we can execute the firmware image in place, using a stack and temporary heap in non-secure SRAM. This allows us to query the secure firmware for the size and placement of DRAM, and also allows the use of capsules for firmware update. NOTE: this requires ARM Trusted Firmware to be built with PRELOADED_BL33_BASE set to the base of UEFI in the NOR flash, 0x820_ in our case. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf index c099c3dd8d2f..80cbcdad18aa 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf @@ -26,7 +26,7 @@ [FD.BL33_AP_UEFI] -BaseAddress = 0xE000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +BaseAddress = 0x0820|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. Size = 0x0020|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device ErasePolarity = 1 -- 2.11.0 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH edk2-platforms v4 18/34] Socionext/SynQuacerEvalBoard: wire up basic capsule support
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 7 ++- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 2 ++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index 2d107f13f352..0f60bb65a11b 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -157,6 +157,7 @@ [LibraryClasses.common.DXE_DRIVER] DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf # # PCI @@ -182,7 +183,7 @@ [LibraryClasses.common.UEFI_APPLICATION] [LibraryClasses.common.DXE_RUNTIME_DRIVER] BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf @@ -198,6 +199,8 @@ [PcdsFeatureFlag] gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE + [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Linaro" @@ -388,7 +391,9 @@ [Components.common] ArmPlatformPkg/PlatformPei/PlatformPeim.inf ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf ArmPkg/Drivers/CpuPei/CpuPei.inf + MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Universal/CapsulePei/CapsulePei.inf MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf index ac5c458134b0..c099c3dd8d2f 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf @@ -235,7 +235,9 @@ [FV.FVMAIN_COMPACT] INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { -- 2.11.0 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH edk2-platforms v4 13/34] Silicon/SynQuacer: add NorFlashPlatformLib implementation
Add the platform glue for the NOR flash driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c | 70 Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf | 41 2 files changed, 111 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c new file mode 100644 index ..816d8ba33f8c --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c @@ -0,0 +1,70 @@ +/** @file + + Copyright (c) 2011-2014, ARM Ltd. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + **/ + +#include +#include +#include +#include + +#include + +STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = { + { +// UEFI code region +SYNQUACER_SPI_NOR_BASE, // device base +FixedPcdGet64 (PcdFdBaseAddress), // region base +FixedPcdGet32 (PcdFdSize), // region size +SIZE_64KB, // block size +{ + 0x19c118b0, 0xc423, 0x42be, { 0xb8, 0x0f, 0x70, 0x6f, 0x1f, 0xcb, 0x59, 0x9a } +} + }, + { +// Environment variable region +SYNQUACER_SPI_NOR_BASE, // device base +FixedPcdGet32 (PcdFlashNvStorageVariableBase), // region base +FixedPcdGet32 (PcdFlashNvStorageVariableSize) + +FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + +FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize), // region size +SIZE_64KB, // block size +{ + 0x3105bd7a, 0x82c3, 0x486f, { 0xb1, 0x03, 0x1e, 0x09, 0x54, 0xec, 0x85, 0x75 } +} + }, +}; + +EFI_STATUS +NorFlashPlatformInitialization ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +NorFlashPlatformGetDevices ( + OUT NOR_FLASH_DESCRIPTION **NorFlashDevices, + OUT UINT32 *Count + ) +{ + if (NorFlashDevices == NULL || + Count == NULL) { +return EFI_INVALID_PARAMETER; + } + + *Count = ARRAY_SIZE (mNorFlashDevices); + *NorFlashDevices = mNorFlashDevices; + + return EFI_SUCCESS; +} diff --git a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf new file mode 100644 index ..2a8fd209f5e3 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf @@ -0,0 +1,41 @@ +#/** @file +# +# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION= 0x0001001A + BASE_NAME = NorFlashSynQuacerLib + FILE_GUID = 8279227C-C555-4D75-B439-D8A959635CDD + MODULE_TYPE= BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = NorFlashPlatformLib + +[Sources] + NorFlashSynQuacer.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Socionext/SynQuacer/SynQuacer.dec + +[LibraryClasses] + BaseLib + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize -- 2.11.0 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH edk2-platforms v4 12/34] Silicon/SynQuacer: add device tree support for eval board
Add a device tree description of the SynQuacer SoC, and expose it for the SynQuacerEvalBoard platforms. This includes the menu option in the UEFI boot menu to switch between ACPI and DT. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 6 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 11 + Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 514 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 21 + Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf | 33 ++ 5 files changed, 585 insertions(+) diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index f6a1d1ad8eda..60a53dd797ed 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -154,6 +154,7 @@ [LibraryClasses.common.DXE_CORE] PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf [LibraryClasses.common.DXE_DRIVER] + DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefault/DxeDtPlatformDtbLoaderLibDefault.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf @@ -536,3 +537,8 @@ [Components.common] DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf } + + # + # DT support + # + Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf index d87829b18902..c10e333efd43 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf @@ -1,3 +1,4 @@ + # # Copyright (c) 2013-2014, ARM Limited. All rights reserved. # Copyright (c) 2017, Linaro Limited. All rights reserved. @@ -198,6 +199,11 @@ [FV.FvMain] INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf INF Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf + # + # DT support + # + INF RuleOverride = DTB Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf + [FV.FVMAIN_COMPACT] FvAlignment= 16 BlockSize = 0x1 @@ -336,3 +342,8 @@ [Rule.Common.UEFI_APPLICATION.BINARY] UISTRING="$(MODULE_NAME)" Optional VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) } + +[Rule.Common.USER_DEFINED.DTB] + FILE FREEFORM = $(NAMED_GUID) { +RAW BIN|.dtb + } diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi new file mode 100644 index ..f89e722219ad --- /dev/null +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -0,0 +1,514 @@ +/** @file + * Copyright (c) 2017, Linaro Limited. All rights reserved. + * + * This program and the accompanying materials are licensed and made + * available under the terms and conditions of the BSD License which + * accompanies this distribution. The full text of the license may be + * found at http://opensource.org/licenses/bsd-license.php + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR + * IMPLIED. + */ + +#define GIC_SPI 0 +#define GIC_PPI 1 + +#define IRQ_TYPE_NONE 0 +#define IRQ_TYPE_EDGE_RISING1 +#define IRQ_TYPE_EDGE_FALLING 2 +#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) +#define IRQ_TYPE_LEVEL_HIGH 4 +#define IRQ_TYPE_LEVEL_LOW 8 + +/ { +#address-cells = <2>; +#size-cells = <2>; +interrupt-parent = <>; +dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + +aliases { +serial0 = _uart0; +}; + +chosen { +stdout-path = "serial0:115200n8"; +}; + +cpus { +#address-cells = <1>; +#size-cells = <0>; + +CPU0: cpu@0 { +device_type = "cpu"; +compatible = "arm,cortex-a53","arm,armv8"; +reg = <0x0>; +enable-method = "psci"; +//cpu-idle-states = <_SLEEP_0 _SLEEP_0>; +}; +CPU1: cpu@1 { +device_type = "cpu"; +compatible = "arm,cortex-a53","arm,armv8"; +reg = <0x1>; +enable-method = "psci"; +//cpu-idle-states = <_SLEEP_0 _SLEEP_0>; +}; +CPU2: cpu@100 { +device_type = "cpu"; +compatible = "arm,cortex-a53","arm,armv8"; +reg = <0x100>; +enable-method = "psci"; +
[edk2] [PATCH edk2-platforms v4 16/34] Silicon/SynQuacer: implement PlatformFlashAccessLib
In order to support capsule update, implement PlatformFlashAccessLib that exposes write access to the UEFI NOR partition. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.c | 251 Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.inf | 38 +++ 2 files changed, 289 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.c new file mode 100644 index ..5a67f8c00995 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformFlashAccessLib/SynQuacerPlatformFlashAccessLib.c @@ -0,0 +1,251 @@ +/** @file + Platform flash device access library for Socionext SynQuacer + + Copyright (c) 2016, Linaro, Ltd. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include +#include +#include +#include +#include +#include + +#include + +/** + Gets firmware volume block handle by given address. + + This function gets firmware volume block handle whose + address range contains the parameter Address. + + @param[in] AddressAddress which should be contained + by returned FVB handle. + @param[out] FvbHandle Pointer to FVB handle for output. + + @retval EFI_SUCCESSFVB handle successfully returned. + @retval EFI_NOT_FOUND Failed to find FVB handle by address. + +**/ +STATIC +EFI_STATUS +GetFvbByAddress ( + IN EFI_PHYSICAL_ADDRESSAddress, + OUT EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL **OutFvb, + OUT EFI_PHYSICAL_ADDRESS*FvbBaseAddress + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN HandleCount; + UINTN Index; + EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *Fvb; + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader; + EFI_FVB_ATTRIBUTES_2Attributes; + + // + // Locate all handles with Firmware Volume Block protocol + // + Status = gBS->LocateHandleBuffer ( + ByProtocol, + , + NULL, + , + + ); + if (EFI_ERROR (Status)) { +return EFI_NOT_FOUND; + } + // + // Traverse all the handles, searching for the one containing parameter Address + // + for (Index = 0; Index < HandleCount; Index += 1) { +Status = gBS->HandleProtocol ( +HandleBuffer[Index], +, +(VOID **) +); +if (EFI_ERROR (Status)) { + Status = EFI_NOT_FOUND; + break; +} +// +// Checks if the address range of this handle contains parameter Address +// +Status = Fvb->GetPhysicalAddress (Fvb, FvbBaseAddress); +if (EFI_ERROR (Status)) { + continue; +} + +// +// Check if this FVB is writable: DXE core produces FVB protocols for +// firmware volumes as well. +// +Status = Fvb->GetAttributes (Fvb, ); +if (EFI_ERROR (Status) || !(Attributes & EFI_FVB2_WRITE_STATUS)) { + DEBUG ((DEBUG_INFO, +"%a: ignoring read-only FVB protocol implementation\n", +__FUNCTION__)); + continue; +} + +FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *) ((UINTN) *FvbBaseAddress); +if ((Address >= *FvbBaseAddress) && (Address <= (*FvbBaseAddress + FwVolHeader->FvLength))) { + *OutFvb = Fvb; + Status = EFI_SUCCESS; + break; +} + +Status = EFI_NOT_FOUND; + } + + FreePool (HandleBuffer); + return Status; +} + +/** + Perform flash write operation. + + @param[in] FirmwareType The type of firmware. + @param[in] FlashAddress The address of flash device to be accessed. + @param[in] FlashAddressType The type of flash device address. + @param[in] BufferThe pointer to the data buffer. + @param[in] LengthThe length of data buffer in bytes. + + @retval EFI_SUCCESS The operation returns successfully. + @retval EFI_WRITE_PROTECTED The flash device is read only. + @retval EFI_UNSUPPORTED The flash device access is unsupported. + @retval EFI_INVALID_PARAMETER The input parameter is not valid. +**/ +EFI_STATUS
[edk2] [PATCH edk2-platforms v4 10/34] Platform/SynQuacerEvalBoard: add PCI support
Wire up the various drivers and libraries for the SynQuacerEvalBoard platform. Also enable the usual PCI suspects: XHCI, SATA and NVME, and the various bus, partition and file system drivers that we need to make use of PCIe devices. Given how PCI support enables USB support too, and taking the lack of a RNG on this SoC into account, let's enable the ChaosKey driver as well. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 52 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 41 +++ 2 files changed, 93 insertions(+) diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index 59c55fe13af1..126a588de587 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -100,6 +100,7 @@ [LibraryClasses.common] DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf # BDS Libraries UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf @@ -153,6 +154,12 @@ [LibraryClasses.common.DXE_DRIVER] SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + # + # PCI + # + PciSegmentLib|Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/SynQuacerPciSegmentLib.inf + PciHostBridgeLib|Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf + [LibraryClasses.common.UEFI_APPLICATION] PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf @@ -196,6 +203,7 @@ [PcdsFixedAtBuild.common] gSynQuacerTokenSpaceGuid.PcdDramInfoBase|0x2E00FFC0 gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 # 12x 2-core processor clusters gArmPlatformTokenSpaceGuid.PcdCoreCount|2 @@ -438,3 +446,47 @@ [Components.common] # Platform driver # Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf + + # + # PCI + # + Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { + +gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F + } + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + MdeModulePkg/Universal/EbcDxe/EbcDxe.inf + + # + # AHCI Support + # + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + + # + # USB + # + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + + # + # RNG + # + Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf index cc5377b1413f..b72a8ef664c3 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf @@ -133,6 +133,47 @@ [FV.FvMain] # INF Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf + # + # PCI + # + INF Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf + + # + # AHCI Support + # + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + + #
[edk2] [PATCH edk2-platforms v4 15/34] Platform/SynQuacer: incorporate NOR flash and variable drivers
Wire up the non-volatile EFI variable store support, by switching from the emulation driver to the real one, and enabling the prerequisite FTW and NOR flash drivers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 30 +++- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 9 -- Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 12 Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf | 3 ++ 4 files changed, 51 insertions(+), 3 deletions(-) diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index 60a53dd797ed..2d107f13f352 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -341,6 +341,19 @@ [PcdsFixedAtBuild.common] # gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE + # + # Variable store + # + gFip006DxeTokenSpaceGuid.PcdFip006DxeRegBaseAddress|0x5480 + gFip006DxeTokenSpaceGuid.PcdFip006DxeMemBaseAddress|0x0800 + + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0840 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x0001 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0841 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x0001 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0842 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x0001 + [PcdsPatchableInModule] gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 @@ -407,7 +420,6 @@ [Components.common] MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf ArmPkg/Drivers/TimerDxe/TimerDxe.inf - MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf @@ -426,6 +438,22 @@ [Components.common] } # + # Variable services + # + Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.inf { + + NorFlashPlatformLib|Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf + } + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + } + + # # UEFI application (Shell Embedded Boot Loader) # ShellPkg/Application/Shell/Shell.inf { diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf index c10e333efd43..ac5c458134b0 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf @@ -1,4 +1,3 @@ - # # Copyright (c) 2013-2014, ARM Limited. All rights reserved. # Copyright (c) 2017, Linaro Limited. All rights reserved. @@ -101,7 +100,6 @@ [FV.FvMain] INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf - INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf @@ -116,6 +114,13 @@ [FV.FvMain] INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf # + # Variable services + # + INF Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + # # UEFI applications # INF ShellPkg/Application/Shell/Shell.inf diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c index 30b42080d515..b682d631d0c2 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c @@ -97,6 +97,18 @@ STATIC
[edk2] [PATCH edk2-platforms v4 05/34] Silicon/SynQuacer: add MemoryInitPeiLib implementation
Implement MemoryInitPeiLib based on the newly added DramInfo PPI, which retrieves the DRAM information from lower level firmware. Note that the firmware volumes in SPI NOR are mapped with different attributes: the FV containing the PEI modules that may execute in place is mapped as uncached memory, given that it requires executable permissions. The FV containing the compressed DXE modules is mapped with device attributes for performance (!), and copied into DRAM by the platform PEIM once permanent memory is installed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- v4: use non-shareable writeback cacheable memory type for SPI NOR and EEPROM add GPIO block Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 186 Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf | 65 +++ 2 files changed, 251 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c new file mode 100644 index ..30b42080d515 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c @@ -0,0 +1,186 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#define ARM_MEMORY_REGION(Base, Size) \ + { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK } + +#define ARM_UNCACHED_REGION(Base, Size) \ + { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED } + +#define ARM_DEVICE_REGION(Base, Size) \ + { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_DEVICE } + +#define ARM_CACHED_DEVICE_REGION(Base, Size) \ + { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE } + +VOID +BuildMemoryTypeInformationHob ( + VOID + ); + +STATIC CONST EFI_RESOURCE_ATTRIBUTE_TYPE mDramResourceAttributes = + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + +STATIC CONST ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = { + // Memory mapped SPI NOR flash + ARM_CACHED_DEVICE_REGION (FixedPcdGet64 (PcdFdBaseAddress), +FixedPcdGet32 (PcdFdSize)), + + // SynQuacer OnChip peripherals + ARM_DEVICE_REGION (SYNQUACER_PERIPHERALS_BASE, + SYNQUACER_PERIPHERALS_SZ), + + // SynQuacer OnChip non-secure SRAM + ARM_CACHED_DEVICE_REGION (SYNQUACER_NON_SECURE_SRAM_BASE, +SYNQUACER_NON_SECURE_SRAM_SZ), + + // SynQuacer GIC-500 + ARM_DEVICE_REGION (SYNQUACER_GIC500_DIST_BASE, SYNQUACER_GIC500_DIST_SIZE), + ARM_DEVICE_REGION (SYNQUACER_GIC500_RDIST_BASE, SYNQUACER_GIC500_RDIST_SIZE), + + // SynQuacer eMMC(SDH30) + ARM_DEVICE_REGION (SYNQUACER_EMMC_BASE, SYNQUACER_EMMC_BASE_SZ), + + // SynQuacer GPIO block + ARM_DEVICE_REGION (SYNQUACER_GPIO_BASE, SYNQUACER_GPIO_SIZE), + + // SynQuacer EEPROM - could point to NOR flash as well + ARM_CACHED_DEVICE_REGION (FixedPcdGet32 (PcdNetsecEepromBase), +SYNQUACER_EEPROM_BASE_SZ), + + // SynQuacer NETSEC + ARM_DEVICE_REGION (SYNQUACER_NETSEC1_BASE, SYNQUACER_NETSEC1_BASE_SZ), + + // PCIe control registers + ARM_DEVICE_REGION (SYNQUACER_PCIE_BASE, SYNQUACER_PCIE_SIZE), + + // PCIe config space + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_CONFIG_BASE, + SYNQUACER_PCI_SEG0_CONFIG_SIZE), + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_CONFIG_BASE, + SYNQUACER_PCI_SEG1_CONFIG_SIZE), + + // PCIe I/O space + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_PORTIO_MEMBASE, + SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE), + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_PORTIO_MEMBASE, + SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE), +}; + +STATIC +EFI_STATUS +DeclareDram ( + OUT ARM_MEMORY_REGION_DESCRIPTOR**VirtualMemoryTable + ) +{ + SYNQUACER_DRAM_INFO_PPI *DramInfo; + EFI_STATUSStatus; + UINTN
[edk2] [PATCH edk2-platforms v4 14/34] Silicon/Socionext: add driver for SPI NOR flash
From: Pipat MethavanitpongThis imports the driver sources provided by Socionext for the FIP006 SPI NOR flash device found on SynQuacer SoCs. It has been slightly tweaked to bring it up to date with the changes made on the EDK2 side since it was forked. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pipat Methavanitpong [various tweaks and bugfixes] Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- v4: incorporate feedback from Leif, with the exception of subjective feedback (i.e., 'this function is too long'), addressing of which would make this driver deviate more from the driver it as based on in ArmPlatformPkg, making it less likely we can ever merge these into a unified NOR flash driver. Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.dec| 31 + Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.inf| 81 ++ Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Reg.h | 244 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashBlockIoDxe.c | 138 ++ Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashDxe.c| 1391 Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashDxe.h| 357 + Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlashFvbDxe.c | 853 7 files changed, 3095 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.dec b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.dec new file mode 100644 index ..aec95bc82387 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.dec @@ -0,0 +1,31 @@ +## @file +# Socionext FIP006 High-Speed SPI Controller with NOR Flash Driver +# +# Copyright (c) 2017, Socionext Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + DEC_SPECIFICATION = 0x0001001A + PACKAGE_NAME = Fip006DxePkg + PACKAGE_GUID = ABC7870B-FE82-4DAD-8179-FEC5F5194FA0 + PACKAGE_VERSION = 0.1 + +[Guids] + gFip006DxeTokenSpaceGuid = {0x4D45399E, 0x98F9, 0x4127, {0x8F, 0xB9,0xF8, 0xDE, 0x22, 0xA1, 0x09, 0x2C}} + +[PcdsFixedAtBuild] + gFip006DxeTokenSpaceGuid.PcdFip006DxeRegBaseAddress|0x0|UINT32|0x0001 + gFip006DxeTokenSpaceGuid.PcdFip006DxeMemBaseAddress|0x0|UINT32|0x0002 + gFip006DxeTokenSpaceGuid.PcdN25qSlaveId|0x0|UINT8|0x0003 + gFip006DxeTokenSpaceGuid.PcdN25qBlockSize|256|UINT32|0x0004 + gFip006DxeTokenSpaceGuid.PcdN25qBlockCount|524288|UINT32|0x0005 + diff --git a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.inf b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.inf new file mode 100644 index ..62f81cfe33cd --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.inf @@ -0,0 +1,81 @@ +## @file +# Socionext FIP006 High-Speed SPI Controller with NOR Flash Driver +# +# Copyright (c) 2017, Socionext Inc. All rights reserved. +# Copyright (c) 2017, Linaro, Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + + +[Defines] + INF_VERSION= 0x0001001A + BASE_NAME = Fip006Dxe + FILE_GUID = 44F7D21F-C36F-4766-BC5B-C72E97E6897B + MODULE_TYPE= DXE_RUNTIME_DRIVER + VERSION_STRING = 0.1 + ENTRY_POINT= NorFlashInitialise + +[Sources] + NorFlashBlockIoDxe.c + NorFlashDxe.c + NorFlashFvbDxe.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/Fip006Dxe.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DevicePathLib + DxeServicesTableLib + HobLib + IoLib + MemoryAllocationLib + NorFlashInfoLib + NorFlashPlatformLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeLib + UefiRuntimeServicesTableLib + +[Guids] + gEfiAuthenticatedVariableGuid +
[edk2] [PATCH edk2-platforms v4 09/34] Silicon/SynQuacer: implement EFI_CPU_IO2_PROTOCOL
The SynQuacer SOC has two separate PCIe RCs, which means there is no single value for the translation offset between I/O port accesses and MMIO accesses. So add a special implementation of EFI_CPU_IO2_PROTOCOL that takes the two disjoint I/O windows into account. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c | 590 Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.inf | 50 ++ 2 files changed, 640 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c new file mode 100644 index ..6ef44b11bb7d --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c @@ -0,0 +1,590 @@ +/** @file + Produces the CPU I/O 2 Protocol. + +Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved. +Copyright (c) 2016 - 2017, Linaro Ltd. All rights reserved. + +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include +#include + +#include +#include +#include +#include +#include + +#define MAX_IO_PORT_ADDRESS SYNQUACER_PCI_SEG1_PORTIO_MAX + +// +// Handle for the CPU I/O 2 Protocol +// +STATIC EFI_HANDLE mHandle = NULL; + +// +// Lookup table for increment values based on transfer widths +// +STATIC CONST UINT8 mInStride[] = { + 1, // EfiCpuIoWidthUint8 + 2, // EfiCpuIoWidthUint16 + 4, // EfiCpuIoWidthUint32 + 8, // EfiCpuIoWidthUint64 + 0, // EfiCpuIoWidthFifoUint8 + 0, // EfiCpuIoWidthFifoUint16 + 0, // EfiCpuIoWidthFifoUint32 + 0, // EfiCpuIoWidthFifoUint64 + 1, // EfiCpuIoWidthFillUint8 + 2, // EfiCpuIoWidthFillUint16 + 4, // EfiCpuIoWidthFillUint32 + 8 // EfiCpuIoWidthFillUint64 +}; + +// +// Lookup table for increment values based on transfer widths +// +STATIC CONST UINT8 mOutStride[] = { + 1, // EfiCpuIoWidthUint8 + 2, // EfiCpuIoWidthUint16 + 4, // EfiCpuIoWidthUint32 + 8, // EfiCpuIoWidthUint64 + 1, // EfiCpuIoWidthFifoUint8 + 2, // EfiCpuIoWidthFifoUint16 + 4, // EfiCpuIoWidthFifoUint32 + 8, // EfiCpuIoWidthFifoUint64 + 0, // EfiCpuIoWidthFillUint8 + 0, // EfiCpuIoWidthFillUint16 + 0, // EfiCpuIoWidthFillUint32 + 0 // EfiCpuIoWidthFillUint64 +}; + +/** + Check parameters to a CPU I/O 2 Protocol service request. + + The I/O operations are carried out exactly as requested. The caller is responsible + for satisfying any alignment and I/O width restrictions that a PI System on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will + be handled by the driver. + + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] AddressThe base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number of +bytes moved is Width size * Count, starting at Address. + @param[in] Buffer For read operations, the destination buffer to store the results. +For write operations, the source buffer from which to write data. + + @retval EFI_SUCCESSThe parameters for this request pass the checks. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTEDThe Buffer is not aligned for the given Width. + @retval EFI_UNSUPPORTEDThe address range specified by Address, Width, + and Count is not valid for this PI system. + +**/ +STATIC +EFI_STATUS +CpuIoCheckParameter ( + IN BOOLEANMmioOperation, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT64 MaxCount; + UINT64 Limit; + + // + // Check to see if Buffer is NULL + // + if (Buffer == NULL) { +ASSERT (FALSE); +return EFI_INVALID_PARAMETER; + } + + // + // Check to see if Width is in the valid range + // + if ((UINT32)Width >= EfiCpuIoWidthMaximum) { +ASSERT (FALSE); +return EFI_INVALID_PARAMETER; + } + + // + // For FIFO type, the target
[edk2] [PATCH edk2-platforms v4 11/34] Platform/SynQuacerEvalBoard: add NETSEC driver
Add the NETSEC driver to the SynQuacerEvalBoard platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 46 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 24 ++ 2 files changed, 70 insertions(+) diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index 126a588de587..f6a1d1ad8eda 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -114,6 +114,9 @@ [LibraryClasses.common] SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf + HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf + TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf @@ -233,6 +236,22 @@ [PcdsFixedAtBuild.common] gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2a44 gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2a45 + # + # NETSEC Info + # + gNetsecDxeTokenSpaceGuid.PcdEncTxDescNum|128 + gNetsecDxeTokenSpaceGuid.PcdDecRxDescNum|128 + gNetsecDxeTokenSpaceGuid.PcdJumboPacket|0 + gNetsecDxeTokenSpaceGuid.PcdFlowCtrl|0 + gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold|36 + gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold|48 + gNetsecDxeTokenSpaceGuid.PcdPauseTime|256 + + gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase|0x1000 + gSynQuacerTokenSpaceGuid.PcdNetsecPhyAddress|1 + + gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections|TRUE + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|100 gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|100 gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|100 @@ -490,3 +509,30 @@ [Components.common] # RNG # Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf + + # + # Networking stack + # + MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf + MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + NetworkPkg/Ip6Dxe/Ip6Dxe.inf + NetworkPkg/TcpDxe/TcpDxe.inf + NetworkPkg/Udp6Dxe/Udp6Dxe.inf + NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf + NetworkPkg/IScsiDxe/IScsiDxe.inf + NetworkPkg/DnsDxe/DnsDxe.inf + NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf + NetworkPkg/HttpDxe/HttpDxe.inf + NetworkPkg/HttpBootDxe/HttpBootDxe.inf + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf { + + DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf + } diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf index b72a8ef664c3..d87829b18902 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf @@ -174,6 +174,30 @@ [FV.FvMain] # INF Silicon/Openmoko/ChaosKeyDxe/ChaosKeyDxe.inf + # + # Networking stack + # + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf + INF NetworkPkg/TcpDxe/TcpDxe.inf + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf + INF NetworkPkg/IScsiDxe/IScsiDxe.inf + INF NetworkPkg/DnsDxe/DnsDxe.inf + INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf + INF NetworkPkg/HttpDxe/HttpDxe.inf + INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf + INF Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf + [FV.FVMAIN_COMPACT] FvAlignment= 16 BlockSize = 0x1 -- 2.11.0 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH edk2-platforms v4 04/34] Silicon/SynQuacer: implement a platform DXE driver
This implements a driver that will take care of platform specific initialization, such as declaring non-discoverable devices, and installing the device tree blob as a configuration table. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 122 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 55 + Silicon/Socionext/SynQuacer/SynQuacer.dec | 3 + 3 files changed, 180 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c new file mode 100644 index ..9639c09f --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -0,0 +1,122 @@ +/** @file + SynQuacer DXE platform driver. + + Copyright (c) 2017, Linaro, Ltd. All rights reserved. + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +STATIC EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR mNetsecDesc[] = { + { +ACPI_ADDRESS_SPACE_DESCRIPTOR,// Desc +sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3, // Len +ACPI_ADDRESS_SPACE_TYPE_MEM, // ResType +0,// GenFlag +0,// SpecificFlag +32, // AddrSpaceGranularity +SYNQUACER_NETSEC1_BASE, // AddrRangeMin +SYNQUACER_NETSEC1_BASE + +SYNQUACER_NETSEC1_BASE_SZ - 1,// AddrRangeMax +0,// AddrTranslationOffset +SYNQUACER_NETSEC1_BASE_SZ,// AddrLen + }, { +ACPI_ADDRESS_SPACE_DESCRIPTOR,// Desc +sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3, // Len +ACPI_ADDRESS_SPACE_TYPE_MEM, // ResType +0,// GenFlag +0,// SpecificFlag +32, // AddrSpaceGranularity +FixedPcdGet32 (PcdNetsecEepromBase), // AddrRangeMin +FixedPcdGet32 (PcdNetsecEepromBase) + +SYNQUACER_EEPROM_BASE_SZ - 1, // AddrRangeMax +0,// AddrTranslationOffset +SYNQUACER_EEPROM_BASE_SZ, // AddrLen + }, { +ACPI_ADDRESS_SPACE_DESCRIPTOR,// Desc +sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3, // Len +ACPI_ADDRESS_SPACE_TYPE_MEM, // ResType +0,// GenFlag +0,// SpecificFlag +32, // AddrSpaceGranularity +FixedPcdGet32 (PcdNetsecPhyAddress), // AddrRangeMin +FixedPcdGet32 (PcdNetsecPhyAddress), // AddrRangeMax +0,// AddrTranslationOffset +1,// AddrLen + }, { +ACPI_END_TAG_DESCRIPTOR // Desc + } +}; + +STATIC +EFI_STATUS +RegisterNetsec ( + VOID + ) +{ + NON_DISCOVERABLE_DEVICE *Device; + EFI_STATUS Status; + EFI_HANDLE Handle; + + Device = (NON_DISCOVERABLE_DEVICE *)AllocateZeroPool (sizeof (*Device)); + if (Device == NULL) { +return EFI_OUT_OF_RESOURCES; + } + + Device->Type = + Device->DmaType = NonDiscoverableDeviceDmaTypeNonCoherent; + Device->Resources = mNetsecDesc; + + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces (, + , Device, + NULL); + if (EFI_ERROR (Status)) { +goto FreeDevice; + } + return EFI_SUCCESS; + +FreeDevice: + FreePool (Device); + + return Status; +} + +EFI_STATUS +EFIAPI +PlatformDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + VOID*Dtb; + UINTN DtbSize; + + Dtb = NULL; + Status = DtPlatformLoadDtb (, ); + if (!EFI_ERROR (Status)) { +Status = gBS->InstallConfigurationTable
[edk2] [PATCH edk2-platforms v4 06/34] Platform: add support for Socionext SynQuacer eval board
This is a barebones port based on the .DSC/.FDF and ArmPlatformLib code provided by Socionext. It can boot into the UiApp menu screen or the UEFI Shell, but lacks support for any peripherals. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 440 Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 273 Silicon/Socionext/SynQuacer/Library/SynQuacerLib/AArch64/SynQuacerHelper.S | 87 Silicon/Socionext/SynQuacer/Library/SynQuacerLib/Arm/SynQuacerHelper.S | 87 Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacer.c | 125 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacerLib.inf | 43 ++ 6 files changed, 1055 insertions(+) diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc new file mode 100644 index ..59c55fe13af1 --- /dev/null +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -0,0 +1,440 @@ +# +# Copyright (c) 2013-2014, ARM Limited. All rights reserved. +# Copyright (c) 2017, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + + +# +# Defines Section - statements that will be processed to create a Makefile. +# + +[Defines] + PLATFORM_NAME = SynQuacerEvalBoard + PLATFORM_GUID = a8180daa-fb8b-11e5-ab24-9fc3167c073d + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001B + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES= AARCH64|ARM + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf + +[BuildOptions] + RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=0 + +[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION] + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000 + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x1 + +[LibraryClasses.common] + ArmPlatformLib|Silicon/Socionext/SynQuacer/Library/SynQuacerLib/SynQuacerLib.inf + ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + +!if $(TARGET) == RELEASE + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + + BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf + + # Networking Requirements + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf + + # ARM Architectural Libraries + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf +
[edk2] [PATCH edk2-platforms v4 00/34] add support for Socionext SynQuacer
This adds support for the Socionext Synquacer SC2A11 evaluation board and revision 0.1/0.2 of the Developer Box. It implements support for the core peripherals (CPU, GIC, serial), and for the two PCIe RCs present on this board, as well as the NETSEC network controller. The DT description contains references to drivers that are not upstream yet, and will be merged into Linux v4.15 at the earliest. No other OS support is currently planned (as far as I am aware) The non-volatile EFI variable store is backed by the SPI NOR flash, which is therefore not exposed to the OS. Note that it occupies the 'devtree' partition, which must be wiped before use. A driver for the NETSEC network interface is included, which means network boot is supported as well. (Note that this driver deviates in coding style. This code is based on the platform independent driver provided by Socionext, and making cosmetic changes to it will only make it more difficult to track upstream changes) Changes since v3: - remove ACPI support for now, we can add it on top if we manage to sort out all the SoC quirks that make it difficult to have full support under ACPI - add RTC support to DeveloperBox - add eMMC support to SynQuacerEvalBoard - incorporate review feedback on the SPI NOR driver (which was possible after noticing that I did in fact have a manual for this IP) - map NOR and EEPROM as writeback cacheable non-shareable; this allows the split FV hack to be reverted, and improves boot time considerably - some other minor changes have been applied, these have been added to the individual patches as notes Changes since v2: - converted NETSEC driver to UEFI driver model - added a platform DXE driver that declares the non-discoverable NETSEC device for the UEFI driver model driver to bind to - remove hardcoded DRAM information - everything is now retrieved from ARM Trusted Firmware - added DT descriptions of the GPIO and interrupt controller IP blocks - addressed various style issues and merge errors highlighted by Leif Ard Biesheuvel (33): Silicon/SynQuacer: add package with platform headers Silicon/Socionext: add driver for NETSEC network controller Silicon/Socionext: add PlatformPeilib implementation for SynQuacer Silicon/SynQuacer: implement a platform DXE driver Silicon/SynQuacer: add MemoryInitPeiLib implementation Platform: add support for Socionext SynQuacer eval board Silicon/SynQuacer: implement PciSegmentLib to support dual RCs Silicon/SynQuacer: implement PciHostBridgeLib support Silicon/SynQuacer: implement EFI_CPU_IO2_PROTOCOL Platform/SynQuacerEvalBoard: add PCI support Platform/SynQuacerEvalBoard: add NETSEC driver Silicon/SynQuacer: add device tree support for eval board Silicon/SynQuacer: add NorFlashPlatformLib implementation Platform/SynQuacer: incorporate NOR flash and variable drivers Silicon/SynQuacer: implement PlatformFlashAccessLib SynQuacer/SynQuacerMemoryInitPeiLib: add capsule support Socionext/SynQuacerEvalBoard: wire up basic capsule support Socionext/SynQuacerEvalBoard: switch to execute in place Platform/SynQuacerEvalBoard: add signed capsule update support Silicon/SynQuacerPciHostBridgeLib: add workaround to support 32-bit only cards Platform/Socionext: add support for Socionext Developer Box rev 0.1 Platform/DeveloperBox: add ConsolePrefDxe driver Silicon/SynQuacer: add description of GPIO block to device tree Silicon/SynQuacer: add description of EXIU to the device tree Silicon/SynQuacer: add DT description of the SDHCI controller Silicon/SynQuacerMemoryInitPeiLib: ignore capsules when clearing NVRAM Silicon/SynQuacer: implement PEIM that exposes GPIO PPI Silicon/SynQuacer: implement 'clear NVRAM' feature using a DIP switch Silicon/NXP: add RTC support library for PCF8563 I2C IP Silicon/Socionext: implement I2C master protocol for SynQuacer I2C Platform/DeveloperBox: wire up RTC support Platform/DeveloperBox: add description of power button to DT Platform/SynQuacerEvalBoard: add eMMC driver stack Pipat Methavanitpong (1): Silicon/Socionext: add driver for SPI NOR flash Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 630 + Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 465 +++ Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf | 46 + Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c | 68 + Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptorTable.aslc | 80 ++ Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 25 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
[edk2] [PATCH edk2-platforms v4 01/34] Silicon/SynQuacer: add package with platform headers
Add a package .DEC description for SynQuacer with an [Includes] section, and add header files containing descriptions of the platform's memory map and PCIe configuration. No code yet. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 60 +++ Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 63 Silicon/Socionext/SynQuacer/SynQuacer.dec| 20 +++ 3 files changed, 143 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h new file mode 100644 index ..f29a35809bac --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h @@ -0,0 +1,60 @@ +/** @file + Physical memory map for SynQuacer + + Copyright (c) 2017, Linaro Ltd. All rights reserved. + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SYNQUACER_PLATFORM_MEMORYMAP_H_ +#define _SYNQUACER_PLATFORM_MEMORYMAP_H_ + +// Memory mapped SPI NOR +#define SYNQUACER_SPI_NOR_BASE 0x0800 +#define SYNQUACER_SPI_NOR_SIZE SIZE_128MB + +// On-Chip non-secure ROM +#define SYNQUACER_NON_SECURE_ROM_BASE 0x1F00 +#define SYNQUACER_NON_SECURE_ROM_SZ SIZE_512KB + +// On-Chip Peripherals +#define SYNQUACER_PERIPHERALS_BASE 0x2000 +#define SYNQUACER_PERIPHERALS_SZ0x0E00 + +// On-Chip non-secure SRAM +#define SYNQUACER_NON_SECURE_SRAM_BASE 0x2E00 +#define SYNQUACER_NON_SECURE_SRAM_SZSIZE_64KB + +// GIC-500 +#define SYNQUACER_GIC500_DIST_BASE FixedPcdGet64 (PcdGicDistributorBase) +#define SYNQUACER_GIC500_DIST_SIZE SIZE_256KB +#define SYNQUACER_GIC500_RDIST_BASE FixedPcdGet64 (PcdGicRedistributorsBase) +#define SYNQUACER_GIC500_RDIST_SIZE SIZE_8MB + +// GPIO block +#define SYNQUACER_GPIO_BASE 0x5100 +#define SYNQUACER_GPIO_SIZE SIZE_4KB + +// eMMC(SDH30) +#define SYNQUACER_EMMC_BASE 0x5230 +#define SYNQUACER_EMMC_BASE_SZ SIZE_4KB + +#define SYNQUACER_EEPROM_BASE 0x1000 +#define SYNQUACER_EEPROM_BASE_SZSIZE_64KB + +// NETSEC +#define SYNQUACER_NETSEC1_BASE 0x522D +#define SYNQUACER_NETSEC1_BASE_SZ SIZE_64KB + +// PCI +#define SYNQUACER_PCIE_BASE 0x5820 +#define SYNQUACER_PCIE_SIZE 0x0020 + +#endif diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h new file mode 100644 index ..d2a3f9acbf49 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h @@ -0,0 +1,63 @@ +/** @file + PCI memory configuration for SynQuacer + + Copyright (c) 2017, Linaro Ltd. All rights reserved. + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SYNQUACER_PLATFORM_PCI_H_ +#define _SYNQUACER_PLATFORM_PCI_H_ + +#define SYNQUACER_PCI_SEG0_CONFIG_BASE 0x6000 +#define SYNQUACER_PCI_SEG0_CONFIG_SIZE 0x07f0 +#define SYNQUACER_PCI_SEG0_DBI_BASE 0x583d +#define SYNQUACER_PCI_SEG0_EXS_BASE 0x5839 + +#define SYNQUACER_PCI_SEG0_BUSNUM_MIN 0x0 +#define SYNQUACER_PCI_SEG0_BUSNUM_MAX 0x7e + +#define SYNQUACER_PCI_SEG0_PORTIO_MIN 0x0 +#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0x +#define SYNQUACER_PCI_SEG0_PORTIO_SIZE 0x1 +#define SYNQUACER_PCI_SEG0_PORTIO_MEMBASE 0x67f0 +#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE SYNQUACER_PCI_SEG0_PORTIO_SIZE + +#define SYNQUACER_PCI_SEG0_MMIO32_MIN 0x6800 +#define SYNQUACER_PCI_SEG0_MMIO32_MAX 0x6fff +#define SYNQUACER_PCI_SEG0_MMIO32_SIZE 0x0800 + +#define SYNQUACER_PCI_SEG0_MMIO64_MIN 0x3e +#define SYNQUACER_PCI_SEG0_MMIO64_MAX 0x3e +#define SYNQUACER_PCI_SEG0_MMIO64_SIZE 0x1 + +#define SYNQUACER_PCI_SEG1_CONFIG_BASE 0x7000 +#define SYNQUACER_PCI_SEG1_CONFIG_SIZE 0x07f0 +#define SYNQUACER_PCI_SEG1_DBI_BASE 0x583c +#define SYNQUACER_PCI_SEG1_EXS_BASE 0x5838 +
[edk2] [PATCH edk2-platforms v4 08/34] Silicon/SynQuacer: implement PciHostBridgeLib support
Implement the glue library that exposes the PCIe root complexes to the generic PCI host bridge driver. Since that driver is the first one to access the PCI config space, put the low level init code for the RCs into this library's constructor. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 225 +++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 50 +++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 390 3 files changed, 665 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c new file mode 100644 index ..42cdce24b2c4 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c @@ -0,0 +1,225 @@ +/** @file + PCI Host Bridge Library instance for Socionext SynQuacer ARM SOC + + Copyright (c) 2017, Linaro Ltd. All rights reserved. + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#pragma pack(1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { + { +{ + { +ACPI_DEVICE_PATH, +ACPI_DP, +{ + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) +} + }, + EISA_PNP_ID (0x0A08), // PCI Express + 0 +}, + +{ + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { +END_DEVICE_PATH_LENGTH, +0 + } +} + }, + { +{ + { +ACPI_DEVICE_PATH, +ACPI_DP, +{ + (UINT8)(sizeof(ACPI_HID_DEVICE_PATH)), + (UINT8)(sizeof(ACPI_HID_DEVICE_PATH) >> 8) +} + }, + EISA_PNP_ID (0x0A08), // PCI Express + 1 +}, + +{ + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { +END_DEVICE_PATH_LENGTH, +0 + } +} + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { + L"Mem", L"I/O", L"Bus" +}; + +#ifndef MDE_CPU_ARM +#define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | \ +EFI_PCI_HOST_BRIDGE_MEM64_DECODE +#else +#define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM +#endif + +STATIC PCI_ROOT_BRIDGE mPciRootBridges[] = { + { +0, // Segment +0, // Supports +0, // Attributes +TRUE, // DmaAbove4G +FALSE, // NoExtendedConfigSpace +FALSE, // ResourceAssigned +PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes +{ SYNQUACER_PCI_SEG0_BUSNUM_MIN, + SYNQUACER_PCI_SEG0_BUSNUM_MAX }, // Bus +{ SYNQUACER_PCI_SEG0_PORTIO_MIN, + SYNQUACER_PCI_SEG0_PORTIO_MAX }, // Io +{ SYNQUACER_PCI_SEG0_MMIO32_MIN, + SYNQUACER_PCI_SEG0_MMIO32_MAX }, // Mem +{ SYNQUACER_PCI_SEG0_MMIO64_MIN, + SYNQUACER_PCI_SEG0_MMIO64_MAX }, // MemAbove4G +{ MAX_UINT64, 0x0 },// PMem +{ MAX_UINT64, 0x0 },// PMemAbove4G +(EFI_DEVICE_PATH_PROTOCOL *)[0] + }, { +1, // Segment +0, // Supports +0, // Attributes +TRUE, // DmaAbove4G +FALSE, // NoExtendedConfigSpace +FALSE, // ResourceAssigned +PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes +{ SYNQUACER_PCI_SEG1_BUSNUM_MIN, + SYNQUACER_PCI_SEG1_BUSNUM_MAX }, // Bus +{ SYNQUACER_PCI_SEG1_PORTIO_MIN, + SYNQUACER_PCI_SEG1_PORTIO_MAX }, // Io +
[edk2] [PATCH edk2-platforms v4 07/34] Silicon/SynQuacer: implement PciSegmentLib to support dual RCs
Having two distinct root complexes is not supported by the standard set of PciLib/PciExpressLib/PciSegmentLib, so let's reimplement one of the latter specifically for this platform (and forget about the others). This also allows us to implement the Synopsys Designware PCIe specific workaround for PCI config space accesses to devices 1 and up on bus 0. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/PciSegmentLib.c | 1398 Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/SynQuacerPciSegmentLib.inf | 35 + 2 files changed, 1433 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/PciSegmentLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/PciSegmentLib.c new file mode 100644 index ..62f3b2015d2b --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegmentLib/PciSegmentLib.c @@ -0,0 +1,1398 @@ +/** @file + PCI Segment Library for SynQuacer SoC with multiple RCs + + Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved. + Copyright (c) 2017, Linaro, Ltd. All rights reserved. + + This program and the accompanying materials are + licensed and made available under the terms and conditions of + the BSD License which accompanies this distribution. The full + text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include +#include +#include +#include + +#include + +typedef enum { + PciCfgWidthUint8 = 0, + PciCfgWidthUint16, + PciCfgWidthUint32, + PciCfgWidthMax +} PCI_CFG_WIDTH; + +/** + Assert the validity of a PCI Segment address. + A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63 + + @param A The address to validate. + @param M Additional bits to assert to be zero. + +**/ +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \ + ASSERT (((A) & (0xf000ULL | (M))) == 0) + +STATIC +UINT64 +PciSegmentLibGetConfigBase ( + IN UINT64 Address + ) +{ + switch ((UINT16)(Address >> 32)) { + case 0: +return SYNQUACER_PCI_SEG0_CONFIG_BASE; + case 1: +return SYNQUACER_PCI_SEG1_CONFIG_BASE; + default: +ASSERT (FALSE); + } + + return 0; +} + +/** + Internal worker function to read a PCI configuration register. + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + @param Width The width of data to read + + @return The value read from the PCI configuration register. + +**/ +STATIC +UINT32 +PciSegmentLibReadWorker ( + IN UINT64 Address, + IN PCI_CFG_WIDTH Width + ) +{ + UINT64Base; + + Base = PciSegmentLibGetConfigBase (Address); + + // ignore devices > 0 on bus 0 + if ((Address & 0xff0) == 0 && (Address & 0xf8000) != 0) { +return 0x; + } + + switch (Width) { + case PciCfgWidthUint8: +return MmioRead8 (Base + (UINT32)Address); + case PciCfgWidthUint16: +return MmioRead16 (Base + (UINT32)Address); + case PciCfgWidthUint32: +return MmioRead32 (Base + (UINT32)Address); + default: +ASSERT (FALSE); + } + + return 0; +} + +/** + Internal worker function to writes a PCI configuration register. + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + @param Width The width of data to write + @param DataThe value to write. + + @return The value written to the PCI configuration register. + +**/ +STATIC +UINT32 +PciSegmentLibWriteWorker ( + IN UINT64 Address, + IN PCI_CFG_WIDTH Width, + IN UINT32 Data + ) +{ + UINT64Base; + + Base = PciSegmentLibGetConfigBase (Address); + + // ignore devices > 0 on bus 0 + if ((Address & 0xff0) == 0 && (Address & 0xf8000) != 0) { +return Data; + } + + switch (Width) { + case PciCfgWidthUint8: +MmioWrite8 (Base + (UINT32)Address, Data); +break; + case PciCfgWidthUint16: +MmioWrite16 (Base + (UINT32)Address, Data); +break; + case PciCfgWidthUint32: +MmioWrite32 (Base + (UINT32)Address, Data); +break; + default: +ASSERT (FALSE); + } + + return Data; +} + +/** + Register a PCI device so PCI configuration registers may be accessed after + SetVirtualAddressMap(). + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + + @retval RETURN_SUCCESS The PCI device was registered for runtime access. + @retval RETURN_UNSUPPORTED An attempt was made
[edk2] [PATCH edk2-platforms v4 03/34] Silicon/Socionext: add PlatformPeilib implementation for SynQuacer
Create a specialized PlatformPeiLib implementation that invokes the platform specific firmware interface (currently, just a data structure left in SRAM) to set the ARM standard PcdSystemMemoryBase|Size PCDs, and expose the information via a newly added DramInfo PPI. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- v4: remove code to copy the compressed FV to DRAM, this is no longer necessary now that we have figured out how to map the NOR flash cacheable Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h | 30 + Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h | 64 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c | 123 Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf | 50 Silicon/Socionext/SynQuacer/SynQuacer.dec | 9 ++ 5 files changed, 276 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h b/Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h new file mode 100644 index ..f7691bdade4a --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h @@ -0,0 +1,30 @@ +/** @file + Data structure for passing DRAM information from lower level firmware + + Copyright (c) 2017, Linaro Ltd. All rights reserved. + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SYNQUACER_PLATFORM_DRAM_INFO_H_ +#define _SYNQUACER_PLATFORM_DRAM_INFO_H_ + +typedef struct { + UINT64Base; + UINT64Size; +} DRAM_INFO_ENTRY; + +typedef struct { + UINT32NumRegions; + UINT32Reserved; + DRAM_INFO_ENTRY Entry[3]; +} DRAM_INFO; + +#endif diff --git a/Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h b/Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h new file mode 100644 index ..6453e121317d --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h @@ -0,0 +1,64 @@ +/** @file + DRAM info PPI to retrieve DRAM information from lower level firmware + + Copyright (c) 2017, Linaro Ltd. All rights reserved. + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SYNQUACER_DRAMINFO_PPI_ +#define _SYNQUACER_DRAMINFO_PPI_ + +#define SYNQUACER_DRAMINFO_PPI_GUID \ + { 0x3e1d7356, 0xdda4, 0x4b1a, { 0x93, 0x46, 0xbf, 0x89, 0x1c, 0x86, 0x46, 0xcc } } + +/** + Retrieve the number of discontiguous DRAM regions + + @param[out] RegionCount The number of available DRAM regions + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_INVALID_PARAMETER RegionCount == NULL + +**/ +typedef +EFI_STATUS +(EFIAPI * DRAMINFO_GET_REGION_COUNT) ( + OUT UINTN *RegionCount + ); + +/** + Retrieve the base and size of a DRAM region + + @param[in] RegionIndex The 0-based index of the region to retrieve + @param[out] Base The base of the requested region + @param[out] Size The size of the requested region + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_INVALID_PARAMETER Base == NULL or Size == NULL + @retval EFI_NOT_FOUND No region exists with index >= RegionIndex + +**/ +typedef +EFI_STATUS +(EFIAPI * DRAMINFO_GET_REGION) ( + INUINTN RegionIndex, + OUT UINT64*Base, + OUT UINT64*Size + ); + +typedef struct { + DRAMINFO_GET_REGION_COUNT GetRegionCount; + DRAMINFO_GET_REGION GetRegion; +} SYNQUACER_DRAM_INFO_PPI; + +extern EFI_GUID gSynQuacerDramInfoPpiGuid; + +#endif diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c new file mode 100644 index ..358dd5a91f08 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c @@ -0,0 +1,123 @@ +/** @file +* +* Copyright (c)
[edk2] [RFC PATCH 2/2] MdeModulePkg/SdMmcPciHcDxe: allow HC capabilities to be overridden
Invoke the newly introduced SD/MMC override protocol to override the capabilities register after reading it from the device registers, and to call the pre/post host init and reset hooks at the appropriate times. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel--- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 111 +++- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 ++ MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf | 2 + 3 files changed, 114 insertions(+), 5 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c index 0be8828abfcc..d328e9f867c4 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c @@ -60,7 +60,8 @@ SD_MMC_HC_PRIVATE_DATA gSdMmcPciHcTemplate = { { // MaxCurrent 0, }, - 0 // ControllerVersion + 0,// ControllerVersion + NULL // Override }; SD_DEVICE_PATHmSdDpTemplate = { @@ -213,6 +214,88 @@ Done: return; } +STATIC +EFI_STATUS +SdMmcPciHcResetHost ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot + ) +{ + EFI_STATUSStatus; + + if (Private->Override != NULL && + Private->Override->InvokeHook != NULL) { +Status = Private->Override->InvokeHook ( + Private->ControllerHandle, + Slot, + SD_MMC_OVERRIDE_RESET_PRE_HOOK); +if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: SD/MMC pre reset hook failed - %r\n", +__FUNCTION__, Status)); + return Status; +} + } + + Status = SdMmcHcReset (Private->PciIo, Slot); + if (EFI_ERROR (Status)) { +return Status; + } + + if (Private->Override != NULL && + Private->Override->InvokeHook != NULL) { +Status = Private->Override->InvokeHook ( + Private->ControllerHandle, + Slot, + SD_MMC_OVERRIDE_RESET_POST_HOOK); +if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: SD/MMC post reset hook failed - %r\n", +__FUNCTION__, Status)); +} + } + return Status; +} + +STATIC +EFI_STATUS +SdMmcPciHcInitHost ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot + ) +{ + EFI_STATUSStatus; + + if (Private->Override != NULL && + Private->Override->InvokeHook != NULL) { +Status = Private->Override->InvokeHook ( + Private->ControllerHandle, + Slot, + SD_MMC_OVERRIDE_INIT_HOST_PRE_HOOK); +if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: SD/MMC pre init hook failed - %r\n", +__FUNCTION__, Status)); + return Status; +} + } + + Status = SdMmcHcInitHost (Private->PciIo, Slot, Private->Capability[Slot]); + if (EFI_ERROR (Status)) { +return Status; + } + + if (Private->Override != NULL && + Private->Override->InvokeHook != NULL) { +Status = Private->Override->InvokeHook ( + Private->ControllerHandle, + Slot, + SD_MMC_OVERRIDE_INIT_HOST_POST_HOOK); +if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: SD/MMC post init hook failed - %r\n", +__FUNCTION__, Status)); +} + } + return Status; +} + /** Sd removable device enumeration callback function when the timer event is signaled. @@ -281,14 +364,14 @@ SdMmcPciHcEnumerateDevice ( // // Reset the specified slot of the SD/MMC Pci Host Controller // -Status = SdMmcHcReset (Private->PciIo, Slot); +Status = SdMmcPciHcResetHost (Private, Slot); if (EFI_ERROR (Status)) { continue; } // // Reinitialize slot and restart identification process for the new attached device // -Status = SdMmcHcInitHost (Private->PciIo, Slot, Private->Capability[Slot]); +Status = SdMmcPciHcInitHost (Private, Slot); if (EFI_ERROR (Status)) { continue; } @@ -601,6 +684,12 @@ SdMmcPciHcDriverBindingStart ( goto Done; } + Status = gBS->HandleProtocol (Controller, , + (VOID **)>Override); + if (!EFI_ERROR (Status)) { +DEBUG ((DEBUG_INFO, "%a: using SD/MMC override protocol\n", __FUNCTION__)); + } + Support64BitDma = TRUE; for (Slot = FirstBar; Slot < (FirstBar + SlotNum); Slot++) { Private->Slot[Slot].Enable = TRUE; @@ -609,6 +698,18 @@ SdMmcPciHcDriverBindingStart ( if (EFI_ERROR (Status)) { continue; } +if
[edk2] [RFC PATCH 1/2] MdeModulePkg: introduce SD/MMC override protocol
Many ARM based SoCs have integrated SDHCI controllers, and often, these implementations deviate in subtle ways from the pertinent specifications. On the one hand, these deviations are quite easy to work around, but on the other hand, having a collection of SoC specific workarounds in the generic driver stack is undesirable. So let's introduce an optional SD/MMC override protocol that we can invoke at the appropriate moments in the device initialization. That way, the workaround itself remains platform specific, but we can still use the generic driver stack on such platforms. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel--- MdeModulePkg/Include/Protocol/SdMmcOverride.h | 95 MdeModulePkg/MdeModulePkg.dec | 3 + 2 files changed, 98 insertions(+) diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h new file mode 100644 index ..95fc48bb8dee --- /dev/null +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h @@ -0,0 +1,95 @@ +/** @file + Protocol to describe overrides required to support non-standard SDHCI + implementations + + Copyright (c) 2017, Linaro, Ltd. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SD_MMC_OVERRIDE_H__ +#define __SD_MMC_OVERRIDE_H__ + +#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \ + { 0xeaf9e3c1, 0xc9cd, 0x46db, { 0xa5, 0xe5, 0x5a, 0x12, 0x4c, 0x83, 0x23, 0x23 } } + +#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION0x1 + +typedef struct _SD_MMC_OVERRIDE SD_MMC_OVERRIDE; + +typedef enum { + SD_MMC_OVERRIDE_RESET_PRE_HOOK, + SD_MMC_OVERRIDE_RESET_POST_HOOK, + SD_MMC_OVERRIDE_INIT_HOST_PRE_HOOK, + SD_MMC_OVERRIDE_INIT_HOST_POST_HOOK, +} SD_MMC_OVERRIDE_HOOK; + +/** + + Override function for SDHCI capability bits + + @param[in] ControllerHandle The EFI_HANDLE of the controller. + @param[in] Slot The 0 based slot index. + @param[in,out] SdMmcHcSlotCapability The SDHCI capability structure. + + @retval EFI_SUCCESS The override function completed successfully. + @retval EFI_NOT_FOUND The specified controller or slot does not exist. + @retval EFI_INVALID_PARAMETER SdMmcHcSlotCapability is NULL + +**/ +typedef +EFI_STATUS +(EFIAPI * SD_MMC_OVERRIDE_CAPABILITY) ( + IN EFI_HANDLE ControllerHandle, + IN UINT8 Slot, + IN OUT VOID*SdMmcHcSlotCapability + ); + +/** + + Override function for SDHCI controller operations + + @param[in] ControllerHandleThe EFI_HANDLE of the controller. + @param[in] SlotThe 0 based slot index. + @param[in,out] HookTypeThe type of operation and whether the + hook is invoked right before (pre) or + right after (post) + + @retval EFI_SUCCESS The override function completed successfully. + @retval EFI_NOT_FOUND The specified controller or slot does not exist. + @retval EFI_INVALID_PARAMETER HookType is invalid + +**/ +typedef +EFI_STATUS +(EFIAPI * SD_MMC_OVERRIDE_INVOKE_HOOK) ( + IN EFI_HANDLE ControllerHandle, + IN UINT8 Slot, + IN SD_MMC_OVERRIDE_HOOKHookType + ); + +struct _SD_MMC_OVERRIDE { + // + // Protocol version of this implementation + // + UINTN Version; + // + // Callback to override SD/MMC host controller capability bits + // + SD_MMC_OVERRIDE_CAPABILITY OverrideCapability; + // + // Callback to invoke SD/MMC override hooks + // + SD_MMC_OVERRIDE_INVOKE_HOOK InvokeHook; +}; + +extern EFI_GUID gEdkiiSdMmcOverrideProtocolGuid; + +#endif diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 92ee02708013..d14326199591 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -559,6 +559,9 @@ [Protocols] ## Include/Protocol/SmmEndofS3Resume.h gEdkiiSmmEndOfS3ResumeProtocolGuid = { 0x96f5296d, 0x05f7, 0x4f3c, {0x84, 0x67, 0xe4, 0x56, 0x89, 0x0e, 0x0c, 0xb5 } } + ## Include/Protocol/SdMmcOverride.h + gEdkiiSdMmcOverrideProtocolGuid = { 0xeaf9e3c1, 0xc9cd, 0x46db, { 0xa5, 0xe5, 0x5a, 0x12, 0x4c, 0x83, 0x23, 0x23 } } + # # [Error.gEfiMdeModulePkgTokenSpaceGuid] # 0x8001 | Invalid value provided. -- 2.11.0 ___ edk2-devel mailing list edk2-devel@lists.01.org
[edk2] [RFC PATCH 0/2] quirks handling for SDHCI controllers
Many SDHCI implementations exist that are almost spec complicant, and could be driver by the generic SD/MMC host controller driver except for some minimal necessary init time tweaks. Adding such tweaks to the generic driver is undesirable. On the other hand, forking the driver for every platform that has such a SDHCI controller is problematic when it comes to upstreaming and ongoing maintenance (which is arguably the point of upstreaming in the first place). So these patches propose a workaround that is minimally invasive on the EDK2 side, but gives platforms a lot of leeway when it comes to applying SDHCI quirks. Ard Biesheuvel (2): MdeModulePkg: introduce SD/MMC override protocol MdeModulePkg/SdMmcPciHcDxe: allow HC capabilities to be overridden MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 111 +++- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 ++ MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf | 2 + MdeModulePkg/Include/Protocol/SdMmcOverride.h| 95 + MdeModulePkg/MdeModulePkg.dec| 3 + 5 files changed, 212 insertions(+), 5 deletions(-) create mode 100644 MdeModulePkg/Include/Protocol/SdMmcOverride.h -- 2.11.0 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
Re: [edk2] [PATCH v5] UefiCpuPkg/CpuDxe: Fix multiple entries of RT_CODE in memory map
Hi Jian, I'm CC'ing Ard and Matt, and commenting at the bottom. On 11/10/17 02:02, Jian J Wang wrote: >> v5: >>Coding style clean-up > >> v4: >> a. Remove DoUpdate and check attributes mismatch all the time to avoid >>a logic hole >> b. Add warning message if failed to update capability >> c. Add local variable to hold new attributes to make code cleaner > >> v3: >> a. Add comment to explain more on updating memory capabilities >> b. Fix logic hole in updating attributes >> c. Instead of checking illegal memory space address and size, use return >>status of gDS->SetMemorySpaceCapabilities() to skip memory block which >>cannot be updated with new capabilities. > >> v2 >> a. Fix an issue which will cause setting capability failure if size is >> smaller >>than a page. > > More than one entry of RT_CODE memory might cause boot problem for some > old OSs. This patch will fix this issue to keep OS compatibility as much > as possible. > > More detailed information, please refer to > https://bugzilla.tianocore.org/show_bug.cgi?id=753 > > Cc: Eric Dong> Cc: Jiewen Yao > Cc: Laszlo Ersek > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Jian J Wang > --- > UefiCpuPkg/CpuDxe/CpuPageTable.c | 69 > +--- > 1 file changed, 50 insertions(+), 19 deletions(-) > > diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c > b/UefiCpuPkg/CpuDxe/CpuPageTable.c > index d312eb66f8..61537838b7 100644 > --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c > +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c > @@ -789,8 +789,7 @@ RefreshGcdMemoryAttributesFromPaging ( >UINT64 BaseAddress; >UINT64 PageStartAddress; >UINT64 Attributes; > - UINT64 Capabilities; > - BOOLEAN DoUpdate; > + UINT64 NewAttributes; >UINTN Index; > >// > @@ -802,9 +801,8 @@ RefreshGcdMemoryAttributesFromPaging ( > >GetCurrentPagingContext (); > > - DoUpdate = FALSE; > - Capabilities = 0; >Attributes= 0; > + NewAttributes = 0; >BaseAddress = 0; >PageLength= 0; > > @@ -813,6 +811,34 @@ RefreshGcdMemoryAttributesFromPaging ( >continue; > } > > +// > +// Sync the actual paging related capabilities back to GCD service first. > +// As a side effect (good one), this can also help to avoid unnecessary > +// memory map entries due to the different capabilities of the same type > +// memory, such as multiple RT_CODE and RT_DATA entries in memory map, > +// which could cause boot failure of some old Linux distro (before v4.3). > +// > +Status = gDS->SetMemorySpaceCapabilities ( > +MemorySpaceMap[Index].BaseAddress, > +MemorySpaceMap[Index].Length, > +MemorySpaceMap[Index].Capabilities | > +EFI_MEMORY_PAGETYPE_MASK > +); > +if (EFI_ERROR (Status)) { > + // > + // If we cannot udpate the capabilities, we cannot update its > + // attributes either. So just simply skip current block of memory. > + // > + DEBUG (( > +DEBUG_WARN, > +"Failed to update capability: [%lu] %016lx - %016lx (%016lx -> > %016lx)\r\n", > +(UINT64)Index, BaseAddress, BaseAddress + Length - 1, > +MemorySpaceMap[Index].Capabilities, > +MemorySpaceMap[Index].Capabilities | EFI_MEMORY_PAGETYPE_MASK > +)); > + continue; > +} > + > if (MemorySpaceMap[Index].BaseAddress >= (BaseAddress + PageLength)) { >// >// Current memory space starts at a new page. Resetting PageLength will > @@ -826,7 +852,9 @@ RefreshGcdMemoryAttributesFromPaging ( >PageLength -= (MemorySpaceMap[Index].BaseAddress - BaseAddress); > } > > -// Sync real page attributes to GCD > +// > +// Sync actual page attributes to GCD > +// > BaseAddress = MemorySpaceMap[Index].BaseAddress; > MemorySpaceLength = MemorySpaceMap[Index].Length; > while (MemorySpaceLength > 0) { > @@ -842,23 +870,26 @@ RefreshGcdMemoryAttributesFromPaging ( > PageStartAddress = (*PageEntry) & > (UINT64)PageAttributeToMask(PageAttribute); > PageLength= PageAttributeToLength (PageAttribute) - > (BaseAddress - PageStartAddress); > Attributes= GetAttributesFromPageEntry (PageEntry); > - > -if (Attributes != (MemorySpaceMap[Index].Attributes & > EFI_MEMORY_PAGETYPE_MASK)) { > - DoUpdate = TRUE; > - Attributes |= (MemorySpaceMap[Index].Attributes & > ~EFI_MEMORY_PAGETYPE_MASK); > - Capabilities = Attributes | MemorySpaceMap[Index].Capabilities; > -} else { > -
Re: [edk2] [PATCH v2] ArmPlatformPkg/PrePeiCore: seed temporary stack before entering PEI core
On 10 November 2017 at 09:29, Laszlo Ersekwrote: > On 11/09/17 22:11, Ard Biesheuvel wrote: >> On 7 November 2017 at 18:13, Ard Biesheuvel >> wrote: >>> On 7 November 2017 at 18:09, Laszlo Ersek wrote: On 11/05/17 17:29, Ard Biesheuvel wrote: > On 5 November 2017 at 16:27, Ard Biesheuvel > wrote: >> On 5 November 2017 at 05:52, Leif Lindholm >> wrote: >>> On Fri, Nov 03, 2017 at 11:33:52AM +, Ard Biesheuvel wrote: DEBUG builds of PEI code will print a diagnostic message regarding the utilization of temporary RAM before switching to permanent RAM. For example, Total temporary memory:16352 bytes. temporary memory stack ever used: 4820 bytes. temporary memory heap used for HobList: 4720 bytes. Tracking stack utilization like this requires the stack to be seeded with a known magic value, and this needs to occur before entering C code, given that it uses the stack. Currently, only Nt32Pkg appears to implement this feature, but it is useful nonetheless, so let's wire it up for PrePeiCore as well. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=748 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel >>> >>> OK, this may sound completely unreasonable, but seeing those >>> implementations overwrite callee-saved registers without saving them >>> makes my brain unhappy. (Yes, I know.) >>> >>> Could they either: >>> - Have a comment prepended establishing the implicit ABI of which >>> registers the caller cannot rely on reusing after return. >>> Preferably somewhat echoed at the call site. >>> - Be rewritten to use only scratch registers? >>> >> >> I think it is implied that the startup code does not adhere to the >> AAPCS. That code already uses r5 and r6 without stacking them, simply >> because we're in the middle of preparing the stack and other execution >> context, precisely so the C code we call into can rely on AAPCS >> guarantees. > > > Ehm, hold on, what do you mean by 'call site'? This code just runs and > jumps back to a local label. There are no functions calls here until > the point where we call into C (with the exception of the lovely > ArmPlatformPeiBootAction() we added so Juno can find out how much DRAM > it can use) Please continue the discussion with Leif on this; from my side, I'm happy with the patch (I've sort of deduced what the assembly code does, also relying on your v1 notes). The only eyebrow-raising part was: + MOV64 (x9, FixedPcdGet32 (PcdInitValueInTempStack) |\ + FixedPcdGet32 (PcdInitValueInTempStack) << 32) where we left-shift a constant that is "in theory" UINT32 by 32 binary places, using the << operator. In C that would be undefined behavior, but this is assembly, so what do I know? ¯\_(ツ)_/¯ Acked-by: Laszlo Ersek >>> >>> Thanks. And you're right, this is not C so no need to worry about that. >>> ( By the way, just to see if I remember correctly, isn't STP: +0:stp x9, x9, [x8], #16 the kind of instruction that modifies multiple operands at once, and so if it faults, it cannot be virtualized well? (Because the syndrome register or whatever does not tell the VMM the whole picture about the fault?) Totally irrelevant here, I'm just curious. >>> >>> STP == STore Pair, and so it stores the values in the registers to >>> memory. The only register that gets modified here is x8, due to the >>> post-increment. >>> >> >> ... which actually doesn't mean it is not affected by the same issue. >> >> The reason such instructions are more difficult to virtualize is that >> it requires KVM to decode the instruction, rather than read the >> syndrome registers that can tell it which register we intended to >> read/write from. So it is in fact perfectly feasible to virtualize it, >> but the KVM authors just haven't bothered yet. > > Hm, I'm slightly curious if and how this differs from x86 KVM :) In x86 > KVM there are huge instruction tables for emulation etc. > It does differ from x86: on ARM, you can derive most information you need to emulate an instruction from the CPU registers that describe the fault condition (i.e.. the syndrome register and the fault address register). Only, those registers can only describe a single general purpose register, anything that uses more is difficult to emulate. It is essentially laziness on the part of the KVM/ARM authors, because they have been able to get away with it up to this point :-)
Re: [edk2] [PATCH v2] ArmPlatformPkg/PrePeiCore: seed temporary stack before entering PEI core
On 11/09/17 22:11, Ard Biesheuvel wrote: > On 7 November 2017 at 18:13, Ard Biesheuvelwrote: >> On 7 November 2017 at 18:09, Laszlo Ersek wrote: >>> On 11/05/17 17:29, Ard Biesheuvel wrote: On 5 November 2017 at 16:27, Ard Biesheuvel wrote: > On 5 November 2017 at 05:52, Leif Lindholm > wrote: >> On Fri, Nov 03, 2017 at 11:33:52AM +, Ard Biesheuvel wrote: >>> DEBUG builds of PEI code will print a diagnostic message regarding >>> the utilization of temporary RAM before switching to permanent RAM. >>> For example, >>> >>> Total temporary memory:16352 bytes. >>> temporary memory stack ever used: 4820 bytes. >>> temporary memory heap used for HobList: 4720 bytes. >>> >>> Tracking stack utilization like this requires the stack to be seeded >>> with a known magic value, and this needs to occur before entering C >>> code, given that it uses the stack. Currently, only Nt32Pkg appears >>> to implement this feature, but it is useful nonetheless, so let's >>> wire it up for PrePeiCore as well. >>> >>> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=748 >>> Contributed-under: TianoCore Contribution Agreement 1.1 >>> Signed-off-by: Ard Biesheuvel >> >> OK, this may sound completely unreasonable, but seeing those >> implementations overwrite callee-saved registers without saving them >> makes my brain unhappy. (Yes, I know.) >> >> Could they either: >> - Have a comment prepended establishing the implicit ABI of which >> registers the caller cannot rely on reusing after return. >> Preferably somewhat echoed at the call site. >> - Be rewritten to use only scratch registers? >> > > I think it is implied that the startup code does not adhere to the > AAPCS. That code already uses r5 and r6 without stacking them, simply > because we're in the middle of preparing the stack and other execution > context, precisely so the C code we call into can rely on AAPCS > guarantees. Ehm, hold on, what do you mean by 'call site'? This code just runs and jumps back to a local label. There are no functions calls here until the point where we call into C (with the exception of the lovely ArmPlatformPeiBootAction() we added so Juno can find out how much DRAM it can use) >>> >>> Please continue the discussion with Leif on this; from my side, I'm >>> happy with the patch (I've sort of deduced what the assembly code does, >>> also relying on your v1 notes). >>> >>> The only eyebrow-raising part was: >>> >>> + MOV64 (x9, FixedPcdGet32 (PcdInitValueInTempStack) |\ >>> + FixedPcdGet32 (PcdInitValueInTempStack) << 32) >>> >>> where we left-shift a constant that is "in theory" UINT32 by 32 binary >>> places, using the << operator. In C that would be undefined behavior, >>> but this is assembly, so what do I know? ¯\_(ツ)_/¯ >>> >>> Acked-by: Laszlo Ersek >>> >> >> Thanks. And you're right, this is not C so no need to worry about that. >> >>> ( >>> >>> By the way, just to see if I remember correctly, isn't STP: >>> >>> +0:stp x9, x9, [x8], #16 >>> >>> the kind of instruction that modifies multiple operands at once, and so >>> if it faults, it cannot be virtualized well? (Because the syndrome >>> register or whatever does not tell the VMM the whole picture about the >>> fault?) >>> >>> Totally irrelevant here, I'm just curious. >>> >> >> STP == STore Pair, and so it stores the values in the registers to >> memory. The only register that gets modified here is x8, due to the >> post-increment. >> > > ... which actually doesn't mean it is not affected by the same issue. > > The reason such instructions are more difficult to virtualize is that > it requires KVM to decode the instruction, rather than read the > syndrome registers that can tell it which register we intended to > read/write from. So it is in fact perfectly feasible to virtualize it, > but the KVM authors just haven't bothered yet. Hm, I'm slightly curious if and how this differs from x86 KVM :) In x86 KVM there are huge instruction tables for emulation etc. Anyway I'm happy this patch is now committed! Thanks! Laszlo > >> But its converse >> >> LDP , , [], # >> >> is indeed such an instruction, given that it modifies three registers >> at once, and so the registers that encode the exception run out of >> space. Note that this only affects virtualized MMIO. ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH v3 1/3] EmbeddedPkg/RealTimeClockRuntimeDxe: move common functionality into core
RealTimeClockRuntimeDxe defers the hardware/platform specific handling of reading/setting the hardware clock to RealTimeClockLib, but for unknown reasons, it also defers common functionality such as input validation and recording the timezone and DST settings (which are informational only and not managed by hardware) This has led to a lot of duplication in implementations of RealTimeClockLib as well as TimeBaseLib, to the point where each library implementation has its own set of UEFI variables to record the timezone and DST settings. This makes little sense, and so let's update RealTimeClockRuntimeDxe now to allow future implementations to rely on the core driver to take care of these things. Note that reading the timezone and DST settings occurs before calling into the library, so we can phase out this behavior gradually from library implementations in EDK2, edk2-platforms or out of tree. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel--- EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClock.c | 171 +++- EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf | 11 +- 2 files changed, 171 insertions(+), 11 deletions(-) diff --git a/EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClock.c b/EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClock.c index f1e067c0b59e..8323a4b4b848 100644 --- a/EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClock.c +++ b/EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClock.c @@ -1,10 +1,8 @@ /** @file Implement EFI RealTimeClock runtime services via RTC Lib. - Currently this driver does not support runtime virtual calling. - - Copyright (c) 2008 - 2009, Apple Inc. All rights reserved. + Copyright (c) 2017, Linaro, Ltd. All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -17,14 +15,116 @@ **/ #include +#include +#include #include #include -#include +#include #include EFI_HANDLE mHandle = NULL; +// +// These values can be set by SetTime () and need to be returned by GetTime () +// but cannot usually be kept by the RTC hardware, so we store them in a UEFI +// variable instead. +// +typedef struct { + INT16 TimeZone; + UINT8 Daylight; +} NON_VOLATILE_TIME_SETTINGS; + +STATIC CONST CHAR16 mTimeSettingsVariableName[] = L"RtcTimeSettings"; +STATIC NON_VOLATILE_TIME_SETTINGS mTimeSettings; + +STATIC +BOOLEAN +IsValidTimeZone ( + IN INT16 TimeZone + ) +{ + return TimeZone == EFI_UNSPECIFIED_TIMEZONE || + (TimeZone >= -1440 && TimeZone <= 1440); +} + +STATIC +BOOLEAN +IsValidDaylight ( + IN INT8 Daylight + ) +{ + return Daylight == 0 || + Daylight == EFI_TIME_ADJUST_DAYLIGHT || + Daylight == (EFI_TIME_ADJUST_DAYLIGHT | EFI_TIME_IN_DAYLIGHT); +} +STATIC +BOOLEAN +EFIAPI +IsLeapYear ( + IN EFI_TIME *Time + ) +{ + if (Time->Year % 4 == 0) { +if (Time->Year % 100 == 0) { + if (Time->Year % 400 == 0) { +return TRUE; + } else { +return FALSE; + } +} else { + return TRUE; +} + } else { +return FALSE; + } +} + +STATIC CONST INTN mDayOfMonth[12] = { + 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 +}; + +STATIC +BOOLEAN +EFIAPI +IsDayValid ( + IN EFI_TIME *Time + ) +{ + ASSERT (Time->Day >= 1); + ASSERT (Time->Day <= mDayOfMonth[Time->Month - 1]); + ASSERT (Time->Month != 2 || IsLeapYear (Time) || Time->Day <= 28); + + if (Time->Day < 1 || + Time->Day > mDayOfMonth[Time->Month - 1] || + (Time->Month == 2 && !IsLeapYear (Time) && Time->Day > 28)) { +return FALSE; + } + return TRUE; +} + +STATIC +BOOLEAN +EFIAPI +IsTimeValid( + IN EFI_TIME *Time + ) +{ + // Check the input parameters are within the range specified by UEFI + if (Time->Year < 1900 || + Time->Year > || + Time->Month < 1 || + Time->Month > 12 || + !IsDayValid (Time)|| + Time->Hour > 23 || + Time->Minute > 59 || + Time->Second > 59 || + !IsValidTimeZone (Time->TimeZone) || + !IsValidDaylight (Time->Daylight)) { +return FALSE; + } + return TRUE; +} /** Returns the current time and date information, and the time-keeping capabilities @@ -43,9 +143,20 @@ EFI_STATUS EFIAPI GetTime ( OUT EFI_TIME*Time, - OUT EFI_TIME_CAPABILITIES *Capabilities + OUT EFI_TIME_CAPABILITIES *Capabilities ) { + if (Time == NULL) { +return EFI_INVALID_PARAMETER; + } + + // + // Set these first so the RealTimeClockLib implementation + // can override them based on its own settings. + // + Time->TimeZone = mTimeSettings.TimeZone; + Time->Daylight = mTimeSettings.Daylight; + return LibGetTime (Time, Capabilities); } @@ -67,7 +178,41 @@ SetTime ( IN
[edk2] [PATCH v3 2/3] ArmPlatformPkg/PL031RealTimeClockLib: remove validation and DST handling
This library, which is intended to encapsulate the hardware specifics of the ARM PL031 RTC, also implements its own input validation routines and record the timezone and DST settings in its own set of EFI variables. This functionality has recently been added to the core driver, so let's remove it here. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard BiesheuvelReviewed-by: Leif Lindholm --- ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c | 186 ++-- 1 file changed, 15 insertions(+), 171 deletions(-) diff --git a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c index 41ebcb95ab85..f1eb0deb3249 100644 --- a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c +++ b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c @@ -40,8 +40,6 @@ #include -STATIC CONST CHAR16 mTimeZoneVariableName[] = L"PL031RtcTimeZone"; -STATIC CONST CHAR16 mDaylightVariableName[] = L"PL031RtcDaylight"; STATIC BOOLEANmPL031Initialized = FALSE; STATIC EFI_EVENT mRtcVirtualAddrChangeEvent; STATIC UINTN mPL031RtcBase; @@ -134,15 +132,12 @@ LibGetTime ( { EFI_STATUS Status = EFI_SUCCESS; UINT32 EpochSeconds; - INT16 TimeZone; - UINT8 Daylight; - UINTN Size; // Initialize the hardware if not already done if (!mPL031Initialized) { Status = InitializePL031 (); if (EFI_ERROR (Status)) { - goto EXIT; + return Status; } } @@ -156,7 +151,7 @@ LibGetTime ( Status = EFI_SUCCESS; } else if (EFI_ERROR (Status)) { // Battery backed up hardware RTC exists but could not be read due to error. Abort. -goto EXIT; +return Status; } else { // Battery backed up hardware RTC exists and we read the time correctly from it. // Now sync the PL031 to the new time. @@ -165,107 +160,18 @@ LibGetTime ( // Ensure Time is a valid pointer if (Time == NULL) { -Status = EFI_INVALID_PARAMETER; -goto EXIT; +return EFI_INVALID_PARAMETER; } - // Get the current time zone information from non-volatile storage - Size = sizeof (TimeZone); - Status = EfiGetVariable ( - (CHAR16 *)mTimeZoneVariableName, - , - NULL, - , - (VOID *) - ); - - if (EFI_ERROR (Status)) { -ASSERT(Status != EFI_INVALID_PARAMETER); -ASSERT(Status != EFI_BUFFER_TOO_SMALL); - -if (Status != EFI_NOT_FOUND) - goto EXIT; - -// The time zone variable does not exist in non-volatile storage, so create it. -Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE; -// Store it -Status = EfiSetVariable ( -(CHAR16 *)mTimeZoneVariableName, -, -EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, -Size, -(VOID *)&(Time->TimeZone) -); -if (EFI_ERROR (Status)) { - DEBUG (( -EFI_D_ERROR, -"LibGetTime: Failed to save %s variable to non-volatile storage, Status = %r\n", -mTimeZoneVariableName, -Status -)); - goto EXIT; -} - } else { -// Got the time zone -Time->TimeZone = TimeZone; - -// Check TimeZone bounds: -1440 to 1440 or 2047 -if (((Time->TimeZone < -1440) || (Time->TimeZone > 1440)) -&& (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE)) { - Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE; -} - -// Adjust for the correct time zone -if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) { - EpochSeconds += Time->TimeZone * SEC_PER_MIN; -} + // Adjust for the correct time zone + if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) { +EpochSeconds += Time->TimeZone * SEC_PER_MIN; } - // Get the current daylight information from non-volatile storage - Size = sizeof (Daylight); - Status = EfiGetVariable ( - (CHAR16 *)mDaylightVariableName, - , - NULL, - , - (VOID *) - ); - - if (EFI_ERROR (Status)) { -ASSERT(Status != EFI_INVALID_PARAMETER); -ASSERT(Status != EFI_BUFFER_TOO_SMALL); - -if (Status != EFI_NOT_FOUND) - goto EXIT; - -// The daylight variable does not exist in non-volatile storage, so create it. -Time->Daylight = 0; -// Store it -Status = EfiSetVariable ( -(CHAR16 *)mDaylightVariableName, -, -EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, -Size, -(VOID *)&(Time->Daylight) -); -if
[edk2] [PATCH v3 0/3] ArmPlatformPkg EmbeddedPkg: consolidate shared RTC functionality
This moves input validation and recording of the DST and timezone settings (which cannot usually be done by the hardware) into the core RTC driver in EmbeddedPkg, and removes it from one of the RealTimeClockLib implementations, the one for the ARM PL031. v3: fix leap day assert condition whitespace fix add acks v2: split PL031 into two reinstate (but fix) the PL031 timezone handling (after reading and even understanding the original code) Ard Biesheuvel (3): EmbeddedPkg/RealTimeClockRuntimeDxe: move common functionality into core ArmPlatformPkg/PL031RealTimeClockLib: remove validation and DST handling ArmPlatformPkg/PL031RealTimeClockLib: ignore DST setting when timezone is set ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c | 194 ++-- EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClock.c | 171 - EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf | 11 +- 3 files changed, 188 insertions(+), 188 deletions(-) -- 2.11.0 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel