[edk2] [Patch] BaseTool: Fixed the StructurePcd incorrect value.

[BobCF]

If user not set Structure overall value in Dsc,
Structure Pcd value would be incorrect.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Bob Feng 
Cc: Liming Gao 
---
 BaseTools/Source/Python/Workspace/BuildClassObject.py | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/BaseTools/Source/Python/Workspace/BuildClassObject.py 
b/BaseTools/Source/Python/Workspace/BuildClassObject.py
index e5f1f01556..947ac1f466 100644
--- a/BaseTools/Source/Python/Workspace/BuildClassObject.py
+++ b/BaseTools/Source/Python/Workspace/BuildClassObject.py
@@ -65,11 +65,11 @@ class PcdClassObject(object):
 self.validlists = validlists
 self.expressions = expressions
 self.DscDefaultValue = None
 if IsDsc:
 self.DscDefaultValue = Value
-
+
 ## Convert the class to a string
 #
 #  Convert each member of the class to string
 #  Organize to a signle line format string
 #
@@ -107,11 +107,15 @@ class PcdClassObject(object):
 #
 def __hash__(self):
 return hash((self.TokenCName, self.TokenSpaceGuidCName))
 
 class StructurePcd(PcdClassObject):
-def __init__(self, StructuredPcdIncludeFile="", Packages=None, Name=None, 
Guid=None, Type=None, DatumType=None, Value=None, Token=None, 
MaxDatumSize=None, SkuInfoList={}, IsOverrided=False, GuidValue=None, 
validateranges=[], validlists=[], expressions=[],default_store = 
TAB_DEFAULT_STORES_DEFAULT):
+def __init__(self, StructuredPcdIncludeFile=None, Packages=None, 
Name=None, Guid=None, Type=None, DatumType=None, Value=None, Token=None, 
MaxDatumSize=None, SkuInfoList=None, IsOverrided=False, GuidValue=None, 
validateranges=None, validlists=None, expressions=None,default_store = 
TAB_DEFAULT_STORES_DEFAULT):
+if SkuInfoList is None: SkuInfoList={}
+if validateranges is None: validateranges=[]
+if validlists is None: validlists=[]
+if expressions is None : expressions=[]
 super(StructurePcd, self).__init__(Name, Guid, Type, DatumType, Value, 
Token, MaxDatumSize, SkuInfoList, IsOverrided, GuidValue, validateranges, 
validlists, expressions)
 self.StructuredPcdIncludeFile = StructuredPcdIncludeFile
 self.PackageDecs = Packages
 self.DefaultStoreName = [default_store]
 self.DefaultValues = collections.OrderedDict({})
@@ -435,6 +439,5 @@ class PlatformBuildClassObject(object):
 #
 # @retval string Key for hash table
 #
 def __hash__(self):
 return hash(self.MetaFile)
-
-- 
2.14.3.windows.1

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[edk2] [PATCH v2] UefiCpuPkg/MpInitLib: fix AP init issue in 64-bit PEI

[Jian J Wang]

> v2:
>Roll back changes (just white spaces) caused by misoperation in git

This issue is introduced by a patch at

   f32bfe6d061420a15bac6083063d227c567e6388

The above patch miss the case of 64-bit PEI, which will link
X64/MpFuncs.nasm instead of Ia32/MpFuncs.nasm. For X64/MpFuncs.nasm,
ExchangeInfo->ModeHighMemory should be always initialized no matter
if separate wakeup buffer is allocated or not. Ia32/MpFuncs.nasm will
not need ModeHighMemory during AP init. So the changes made in this
patch should not affect the functionality of it.

Cc: Ruiyu Ni 
Cc: Eric Dong 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang 
---
 UefiCpuPkg/Library/MpInitLib/MpLib.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c 
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 42011d6231..0b7073fd02 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -834,14 +834,15 @@ FillExchangeInfoData (
   );
 
 ExchangeInfo->ModeTransitionMemory = (UINT32)CpuMpData->WakeupBufferHigh;
-ExchangeInfo->ModeHighMemory = (UINT32)CpuMpData->WakeupBufferHigh +
-   (UINT32)ExchangeInfo->ModeOffset -
-   
(UINT32)CpuMpData->AddressMap.ModeTransitionOffset;
-ExchangeInfo->ModeHighSegment = (UINT16)ExchangeInfo->CodeSegment;
   } else {
 ExchangeInfo->ModeTransitionMemory = (UINT32)
   (ExchangeInfo->BufferStart + CpuMpData->AddressMap.ModeTransitionOffset);
   }
+
+  ExchangeInfo->ModeHighMemory = ExchangeInfo->ModeTransitionMemory +
+ (UINT32)ExchangeInfo->ModeOffset -
+ (UINT32)CpuMpData->AddressMap.ModeTransitionOffset;
+  ExchangeInfo->ModeHighSegment = (UINT16)ExchangeInfo->CodeSegment;
 }
 
 /**
-- 
2.15.1.windows.2

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[edk2] [PATCH] UefiCpuPkg/MpInitLib: Make sure AP uses correct StartupApSignal

[Ruiyu Ni]

From: Star Zeng 

Every processor's StartupApSignal is initialized in
MpInitLibInitialize() before calling CollectProcessorCount().
When SortApicId() is called from CollectProcessorCount(), AP Index
is re-assigned by APIC ID. But SortApicId() forgets to set the
correct StartupApSignal when sorting the AP.

The patch fixes this issue.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng 
Signed-off-by: Ruiyu Ni 
Cc: Star Zeng 
Cc: Chasel Chiu 
---
 UefiCpuPkg/Library/MpInitLib/MpLib.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c 
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 42011d6231..742f0c1f5e 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -330,6 +330,7 @@ SortApicId (
   CPU_INFO_IN_HOB   CpuInfo;
   UINT32ApCount;
   CPU_INFO_IN_HOB   *CpuInfoInHob;
+  volatile UINT32   *StartupApSignal;
 
   ApCount = CpuMpData->CpuCount - 1;
   CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;
@@ -354,6 +355,14 @@ SortApicId (
   sizeof (CPU_INFO_IN_HOB)
   );
 CopyMem ([Index1], , sizeof (CPU_INFO_IN_HOB));
+
+//
+// Also exchange the StartupApSignal.
+//
+StartupApSignal = CpuMpData->CpuData[Index3].StartupApSignal;
+CpuMpData->CpuData[Index3].StartupApSignal =
+  CpuMpData->CpuData[Index1].StartupApSignal;
+CpuMpData->CpuData[Index1].StartupApSignal = StartupApSignal;
   }
 }
 
-- 
2.15.1.windows.2

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[edk2] [PATCH] UefiCpuPkg/MpInitLib: fix AP init issue in 64-bit PEI

[Jian J Wang]

This issue is introduced by a patch at

   f32bfe6d061420a15bac6083063d227c567e6388

The above patch miss the case of 64-bit PEI, which will link
X64/MpFuncs.nasm instead of Ia32/MpFuncs.nasm. For X64/MpFuncs.nasm,
ExchangeInfo->ModeHighMemory should be always initialized no matter
if separate wakeup buffer is allocated or not. Ia32/MpFuncs.nasm will
not need ModeHighMemory during AP init. So the changes made in this
patch should not affect the functionality of it.

Cc: Ruiyu Ni 
Cc: Eric Dong 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang 
---
 UefiCpuPkg/Library/MpInitLib/MpLib.c | 15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c 
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 42011d6231..7c4b9deaee 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -834,14 +834,15 @@ FillExchangeInfoData (
   );
 
 ExchangeInfo->ModeTransitionMemory = (UINT32)CpuMpData->WakeupBufferHigh;
-ExchangeInfo->ModeHighMemory = (UINT32)CpuMpData->WakeupBufferHigh +
-   (UINT32)ExchangeInfo->ModeOffset -
-   
(UINT32)CpuMpData->AddressMap.ModeTransitionOffset;
-ExchangeInfo->ModeHighSegment = (UINT16)ExchangeInfo->CodeSegment;
   } else {
 ExchangeInfo->ModeTransitionMemory = (UINT32)
   (ExchangeInfo->BufferStart + CpuMpData->AddressMap.ModeTransitionOffset);
   }
+
+  ExchangeInfo->ModeHighMemory = ExchangeInfo->ModeTransitionMemory +
+ (UINT32)ExchangeInfo->ModeOffset -
+ (UINT32)CpuMpData->AddressMap.ModeTransitionOffset;
+  ExchangeInfo->ModeHighSegment = (UINT16)ExchangeInfo->CodeSegment;
 }
 
 /**
@@ -918,9 +919,9 @@ AllocateResetVector (
 CpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN)
 (CpuMpData->WakeupBuffer + 
CpuMpData->AddressMap.RendezvousFunnelSize);
 CpuMpData->WakeupBufferHigh  = GetModeTransitionBuffer (
-CpuMpData->AddressMap.RendezvousFunnelSize 
-
-CpuMpData->AddressMap.ModeTransitionOffset
-);
+  CpuMpData->AddressMap.RendezvousFunnelSize -
+  CpuMpData->AddressMap.ModeTransitionOffset
+  );
   }
   BackupAndPrepareWakeupBuffer (CpuMpData);
 }
-- 
2.15.1.windows.2

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Re: [edk2] [PATCH] SecurityPkg: Tcg2Smm: Enable TPM2.0 interrupt support

[Zhang, Chao B]

Jiewen: 
  Thank you for the comment.
  I agree with 1〜3. Will update patch accordingly 
  For 4. We verified short format Possible Interrupt with 
PcdTpm2PossibleIrqNumBuf set to
   {(UINT32) 0x01}Short formed resource buffer 
   {(UINT32)0x01, ~ (UINT32)0x0A}   Short formed resource buffer
   {UINT32)0x01 ~  (UINT32) 0x0B}long formed resource buffer
   { UINT32)0x01 ~  (UINT32) 0x0F}long formed resource buffer
   All of them can be patched successfully.

-Original Message-
From: Yao, Jiewen 
Sent: Thursday, January 25, 2018 2:39 PM
To: Zhang, Chao B ; edk2-devel@lists.01.org
Cc: Zhang, Chao B ; Ronald Aigner 

Subject: RE: [edk2] [PATCH] SecurityPkg: Tcg2Smm: Enable TPM2.0 interrupt 
support

Thanks Chao.
In general this patch is good.

Some minor suggestion for your consideration:
1) Can we rename PcdTpm2IrqNum to PcdTpm2CurrentIrqNum ? (To match 
PcdTpm2PossibleIrqNumBuf)

2) I suggest we output debug message if below condition is NOT satisfied. As 
such people know what happens.
Silence failure is not the best way.

> +if (PossibleIrqNumBufSize <= MAX_PRS_INT_BUF_SIZE &&
> (PossibleIrqNumBufSize % sizeof(UINT32)) == 0) {
> +  Status = UpdatePossibleResource(Table, PossibleIrqNumBuf,
> PossibleIrqNumBufSize);
> +  DEBUG ((
> +DEBUG_INFO,
> +"UpdatePossibleResource status - %x\n",
> +Status
> +));
> +  }

3) Do we use UINT32 to IrqNumber? If so, you can use {(UINT32)0x12} for that.

> +  gEfiSecurityPkgTokenSpaceGuid.PcdTpm2PossibleIrqNumBuf|{0x12, 0x00,
> 0x00, 0x00}|VOID*|0x0001001D

4) Would you please clarify what test has been done for the PCD patch?
Since you support flexible format (short v.s. long), please make sure all path 
is covered.



Thank you
Yao Jiewen


> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of 
> Zhang, Chao B
> Sent: Thursday, January 25, 2018 2:25 PM
> To: edk2-devel@lists.01.org
> Cc: Yao, Jiewen ; Zhang, Chao B 
> ; Ronald Aigner 
> Subject: [edk2] [PATCH] SecurityPkg: Tcg2Smm: Enable TPM2.0 interrupt 
> support
> 
> 1. Expose _CRS, _SRS, _PRS control method to support TPM interrupt 2. 
> Provide 2 PCDs to configure _CRS and _PRS returned data
> 
> Cc: Yao Jiewen 
> Cc: Ronald Aigner 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Chao Zhang 
> ---
>  SecurityPkg/SecurityPkg.dec |  12 +-
>  SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.c   | 268
> +++-
>  SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.h   |  24 +++-
>  SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf |   5 +-
>  SecurityPkg/Tcg/Tcg2Smm/Tpm.asl |  96 ++---
>  5 files changed, 383 insertions(+), 22 deletions(-)
> 
> diff --git a/SecurityPkg/SecurityPkg.dec b/SecurityPkg/SecurityPkg.dec 
> index 50dbe95..a2b3191 100644
> --- a/SecurityPkg/SecurityPkg.dec
> +++ b/SecurityPkg/SecurityPkg.dec
> @@ -5,7 +5,7 @@
>  #  It also provides the definitions(including PPIs/PROTOCOLs/GUIDs 
> and library
> classes)
>  #  and libraries instances, which are used for those features.
>  #
> -# Copyright (c) 2009 - 2017, Intel Corporation. All rights 
> reserved.
> +# Copyright (c) 2009 - 2018, Intel Corporation. All rights 
> +reserved.
>  # (C) Copyright 2015 Hewlett Packard Enterprise Development LP   
> # Copyright (c) 2017, Microsoft Corporation.  All rights reserved. 
>   # This program and the accompanying materials are licensed and 
> made available under @@ -450,6 +450,16 @@
># @Prompt Initial setting of TCG2 Persistent Firmware Management 
> Flags
> 
> gEfiSecurityPkgTokenSpaceGuid.PcdTcg2PhysicalPresenceFlags|0x300E2|UIN
> T3
> 2|0x0001001B
> 
> +  ## Indicate current TPM2 Interrupt Number reported by _CRS control
> method.
> +  # TPM2 Interrupt feature is disabled If the pcd is set to 0.  # 
> + @Prompt Current TPM2 Interrupt Number
> +
> gEfiSecurityPkgTokenSpaceGuid.PcdTpm2IrqNum|0x12|UINT32|0x0001001C
> +
> +  ## Indicate platform possible TPM2 Interrupt Number reported by 
> + _PRS
> control method.
> +  # Possible TPM2 Interrupt Number Buffer will not be reported if 
> + TPM2
> Interrupt feature is disabled.
> +  # @Prompt Possible TPM2 Interrupt Number buffer  
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2PossibleIrqNumBuf|{0x12, 0x00,
> 0x00, 0x00}|VOID*|0x0001001D
> +
>  [PcdsDynamic, PcdsDynamicEx]
> 
>## This PCD indicates Hash mask for TPM 2.0. Bit definition 
> strictly follows TCG Algorithm Registry. diff --git 
> a/SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.c
> b/SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.c
> index 5a1fd3e..5ad042e 100644
> --- a/SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.c
> +++ b/SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.c
> @@ -9,7 +9,7 @@
> 
>PhysicalPresenceCallback() and 

Re: [edk2] [PATCH] UefiCpuPkg/CpuExceptionHandler: Init serial port before context dump

[Yao, Jiewen]

Reviewed-by: jiewen@intel.com

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Ruiyu
> Ni
> Sent: Thursday, January 25, 2018 1:10 PM
> To: edk2-devel@lists.01.org
> Cc: Yao, Jiewen 
> Subject: [edk2] [PATCH] UefiCpuPkg/CpuExceptionHandler: Init serial port
> before context dump
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ruiyu Ni 
> Cc: Jiewen Yao 
> ---
>  UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c | 6
> +-
>  UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c| 6
> +-
>  2 files changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
> index 0facfde5dd..1a382e88fb 100644
> --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
> +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
> @@ -1,7 +1,7 @@
>  /** @file
>CPU Exception Library provides PEI/DXE/SMM CPU common exception
> handler.
> 
> -Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
>  This program and the accompanying materials are licensed and made available
> under
>  the terms and conditions of the BSD License that accompanies this 
> distribution.
>  The full text of the license may be found at
> @@ -99,6 +99,10 @@ CommonExceptionHandlerWorker (
>CpuPause ();
>  }
>  //
> +// Initialize the serial port before dumping.
> +//
> +SerialPortInitialize ();
> +//
>  // Display ExceptionType, CPU information and Image information
>  //
>  DumpImageAndCpuContent (ExceptionType, SystemContext);
> diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
> index 13bf20d143..68b159e0ab 100644
> --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
> +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
> @@ -1,7 +1,7 @@
>  /** @file
>CPU exception handler library implemenation for SEC/PEIM modules.
> 
> -Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
>  This program and the accompanying materials are licensed and made available
> under
>  the terms and conditions of the BSD License that accompanies this 
> distribution.
>  The full text of the license may be found at
> @@ -30,6 +30,10 @@ CommonExceptionHandler (
>IN EFI_SYSTEM_CONTEXT   SystemContext
>)
>  {
> +  //
> +  // Initialize the serial port before dumping.
> +  //
> +  SerialPortInitialize ();
>//
>// Display ExceptionType, CPU information and Image information
>//
> --
> 2.15.1.windows.2
> 
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[edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Disable xDCI.

[zwei4]

Disable xDCI and assign USB3 Port 0 (OTG port) to xHCI.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: zwei4 
---
 .../Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi   | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
index f45d47a82..c6e9410ad 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
+++ 
b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/SouthClusterConfig.vfi
@@ -2411,8 +2411,8 @@ form formid = USB_OPTIONS_FORM_ID,
   oneof varid   = Setup.ScUsbOtg,
 prompt  = STRING_TOKEN(STR_USB_XDCI_PROMPT),
 help= STRING_TOKEN(STR_USB_XDCI_HELP),
-option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;
-option text = STRING_TOKEN(STR_PCI_MODE_STRING), value = 1, flags = 
DEFAULT | MANUFACTURING | RESET_REQUIRED;
+option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | 
MANUFACTURING | RESET_REQUIRED;
+option text = STRING_TOKEN(STR_PCI_MODE_STRING), value = 1, flags = 
RESET_REQUIRED;
 //  option text = STRING_TOKEN(STR_ACPI_MODE_STRING), value = 2, flags = 
RESET_REQUIRED;
   endoneof;
 
-- 
2.14.1.windows.1

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Re: [edk2] [PATCH] SecurityPkg:Tpm2DeviceLibDTpm: Support TPM command cancel

[Yao, Jiewen]

Reviewed-by: jiewen@intel.com

> -Original Message-
> From: Zhang, Chao B
> Sent: Thursday, January 25, 2018 12:54 PM
> To: edk2-devel@lists.01.org
> Cc: Yao, Jiewen ; Chinnusamy, Rajkumar K
> ; Zhang, Chao B 
> Subject: [PATCH] SecurityPkg:Tpm2DeviceLibDTpm: Support TPM command
> cancel
> 
> Support TPM Command cancel if executing command timeouts. Cancel could
> happen in long running command case
> 
> Cc: Yao Jiewen 
> Cc: Chinnusamy Rajkumar K 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Chao Zhang 
> ---
>  MdePkg/Include/IndustryStandard/TpmTis.h|  8 +--
>  SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c | 24
> +---
>  SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c | 30
> +
>  3 files changed, 53 insertions(+), 9 deletions(-)
> 
> diff --git a/MdePkg/Include/IndustryStandard/TpmTis.h
> b/MdePkg/Include/IndustryStandard/TpmTis.h
> index 519fa79..f25ca25 100644
> --- a/MdePkg/Include/IndustryStandard/TpmTis.h
> +++ b/MdePkg/Include/IndustryStandard/TpmTis.h
> @@ -2,7 +2,7 @@
>TPM Interface Specification definition.
>It covers both TPM1.2 and TPM2.0.
> 
> -Copyright (c) 2016, Intel Corporation. All rights reserved.
> +Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
>  This program and the accompanying materials
>  are licensed and made available under the terms and conditions of the BSD
> License
>  which accompanies this distribution.  The full text of the license may be 
> found
> at
> @@ -143,6 +143,10 @@ typedef TIS_PC_REGISTERS
> *TIS_PC_REGISTERS_PTR;
>  #define TIS_PC_ACC_ESTABLISHBIT0
> 
>  ///
> +/// Write a 1 to this bit to notify TPM to cancel currently executing command
> +///
> +#define TIS_PC_STS_CANCEL   BIT24
> +///
>  /// This field indicates that STS_DATA and STS_EXPECT are valid
>  ///
>  #define TIS_PC_STS_VALIDBIT7
> @@ -180,4 +184,4 @@ typedef TIS_PC_REGISTERS  *TIS_PC_REGISTERS_PTR;
>  #define TIS_TIMEOUT_C   (750  * 1000)  // 750ms
>  #define TIS_TIMEOUT_D   (750  * 1000)  // 750ms
> 
> -#endif
> \ No newline at end of file
> +#endif
> diff --git a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c
> b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c
> index ddd4bd0..d9df264 100644
> --- a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c
> +++ b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c
> @@ -1,7 +1,7 @@
>  /** @file
>PTP (Platform TPM Profile) CRB (Command Response Buffer) interface used
> by dTPM2.0 library.
> 
> -Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
> +Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
>  This program and the accompanying materials
>  are licensed and made available under the terms and conditions of the BSD
> License
>  which accompanies this distribution.  The full text of the license may be 
> found
> at
> @@ -240,8 +240,26 @@ PtpCrbTpmCommand (
>   PTP_TIMEOUT_MAX
>   );
>if (EFI_ERROR (Status)) {
> -Status = EFI_DEVICE_ERROR;
> -goto Exit;
> +//
> +// Command Completion check timeout. Cancel the currently executing
> command by writing TPM_CRB_CTRL_CANCEL,
> +// Expect TPM_RC_CANCELLED or successfully completed response.
> +//
> +MmioWrite32((UINTN)>CrbControlCancel,
> PTP_CRB_CONTROL_CANCEL);
> +Status = PtpCrbWaitRegisterBits (
> +   >CrbControlStart,
> +   0,
> +   PTP_CRB_CONTROL_START,
> +   PTP_TIMEOUT_B
> +   );
> +MmioWrite32((UINTN)>CrbControlCancel, 0);
> +
> +if (EFI_ERROR(Status)) {
> +  //
> +  // Still in Command Execution state. Try to goIdle, the behavior is
> agnostic.
> +  //
> +  Status = EFI_DEVICE_ERROR;
> +  goto Exit;
> +}
>}
> 
>//
> diff --git a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c
> b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c
> index 6cd7030..0889162 100644
> --- a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c
> +++ b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c
> @@ -1,7 +1,7 @@
>  /** @file
>TIS (TPM Interface Specification) functions used by dTPM2.0 library.
> 
> -Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
> +Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
>  (C) Copyright 2015 Hewlett Packard Enterprise Development LP
>  This program and the accompanying materials
>  are licensed and made available under the terms and conditions of the BSD
> License
> @@ -295,10 +295,32 @@ Tpm2TisTpmCommand (
>   TIS_TIMEOUT_MAX
>   );
>if (EFI_ERROR (Status)) {
> -DEBUG ((DEBUG_ERROR, "Wait for Tpm2 response data time out!!\n"));
> -Status = EFI_DEVICE_ERROR;
> -goto Exit;
> +//
> +// 

Re: [edk2] [PATCH] SecurityPkg: Tcg2Smm: Enable TPM2.0 interrupt support

[Yao, Jiewen]

Thanks Chao.
In general this patch is good.

Some minor suggestion for your consideration:
1) Can we rename PcdTpm2IrqNum to PcdTpm2CurrentIrqNum ? (To match 
PcdTpm2PossibleIrqNumBuf)

2) I suggest we output debug message if below condition is NOT satisfied. As 
such people know what happens.
Silence failure is not the best way.

> +if (PossibleIrqNumBufSize <= MAX_PRS_INT_BUF_SIZE &&
> (PossibleIrqNumBufSize % sizeof(UINT32)) == 0) {
> +  Status = UpdatePossibleResource(Table, PossibleIrqNumBuf,
> PossibleIrqNumBufSize);
> +  DEBUG ((
> +DEBUG_INFO,
> +"UpdatePossibleResource status - %x\n",
> +Status
> +));
> +  }

3) Do we use UINT32 to IrqNumber? If so, you can use {(UINT32)0x12} for that.

> +  gEfiSecurityPkgTokenSpaceGuid.PcdTpm2PossibleIrqNumBuf|{0x12, 0x00,
> 0x00, 0x00}|VOID*|0x0001001D

4) Would you please clarify what test has been done for the PCD patch?
Since you support flexible format (short v.s. long), please make sure all path 
is covered.



Thank you
Yao Jiewen


> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Zhang,
> Chao B
> Sent: Thursday, January 25, 2018 2:25 PM
> To: edk2-devel@lists.01.org
> Cc: Yao, Jiewen ; Zhang, Chao B
> ; Ronald Aigner 
> Subject: [edk2] [PATCH] SecurityPkg: Tcg2Smm: Enable TPM2.0 interrupt
> support
> 
> 1. Expose _CRS, _SRS, _PRS control method to support TPM interrupt
> 2. Provide 2 PCDs to configure _CRS and _PRS returned data
> 
> Cc: Yao Jiewen 
> Cc: Ronald Aigner 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Chao Zhang 
> ---
>  SecurityPkg/SecurityPkg.dec |  12 +-
>  SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.c   | 268
> +++-
>  SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.h   |  24 +++-
>  SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf |   5 +-
>  SecurityPkg/Tcg/Tcg2Smm/Tpm.asl |  96 ++---
>  5 files changed, 383 insertions(+), 22 deletions(-)
> 
> diff --git a/SecurityPkg/SecurityPkg.dec b/SecurityPkg/SecurityPkg.dec
> index 50dbe95..a2b3191 100644
> --- a/SecurityPkg/SecurityPkg.dec
> +++ b/SecurityPkg/SecurityPkg.dec
> @@ -5,7 +5,7 @@
>  #  It also provides the definitions(including PPIs/PROTOCOLs/GUIDs and 
> library
> classes)
>  #  and libraries instances, which are used for those features.
>  #
> -# Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
> +# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
>  # (C) Copyright 2015 Hewlett Packard Enterprise Development LP 
>  # Copyright (c) 2017, Microsoft Corporation.  All rights reserved. 
>  # This program and the accompanying materials are licensed and made
> available under
> @@ -450,6 +450,16 @@
># @Prompt Initial setting of TCG2 Persistent Firmware Management Flags
> 
> gEfiSecurityPkgTokenSpaceGuid.PcdTcg2PhysicalPresenceFlags|0x300E2|UINT3
> 2|0x0001001B
> 
> +  ## Indicate current TPM2 Interrupt Number reported by _CRS control
> method.
> +  # TPM2 Interrupt feature is disabled If the pcd is set to 0.
> +  # @Prompt Current TPM2 Interrupt Number
> +
> gEfiSecurityPkgTokenSpaceGuid.PcdTpm2IrqNum|0x12|UINT32|0x0001001C
> +
> +  ## Indicate platform possible TPM2 Interrupt Number reported by _PRS
> control method.
> +  # Possible TPM2 Interrupt Number Buffer will not be reported if TPM2
> Interrupt feature is disabled.
> +  # @Prompt Possible TPM2 Interrupt Number buffer
> +  gEfiSecurityPkgTokenSpaceGuid.PcdTpm2PossibleIrqNumBuf|{0x12, 0x00,
> 0x00, 0x00}|VOID*|0x0001001D
> +
>  [PcdsDynamic, PcdsDynamicEx]
> 
>## This PCD indicates Hash mask for TPM 2.0. Bit definition strictly 
> follows
> TCG Algorithm Registry.
> diff --git a/SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.c
> b/SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.c
> index 5a1fd3e..5ad042e 100644
> --- a/SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.c
> +++ b/SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.c
> @@ -9,7 +9,7 @@
> 
>PhysicalPresenceCallback() and MemoryClearCallback() will receive untrusted
> input and do some check.
> 
> -Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
>  This program and the accompanying materials
>  are licensed and made available under the terms and conditions of the BSD
> License
>  which accompanies this distribution.  The full text of the license may be 
> found
> at
> @@ -304,6 +304,251 @@ UpdatePPVersion (
>  }
> 
>  /**
> +  Patch interrupt resources returned by TPM _PRS. ResourceTemplate to patch
> is determined by input
> +  interrupt buffer size. BufferSize, PkgLength and interrupt descirptor in
> ByteList need to be patched
> +
> +  @param[in, out] TableThe TPM item in ACPI table.
> +  @param[in]  IrqBufferInput new IRQ buffer.
> +  @param[in]  IrqBuffserSize   Input new IRQ 

[edk2] [PATCH] SecurityPkg: Tcg2Smm: Enable TPM2.0 interrupt support

[Zhang, Chao B]

1. Expose _CRS, _SRS, _PRS control method to support TPM interrupt
2. Provide 2 PCDs to configure _CRS and _PRS returned data

Cc: Yao Jiewen 
Cc: Ronald Aigner 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chao Zhang 
---
 SecurityPkg/SecurityPkg.dec |  12 +-
 SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.c   | 268 +++-
 SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.h   |  24 +++-
 SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf |   5 +-
 SecurityPkg/Tcg/Tcg2Smm/Tpm.asl |  96 ++---
 5 files changed, 383 insertions(+), 22 deletions(-)

diff --git a/SecurityPkg/SecurityPkg.dec b/SecurityPkg/SecurityPkg.dec
index 50dbe95..a2b3191 100644
--- a/SecurityPkg/SecurityPkg.dec
+++ b/SecurityPkg/SecurityPkg.dec
@@ -5,7 +5,7 @@
 #  It also provides the definitions(including PPIs/PROTOCOLs/GUIDs and library 
classes)
 #  and libraries instances, which are used for those features.
 #
-# Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
 # (C) Copyright 2015 Hewlett Packard Enterprise Development LP 
 # Copyright (c) 2017, Microsoft Corporation.  All rights reserved. 
 # This program and the accompanying materials are licensed and made available 
under
@@ -450,6 +450,16 @@
   # @Prompt Initial setting of TCG2 Persistent Firmware Management Flags
   
gEfiSecurityPkgTokenSpaceGuid.PcdTcg2PhysicalPresenceFlags|0x300E2|UINT32|0x0001001B
 
+  ## Indicate current TPM2 Interrupt Number reported by _CRS control 
method.
+  # TPM2 Interrupt feature is disabled If the pcd is set to 0.
+  # @Prompt Current TPM2 Interrupt Number
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpm2IrqNum|0x12|UINT32|0x0001001C
+
+  ## Indicate platform possible TPM2 Interrupt Number reported by _PRS control 
method.
+  # Possible TPM2 Interrupt Number Buffer will not be reported if TPM2 
Interrupt feature is disabled.
+  # @Prompt Possible TPM2 Interrupt Number buffer
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpm2PossibleIrqNumBuf|{0x12, 0x00, 0x00, 
0x00}|VOID*|0x0001001D
+
 [PcdsDynamic, PcdsDynamicEx]
 
   ## This PCD indicates Hash mask for TPM 2.0. Bit definition strictly follows 
TCG Algorithm Registry.
diff --git a/SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.c 
b/SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.c
index 5a1fd3e..5ad042e 100644
--- a/SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.c
+++ b/SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.c
@@ -9,7 +9,7 @@
 
   PhysicalPresenceCallback() and MemoryClearCallback() will receive untrusted 
input and do some check.
 
-Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
 This program and the accompanying materials 
 are licensed and made available under the terms and conditions of the BSD 
License 
 which accompanies this distribution.  The full text of the license may be 
found at 
@@ -304,6 +304,251 @@ UpdatePPVersion (
 }
 
 /**
+  Patch interrupt resources returned by TPM _PRS. ResourceTemplate to patch is 
determined by input
+  interrupt buffer size. BufferSize, PkgLength and interrupt descirptor in 
ByteList need to be patched
+
+  @param[in, out] TableThe TPM item in ACPI table.
+  @param[in]  IrqBufferInput new IRQ buffer.
+  @param[in]  IrqBuffserSize   Input new IRQ buffer size.
+
+  @return  patch status.
+
+**/
+EFI_STATUS
+UpdatePossibleResource (
+  EFI_ACPI_DESCRIPTION_HEADER*Table,
+  UINT32 *IrqBuffer,
+  UINT32 IrqBuffserSize
+  )
+{
+  UINT8   *DataPtr;
+  UINT8   *DataEndPtr;
+  UINT32  NewPkgLength;
+  UINT32  OrignalPkgLength;
+
+  NewPkgLength = 0;
+  OrignalPkgLength = 0;
+  DataEndPtr   = NULL;
+
+  //
+  // Follow ACPI spec
+  //   6.4.3   Extend Interrupt Descriptor.
+  //   19.3.3 ASL Resource Template
+  //   20  AML specification
+  // to patch TPM ACPI object _PRS returned ResourceTemplate() containing 2 
resource descriptors and an auto appended End Tag
+  //
+  //  AML data is organized by following rule.
+  //  Code need to patch BufferSize and PkgLength and interrupt descirptor in 
ByteList
+  //
+  // =  Buffer 
+  //   DefBuffer := BufferOp PkgLength BufferSize ByteList
+  //BufferOp := 0x11
+  //
+  // ==PkgLength==
+  //  PkgLength := PkgLeadByte |
+  //   |
+  //   |
+  //  
+  //
+  //   PkgLeadByte := 
+  //   
+  //   
+  //
+  //==BufferSize==
+  //BufferSize := Integar
+  //   Integar := ByteConst|WordConst|DwordConst
+  //
+  //   ByteConst := BytePrefix ByteData
+  //
+  

Re: [edk2] [PATCH edk2-platforms v1 01/14] Hisilicon/D05: Add PPTT support

[Huangming (Mark)]

On 2018/1/24 5:29, Jeremy Linton wrote:
> Hi,
> 
> 
> On 01/18/2018 09:01 AM, Ming Huang wrote:
>> From: Jason Zhang 
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Jason Zhang 
>> Signed-off-by: Ming Huang 
>> Signed-off-by: Heyi Guo 
>> ---
>>   Platform/Hisilicon/D05/D05.dsc  |   1 +
>>   Platform/Hisilicon/D05/D05.fdf  |   1 +
>>   Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h |  27 ++
>>   Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc  |  31 +-
>>   Silicon/Hisilicon/Hi1616/Pptt/Pptt.c| 447 
>> 
>>   Silicon/Hisilicon/Hi1616/Pptt/Pptt.h| 142 +++
>>   Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf  |  55 +++
>>   7 files changed, 677 insertions(+), 27 deletions(-)
>>
>> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
>> index 77a89fd..710339c 100644
>> --- a/Platform/Hisilicon/D05/D05.dsc
>> +++ b/Platform/Hisilicon/D05/D05.dsc
>> @@ -506,6 +506,7 @@
>> MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
>>   Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
>> +  Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
>> Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
>>   #
>> diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
>> index 78ab0c8..97de4d2 100644
>> --- a/Platform/Hisilicon/D05/D05.fdf
>> +++ b/Platform/Hisilicon/D05/D05.fdf
>> @@ -241,6 +241,7 @@ READ_LOCK_STATUS   = TRUE
>> INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
>>   INF RuleOverride=ACPITABLE 
>> Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
>> +  INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
>> INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
>>   #
>> diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h 
>> b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
>> index 808219a..f1927e8 100644
>> --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
>> +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
>> @@ -19,6 +19,7 @@
>> #ifndef _HI1610_PLATFORM_H_
>>   #define _HI1610_PLATFORM_H_
>> +#include 
>> //
>>   // ACPI table information used to initialize tables.
>> @@ -44,5 +45,31 @@
>> }
>> #define HI1616_WATCHDOG_COUNT  2
>> +#define HI1616_GIC_STRUCTURE_COUNT  64
>> +
>> +#define HI1616_MPID_TA_BASE  0x1
>> +#define HI1616_MPID_TB_BASE  0x3
>> +#define HI1616_MPID_TA_2_BASE  0x5
>> +#define HI1616_MPID_TB_2_BASE  0x7
>> +
>> +// Differs from Juno, we have another affinity level beyond cluster and core
>> +#define PLATFORM_GET_MPID_TA(ClusterId, CoreId)   (HI1616_MPID_TA_BASE | 
>> ((ClusterId) << 8) | (CoreId))
>> +#define PLATFORM_GET_MPID_TB(ClusterId, CoreId)   (HI1616_MPID_TB_BASE | 
>> ((ClusterId) << 8) | (CoreId))
>> +#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId)   (HI1616_MPID_TA_2_BASE 
>> | ((ClusterId) << 8) | (CoreId))
>> +#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId)   (HI1616_MPID_TB_2_BASE 
>> | ((ClusterId) << 8) | (CoreId))
>> +
>> +//
>> +// Multiple APIC Description Table
>> +//
>> +#pragma pack (1)
>> +
>> +typedef struct {
>> +  EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
>> +  EFI_ACPI_6_1_GIC_STRUCTURE
>> GicInterfaces[HI1616_GIC_STRUCTURE_COUNT];
>> +  EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
>> +  EFI_ACPI_6_1_GIC_ITS_STRUCTUREGicITS[8];
>> +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
>> +
>> +#pragma pack ()
>> #endif
>> diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc 
>> b/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
>> index 169ee72..33dca03 100644
>> --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
>> +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
>> @@ -1,9 +1,9 @@
>>   /** @file
>>   *  Multiple APIC Description Table (MADT)
>>   *
>> -*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
>> -*  Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved.
>> -*  Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved.
>> +*  Copyright (c) 2012 - 2018, ARM Limited. All rights reserved.
>> +*  Copyright (c) 2015 - 2018, Hisilicon Limited. All rights reserved.
>> +*  Copyright (c) 2015 - 2018, Linaro Limited. All rights reserved.
>>   *
>>   *  This program and the accompanying materials
>>   *
>> @@ -19,34 +19,11 @@
>>   *
>>   **/
>>   -
>> -#include 
>> +#include "Hi1616Platform.h"
>>   #include 
>>   #include 
>>   #include 
>>   #include 
>> -#include "Hi1616Platform.h"
>> -
>> -// Differs from Juno, we have another affinity level beyond cluster and core
>> -// 0x2 is only for socket 0
>> -#define 

Re: [edk2] [patch 0/3] Remove the useless pref codes

[Bi, Dandan]

Hi Star,

I am not sure. Since these definitions are still used in other packages such as 
Intelframeworkmodulepkg. If we want to remove them, we must clean up all the 
old perf related codes in Edk2 code base to avoid build block issues.


Thanks,
Dandan
-Original Message-
From: Zeng, Star 
Sent: Thursday, January 25, 2018 12:59 PM
To: Bi, Dandan ; edk2-devel@lists.01.org
Cc: Ni, Ruiyu ; Laszlo Ersek ; Dong, 
Eric ; Gao, Liming ; Zeng, Star 

Subject: RE: [edk2] [patch 0/3] Remove the useless pref codes

Could we also remove the related definitions in 
MdeModulePkg\Include\Guid\Performance.h?

//
// The data structure for performance data in ACPI memory.
//
#define PERFORMANCE_SIGNATURE   SIGNATURE_32 ('P', 'e', 'r', 'f')
#define PERF_TOKEN_SIZE 28
#define PERF_TOKEN_LENGTH   (PERF_TOKEN_SIZE - 1)
#define PERF_PEI_ENTRY_MAX_NUM  50
#define PERF_DATA_MAX_LENGTH0x4000

typedef struct {
  CHAR8   Token[PERF_TOKEN_SIZE];
  UINT32  Duration;
} PERF_DATA;

typedef struct {
  UINT64BootToOs;
  UINT64S3Resume;
  UINT32S3EntryNum;
  PERF_DATA S3Entry[PERF_PEI_ENTRY_MAX_NUM];
  UINT64CpuFreq;
  UINT64BDSRaw;
  UINT32Count;
  UINT32Signiture;
} PERF_HEADER;


Thanks,
Star
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Dandan Bi
Sent: Wednesday, January 24, 2018 4:02 PM
To: edk2-devel@lists.01.org
Cc: Ni, Ruiyu ; Zeng, Star ; Laszlo 
Ersek ; Dong, Eric ; Gao, Liming 

Subject: [edk2] [patch 0/3] Remove the useless pref codes

Our new performance infrastructure can support to dump performance date form 
ACPI table in OS. So we can remove the old pref code to write performance data 
to OS.

Cc: Eric Dong 
Cc: Laszlo Ersek 
Cc: Liming Gao 
Cc: Ruiyu Ni 
Cc: Star Zeng 
Dandan Bi (3):
  UefiCpuPkg/S3Resume: Remove useless pref code
  MdeModulePkg/BdsDxe: Remove useless Pref Code
  MdeModulePkg/UefiBootManagerLib: Remove the useless pref codes

 MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c   |  30 +-
 .../Library/UefiBootManagerLib/BmPerformance.c | 317 -
 .../Library/UefiBootManagerLib/InternalBm.h|   1 -
 .../UefiBootManagerLib/UefiBootManagerLib.inf  |   4 +-
 MdeModulePkg/Universal/BdsDxe/Bds.h|   3 +-
 MdeModulePkg/Universal/BdsDxe/BdsDxe.inf   |   3 +-
 MdeModulePkg/Universal/BdsDxe/BdsEntry.c   |  57 +---
 UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c  | 131 -
 .../Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf   |   3 +-
 9 files changed, 32 insertions(+), 517 deletions(-)  delete mode 100644 
MdeModulePkg/Library/UefiBootManagerLib/BmPerformance.c

--
1.9.5.msysgit.1

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Re: [edk2] [PATCH] CorebootPayloadPkg: Use correct BytesPerScanLine

[You, Benjamin]

Hi Arthur,

Could you please give more details about your case that 
HorizontalResolution * (BitsPerPixel / 8) and pFbInfo->BytesPerScanLine 
don't match?

I did a brief search in Coreboot source and found following comments in 
coreboot-4.6\src\lib\edid.c:

  /* In the case of (e.g.) 24 framebuffer bits per pixel, the convention
   * nowadays seems to be to round it up to the nearest reasonable
   * boundary, because otherwise the byte-packing is hideous.
   
So it appears framebuffer BitsPerPixel will likely be 16 or 32, and the 
following statement in the same file calculates:

  edid->x_resolution = edid->bytes_per_line / (fb_bpp / 8);

which results in bytes_per_line (already rounded up to be 32 or 64 byte 
aligned) matching x_resolution * (fb_bpp / 8).

There are cases that even if panel bits_per_pixel is 24, the framebuffer 
bits_per_pixel is still 32, as shown in 
coreboot-4.6\src\drivers\emulation\qemu\bochs.c:

  edid.panel_bits_per_pixel = 24;
  edid_set_framebuffer_bits_per_pixel(, 32, 0);

It would be good if you could help with more details on how the mismatch 
happened in your case as I may have missed something.

Thanks,

- ben

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
> art...@aheymans.xyz
> Sent: Wednesday, January 24, 2018 6:58 PM
> To: edk2-devel@lists.01.org
> Cc: Arthur Heymans 
> Subject: [edk2] [PATCH] CorebootPayloadPkg: Use correct BytesPerScanLine
> 
> From: Arthur Heymans 
> 
> Fetch BytesPerScanLine from coreboot table to reflect how the actual
> framebuffer is set up instead of guessing it from the horizontal
> resolution.
> 
> This fixes a garbled display when HorizontalResolution * (BitsPerPixel
> / 8) and pFbInfo->BytesPerScanLine don't match.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Arthur Heymans 
> 
> diff --git a/CorebootPayloadPkg/FbGop/FbGop.c
> b/CorebootPayloadPkg/FbGop/FbGop.c
> index 37d6def7f7..6790617033 100644
> --- a/CorebootPayloadPkg/FbGop/FbGop.c
> +++ b/CorebootPayloadPkg/FbGop/FbGop.c
> @@ -822,7 +822,7 @@ FbGopCheckForVbe (
>BitsPerPixel = pFbInfo->BitsPerPixel;
>HorizontalResolution = pFbInfo->HorizontalResolution;
>VerticalResolution   = pFbInfo->VerticalResolution;
> -  BytesPerScanLine = HorizontalResolution * (BitsPerPixel / 8);
> +  BytesPerScanLine = pFbInfo->BytesPerScanLine;
> 
>ModeBuffer = (FB_VIDEO_MODE_DATA *) AllocatePool (
> 
> 
>   ModeNumber * sizeof
> (FB_VIDEO_MODE_DATA)
> --
> 2.16.1
> 
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[edk2] [PATCH] UefiCpuPkg/CpuExceptionHandler: Init serial port before context dump

[Ruiyu Ni]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni 
Cc: Jiewen Yao 
---
 UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c | 6 +-
 UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c| 6 +-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
index 0facfde5dd..1a382e88fb 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
@@ -1,7 +1,7 @@
 /** @file
   CPU Exception Library provides PEI/DXE/SMM CPU common exception handler.
 
-Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
 This program and the accompanying materials are licensed and made available 
under
 the terms and conditions of the BSD License that accompanies this distribution.
 The full text of the license may be found at
@@ -99,6 +99,10 @@ CommonExceptionHandlerWorker (
   CpuPause ();
 }
 //
+// Initialize the serial port before dumping.
+//
+SerialPortInitialize ();
+//
 // Display ExceptionType, CPU information and Image information
 //
 DumpImageAndCpuContent (ExceptionType, SystemContext);
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c 
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
index 13bf20d143..68b159e0ab 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
@@ -1,7 +1,7 @@
 /** @file
   CPU exception handler library implemenation for SEC/PEIM modules.
 
-Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
 This program and the accompanying materials are licensed and made available 
under
 the terms and conditions of the BSD License that accompanies this distribution.
 The full text of the license may be found at
@@ -30,6 +30,10 @@ CommonExceptionHandler (
   IN EFI_SYSTEM_CONTEXT   SystemContext
   )
 {
+  //
+  // Initialize the serial port before dumping.
+  //
+  SerialPortInitialize ();
   //
   // Display ExceptionType, CPU information and Image information
   //
-- 
2.15.1.windows.2

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Re: [edk2] [patch 0/3] Remove the useless pref codes

[Zeng, Star]

Could we also remove the related definitions in 
MdeModulePkg\Include\Guid\Performance.h?

//
// The data structure for performance data in ACPI memory.
//
#define PERFORMANCE_SIGNATURE   SIGNATURE_32 ('P', 'e', 'r', 'f')
#define PERF_TOKEN_SIZE 28
#define PERF_TOKEN_LENGTH   (PERF_TOKEN_SIZE - 1)
#define PERF_PEI_ENTRY_MAX_NUM  50
#define PERF_DATA_MAX_LENGTH0x4000

typedef struct {
  CHAR8   Token[PERF_TOKEN_SIZE];
  UINT32  Duration;
} PERF_DATA;

typedef struct {
  UINT64BootToOs;
  UINT64S3Resume;
  UINT32S3EntryNum;
  PERF_DATA S3Entry[PERF_PEI_ENTRY_MAX_NUM];
  UINT64CpuFreq;
  UINT64BDSRaw;
  UINT32Count;
  UINT32Signiture;
} PERF_HEADER;


Thanks,
Star
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Dandan Bi
Sent: Wednesday, January 24, 2018 4:02 PM
To: edk2-devel@lists.01.org
Cc: Ni, Ruiyu ; Zeng, Star ; Laszlo 
Ersek ; Dong, Eric ; Gao, Liming 

Subject: [edk2] [patch 0/3] Remove the useless pref codes

Our new performance infrastructure can support to dump performance date form 
ACPI table in OS. So we can remove the old pref code to write performance data 
to OS.

Cc: Eric Dong 
Cc: Laszlo Ersek 
Cc: Liming Gao 
Cc: Ruiyu Ni 
Cc: Star Zeng 
Dandan Bi (3):
  UefiCpuPkg/S3Resume: Remove useless pref code
  MdeModulePkg/BdsDxe: Remove useless Pref Code
  MdeModulePkg/UefiBootManagerLib: Remove the useless pref codes

 MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c   |  30 +-
 .../Library/UefiBootManagerLib/BmPerformance.c | 317 -
 .../Library/UefiBootManagerLib/InternalBm.h|   1 -
 .../UefiBootManagerLib/UefiBootManagerLib.inf  |   4 +-
 MdeModulePkg/Universal/BdsDxe/Bds.h|   3 +-
 MdeModulePkg/Universal/BdsDxe/BdsDxe.inf   |   3 +-
 MdeModulePkg/Universal/BdsDxe/BdsEntry.c   |  57 +---
 UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c  | 131 -
 .../Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf   |   3 +-
 9 files changed, 32 insertions(+), 517 deletions(-)  delete mode 100644 
MdeModulePkg/Library/UefiBootManagerLib/BmPerformance.c

--
1.9.5.msysgit.1

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Re: [edk2] [patch] UefiCpuPkg/S3Resume: Add more perf enrty for S3 phase

[Bi, Dandan]

Hi Laszlo,

Thank you for your comments.

Yes. The PERF_INMODULE_START_ID macro is from "ExtendedFirmwarePerformance.h" 
which is added in the new performance infrastructure patches([ mail subject: 
patch 0/8] Update EDKII Performance infrastructure based on ACPI FPDT table). 
That is the dependency I mean.

I will send V2 of this patch and the patch which remove Pref code after "new 
performance infrastructure" patches have been committed . Then I will refine 
the commit message of these two patches, add commit  hash value of "new 
performance infrastructure" patches if I need to reference it. 

Thanks,
Dandan

-Original Message-
From: Laszlo Ersek [mailto:ler...@redhat.com] 
Sent: Wednesday, January 24, 2018 11:45 PM
To: Bi, Dandan ; edk2-devel@lists.01.org
Cc: Dong, Eric ; Gao, Liming 
Subject: Re: [patch] UefiCpuPkg/S3Resume: Add more perf enrty for S3 phase

On 01/24/18 08:59, Dandan Bi wrote:
> Add more perf entry to hook BootScriptDonePpi/EndOfPeiPpi/ 
> EndOfS3Resume.
> 
> Notes: This patch depends on the new performance infrastructure.

Since this statement is going into the commit log, please be more specific 
about the "new performance infrastructure" (TianoCore BZ or commit hashes etc).

Also, how is the dependency established? For example, OVMF uses 
BasePerformanceLibNull; so I think it will see no changes.

Do you mean the PERF_INMODULE_START_ID macro, from 
"ExtendedFirmwarePerformance.h"? Ah, that's not committed yet. In this case, 
please add a reference to the mailing list message (subject and archive URL) 
that adds it.

(Actually, the best solution is to reference the TianoCore BZ, and then add the 
mailing list URL for each patch set submission to the TianoCore BZ.)

> 
> Cc: Eric Dong 
> Cc: Laszlo Ersek 
> Cc: Liming Gao 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Dandan Bi 
> ---
>  UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 15 
> ++-
>  1 file changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c 
> b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
> index b597ac7..d7d2a4d 100644
> --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
> +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
> @@ -2,11 +2,11 @@
>This module produces the EFI_PEI_S3_RESUME2_PPI.
>This module works with StandAloneBootScriptExecutor to S3 resume to OS.
>This module will execute the boot script saved during last boot and after 
> that,
>control is passed to OS waking up handler.
>  
> -  Copyright (c) 2006 - 2017, Intel Corporation. All rights 
> reserved.
> +  Copyright (c) 2006 - 2018, Intel Corporation. All rights 
> + reserved.
>Copyright (c) 2017, AMD Incorporated. All rights reserved.
>  
>This program and the accompanying materials
>are licensed and made available under the terms and conditions
>of the BSD License which accompanies this distribution.  The @@ 
> -21,10 +21,11 @@  #include 
>  
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
>  #include 
>  #include 
> @@ -551,13 +552,17 @@ S3ResumeBootOs (
>PERF_END (NULL, "ScriptExec", NULL, 0);
>  
>//
>// Install BootScriptDonePpi
>//
> +  PERF_START_EX (NULL, "BootScriptDonePpi", NULL, 0, 
> + PERF_INMODULE_START_ID);
> +

My question here is not really specific to this patch, but I guess asking it 
this time is just as good as any other time:

- Why do we pass NULL for Module, rather than gEfiCallerBaseName?

- We already have START and END calls for the performance measurement; why do 
we use different Identifier values for the records added?

(These questions are more for my education than about possible issues in the 
patch.)

Thanks!
Laszlo


>Status = PeiServicesInstallPpi ();
>ASSERT_EFI_ERROR (Status);
>  
> +  PERF_END_EX (NULL, "BootScriptDonePpi", NULL, 0, 
> + PERF_INMODULE_END_ID);
> +
>//
>// Get ACPI Table Address
>//
>Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) 
> (AcpiS3Context->AcpiFacsTable));
>  
> @@ -576,18 +581,26 @@ S3ResumeBootOs (
>}
>  
>//
>// Install EndOfPeiPpi
>//
> +  PERF_START_EX (NULL, "EndOfPeiPpi", NULL, 0, 
> + PERF_INMODULE_START_ID);
> +
>Status = PeiServicesInstallPpi ();
>ASSERT_EFI_ERROR (Status);
>  
> +  PERF_END_EX (NULL, "EndOfPeiPpi", NULL, 0, PERF_INMODULE_END_ID);
> +
>//
>// Signal EndOfS3Resume event.
>//
> +  PERF_START_EX (NULL, "EndOfS3Resume", NULL, 0, 
> + PERF_INMODULE_START_ID);
> +
>SignalEndOfS3Resume ();
>  
> +  PERF_END_EX (NULL, "EndOfS3Resume", NULL, 0, PERF_INMODULE_END_ID);
> +
>//
>// report status code on S3 resume
>//
>REPORT_STATUS_CODE (EFI_PROGRESS_CODE, EFI_SOFTWARE_PEI_MODULE | 
> EFI_SW_PEI_PC_OS_WAKE);
>  
> 

Re: [edk2] [PATCH] Enable RSA2048SHA256 to replace CCG SignedSection solution

[Zhang, Chao B]

Sorry. Made a mistake.  please skip the mail. 

-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Zhang, 
Chao B
Sent: Thursday, January 25, 2018 12:54 PM
To: edk2-devel@lists.01.org
Subject: [edk2] [PATCH] Enable RSA2048SHA256 to replace CCG SignedSection 
solution

---
 KabylakePlatSamplePkg/PlatformPkg.dsc   | 13 +--
 KabylakePlatSamplePkg/PlatformPkg.fdf   | 36 +++--
 KabylakePlatSamplePkg/PlatformPkgConfig.dsc |  2 +-
 3 files changed, 31 insertions(+), 20 deletions(-)

diff --git a/KabylakePlatSamplePkg/PlatformPkg.dsc 
b/KabylakePlatSamplePkg/PlatformPkg.dsc
index fb085b9..125e018 100644
--- a/KabylakePlatSamplePkg/PlatformPkg.dsc
+++ b/KabylakePlatSamplePkg/PlatformPkg.dsc
@@ -1114,6 +1114,8 @@ gPlatformModuleTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
 
   gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x8c
 
+gEfiSecurityPkgTokenSpaceGuid.PcdRsa2048Sha256PublicKeyBuffer|{0x91, 
+0x29, 0xc4, 0xbd, 0xea, 0x6d, 0xda, 0xb3, 0xaa, 0x6f, 0x50, 0x16, 0xfc, 
+0xdb, 0x4b, 0x7e, 0x3c, 0xd6, 0xdc, 0xa4, 0x7a, 0x0e, 0xdd, 0xe6, 0x15, 
+0x8c, 0x73, 0x96, 0xa2, 0xd4, 0xa6, 0x4d}
+
 [PcdsFixedAtBuild.IA32]
 !if gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
   gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
@@ -1445,6 +1447,11 @@ gPlatformModuleTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
 
   
NULL|$(CLIENT_COMMON_PACKAGE)/Library/PeiSignedSectionVerificationLib/PeiSignedSectionVerificationLib.inf
   }
+  
+  MdeModulePkg/Universal/SectionExtractionPei/SectionExtractionPei.inf 
+ {  
+
+ NULL|SecurityPkg\Library\PeiRsa2048Sha256GuidedSectionExtractLib\PeiRs
+ a2048Sha256GuidedSectionExtractLib.inf
+  }
 !endif
 
 !if gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE @@ -1575,7 +1582,8 @@ 
$(CLIENT_COMMON_PACKAGE)/Universal/DebugServicePei/DebugServicePei.inf {
   gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046
 
 !if gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == TRUE
-  
NULL|$(CLIENT_COMMON_PACKAGE)/Library/DxeSignedSectionVerificationLib/DxeSignedSectionVerificationLib.inf
+# 
NULL|$(CLIENT_COMMON_PACKAGE)/Library/DxeSignedSectionVerificationLib/DxeSignedSectionVerificationLib.inf
+  
+ NULL|SecurityPkg\Library\DxeRsa2048Sha256GuidedSectionExtractLib\DxeRs
+ a2048Sha256GuidedSectionExtractLib.inf
 !endif
 !if gPlatformModuleTokenSpaceGuid.PcdDxeCrc32SectionEnable == TRUE
   
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
@@ -1600,7 +1608,8 @@ 
$(CLIENT_COMMON_PACKAGE)/Universal/DebugServicePei/DebugServicePei.inf {
   gEfiMdeModulePkgTokenSpaceGuid.PcdPropertiesTableEnable|FALSE
 
 !if gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == TRUE
-  
NULL|$(CLIENT_COMMON_PACKAGE)/Library/DxeSignedSectionVerificationLib/DxeSignedSectionVerificationLib.inf
+  
#NULL|$(CLIENT_COMMON_PACKAGE)/Library/DxeSignedSectionVerificationLib/DxeSignedSectionVerificationLib.inf
+  
+ NULL|SecurityPkg\Library\DxeRsa2048Sha256GuidedSectionExtractLib\DxeRs
+ a2048Sha256GuidedSectionExtractLib.inf
 !endif
 !if gPlatformModuleTokenSpaceGuid.PcdDxeCrc32SectionEnable == TRUE
   
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
diff --git a/KabylakePlatSamplePkg/PlatformPkg.fdf 
b/KabylakePlatSamplePkg/PlatformPkg.fdf
index d2e8ee3..9d3fa5d 100644
--- a/KabylakePlatSamplePkg/PlatformPkg.fdf
+++ b/KabylakePlatSamplePkg/PlatformPkg.fdf
@@ -406,7 +406,7 @@ INF  
$(PLATFORM_FEATURES_PATH)/Amt/AmtStatusCodePei/AmtStatusCodePei.inf
 
 INF $(PLATFORM_PACKAGE)/BiosInfo/BiosInfo.inf # AdvancedFeaturesContent  !if 
gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == TRUE -INF  
$(PLATFORM_PACKAGE)/Override/$(CLIENT_COMMON_PACKAGE)/Universal/BiosInfoChecker/BiosInfoChecker.inf
+#INF  
+$(PLATFORM_PACKAGE)/Override/$(CLIENT_COMMON_PACKAGE)/Universal/BiosInf
+oChecker/BiosInfoChecker.inf
 !endif
 
 !if gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE @@ -462,12 +462,13 @@ INF 
$(PLATFORM_PACKAGE)/Platform/MsegSmramPei/MsegSmramPei.inf
 INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
 
 !if gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == TRUE -INF 
$(CLIENT_COMMON_PACKAGE)/Universal/SignedSectionPei/SignedSectionPei.inf
-!if gPlatformModuleTokenSpaceGuid.PcdPubKeyHashBinEnable == TRUE -FILE RAW = 
31C17ABE-6071-435e-BAA4-0B8A8C3649F3 {
-$(PLATFORM_PACKAGE)/Tools/ToolScripts/SignFv/pubkeyhash.bin
-  }
-!endif # PcdPubKeyHashBinEnable
+INF 
+MdeModulePkg/Universal/SectionExtractionPei/SectionExtractionPei.inf
+#INF 
+$(CLIENT_COMMON_PACKAGE)/Universal/SignedSectionPei/SignedSectionPei.in
+f #!if gPlatformModuleTokenSpaceGuid.PcdPubKeyHashBinEnable == TRUE 
+#FILE RAW = 31C17ABE-6071-435e-BAA4-0B8A8C3649F3 {
+#$(PLATFORM_PACKAGE)/Tools/ToolScripts/SignFv/pubkeyhash.bin
+#  }
+#!endif # PcdPubKeyHashBinEnable
 !endif # PcdSecureBootEnable
 
 !if gPlatformModuleTokenSpaceGuid.PcdTpmEnable == 

Re: [edk2] [patch 3/3] MdeModulePkg/UefiBootManagerLib: Remove useless pref codes

[Ni, Ruiyu]

On 1/24/2018 4:01 PM, Dandan Bi wrote:

Our new performance infrastructure can support to dump performance
date form ACPI table in OS. So we can remove the old pref code to
write performance data to OS.

Cc: Liming Gao 
Cc: Ruiyu Ni 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi 
---
  MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c   |  30 +-
  .../Library/UefiBootManagerLib/BmPerformance.c | 317 -
  .../Library/UefiBootManagerLib/InternalBm.h|   1 -
  .../UefiBootManagerLib/UefiBootManagerLib.inf  |   4 +-
  4 files changed, 28 insertions(+), 324 deletions(-)
  delete mode 100644 MdeModulePkg/Library/UefiBootManagerLib/BmPerformance.c

diff --git a/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c 
b/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
index d684482..eb8f3b5 100644
--- a/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
+++ b/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c
@@ -1,9 +1,9 @@
  /** @file
Library functions which relates with booting.
  
-Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.

+Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
  (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP
  This program and the accompanying materials
  are licensed and made available under the terms and conditions of the BSD 
License
  which accompanies this distribution.  The full text of the license may be 
found at
  http://opensource.org/licenses/bsd-license.php
@@ -26,10 +26,34 @@ EFI_BOOT_MANAGER_LEGACY_BOOT mBmLegacyBoot  
= NULL;
  ///
  EFI_GUID mBmHardDriveBootVariableGuid = { 0xfab7e9e1, 0x39dd, 0x4f2b, { 0x84, 
0x08, 0xe2, 0x0e, 0x90, 0x6c, 0xb6, 0xde } };
  EFI_GUID mBmAutoCreateBootOptionGuid  = { 0x8108ac4e, 0x9f11, 0x4d59, { 0x85, 
0x0e, 0xe2, 0x1a, 0x52, 0x2c, 0x59, 0xb2 } };
  
  /**

+
+  The end of BDS perf code.
+
+  @param  Event The triggered event.
+  @param  Context   Context for this event.
+
+**/
+VOID
+EFIAPI
+BmEndOfBdsPrefCode (
+  IN EFI_EVENT  Event,
+  IN VOID   *Context
+  )
+{
+  //
+  // Record the performance data for End of BDS
+  //
+  PERF_END(NULL, "BDS", NULL, 0);
+
+  return ;
+}
+
+/**
The function registers the legacy boot support capabilities.
  
@param RefreshLegacyBootOption The function pointer to create all the legacy boot options.

@param LegacyBoot  The function pointer to boot the legacy boot 
option.
  **/
@@ -1820,11 +1844,11 @@ EfiBootManagerBoot (
  //
  // Create an event to be signalled when Legacy Boot occurs to write 
performance data.
  //
  Status = EfiCreateEventLegacyBootEx(
 TPL_NOTIFY,
-   BmWriteBootToOsPerformanceData,
+   BmEndOfBdsPrefCode,
 NULL,
 
 );
  ASSERT_EFI_ERROR (Status);
);
@@ -1861,11 +1885,11 @@ EfiBootManagerBoot (
  
//

// Write boot to OS performance data for UEFI boot
//
PERF_CODE (
-BmWriteBootToOsPerformanceData (NULL, NULL);
+BmEndOfBdsPrefCode (NULL, NULL);
);
  
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, PcdGet32 (PcdProgressCodeOsLoaderStart));
  
Status = gBS->StartImage (ImageHandle, >ExitDataSize, >ExitData);

diff --git a/MdeModulePkg/Library/UefiBootManagerLib/BmPerformance.c 
b/MdeModulePkg/Library/UefiBootManagerLib/BmPerformance.c
deleted file mode 100644
index 4d4495b..000
--- a/MdeModulePkg/Library/UefiBootManagerLib/BmPerformance.c
+++ /dev/null
@@ -1,317 +0,0 @@
-/** @file
-  This file include the file which can help to get the system
-  performance, all the function will only include if the performance
-  switch is set.
-
-Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD 
License
-which accompanies this distribution.  The full text of the license may be 
found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "InternalBm.h"
-
-PERF_HEADER   mBmPerfHeader;
-PERF_DATA mBmPerfData;
-EFI_PHYSICAL_ADDRESS  mBmAcpiLowMemoryBase = 0x0ULL;
-
-/**
-  Get the short verion of PDB file name to be
-  used in performance data logging.
-
-  @param PdbFileName The long PDB file name.
-  @param GaugeString The output string to be logged by performance logger.
-  @param StringSize  The buffer size of GaugeString in bytes.
-
-**/
-VOID
-BmGetShortPdbFileName (
-  IN  CONST CHAR8  *PdbFileName,
-  OUT   CHAR8  *GaugeString,
-  INUINTN   StringSize

[edk2] [PATCH] Enable RSA2048SHA256 to replace CCG SignedSection solution

[Zhang, Chao B]

---
 KabylakePlatSamplePkg/PlatformPkg.dsc   | 13 +--
 KabylakePlatSamplePkg/PlatformPkg.fdf   | 36 +++--
 KabylakePlatSamplePkg/PlatformPkgConfig.dsc |  2 +-
 3 files changed, 31 insertions(+), 20 deletions(-)

diff --git a/KabylakePlatSamplePkg/PlatformPkg.dsc 
b/KabylakePlatSamplePkg/PlatformPkg.dsc
index fb085b9..125e018 100644
--- a/KabylakePlatSamplePkg/PlatformPkg.dsc
+++ b/KabylakePlatSamplePkg/PlatformPkg.dsc
@@ -1114,6 +1114,8 @@ gPlatformModuleTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
 
   gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x8c
 
+gEfiSecurityPkgTokenSpaceGuid.PcdRsa2048Sha256PublicKeyBuffer|{0x91, 0x29, 
0xc4, 0xbd, 0xea, 0x6d, 0xda, 0xb3, 0xaa, 0x6f, 0x50, 0x16, 0xfc, 0xdb, 0x4b, 
0x7e, 0x3c, 0xd6, 0xdc, 0xa4, 0x7a, 0x0e, 0xdd, 0xe6, 0x15, 0x8c, 0x73, 0x96, 
0xa2, 0xd4, 0xa6, 0x4d}
+
 [PcdsFixedAtBuild.IA32]
 !if gPlatformModuleTokenSpaceGuid.PcdFspWrapperEnable == TRUE
   gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
@@ -1445,6 +1447,11 @@ gPlatformModuleTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
 
   
NULL|$(CLIENT_COMMON_PACKAGE)/Library/PeiSignedSectionVerificationLib/PeiSignedSectionVerificationLib.inf
   }
+  
+  MdeModulePkg/Universal/SectionExtractionPei/SectionExtractionPei.inf {
+  
+
NULL|SecurityPkg\Library\PeiRsa2048Sha256GuidedSectionExtractLib\PeiRsa2048Sha256GuidedSectionExtractLib.inf
+  }
 !endif
 
 !if gSiPkgTokenSpaceGuid.PcdS3Enable == TRUE
@@ -1575,7 +1582,8 @@ 
$(CLIENT_COMMON_PACKAGE)/Universal/DebugServicePei/DebugServicePei.inf {
   gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046
 
 !if gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == TRUE
-  
NULL|$(CLIENT_COMMON_PACKAGE)/Library/DxeSignedSectionVerificationLib/DxeSignedSectionVerificationLib.inf
+# 
NULL|$(CLIENT_COMMON_PACKAGE)/Library/DxeSignedSectionVerificationLib/DxeSignedSectionVerificationLib.inf
+  
NULL|SecurityPkg\Library\DxeRsa2048Sha256GuidedSectionExtractLib\DxeRsa2048Sha256GuidedSectionExtractLib.inf
 !endif
 !if gPlatformModuleTokenSpaceGuid.PcdDxeCrc32SectionEnable == TRUE
   
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
@@ -1600,7 +1608,8 @@ 
$(CLIENT_COMMON_PACKAGE)/Universal/DebugServicePei/DebugServicePei.inf {
   gEfiMdeModulePkgTokenSpaceGuid.PcdPropertiesTableEnable|FALSE
 
 !if gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == TRUE
-  
NULL|$(CLIENT_COMMON_PACKAGE)/Library/DxeSignedSectionVerificationLib/DxeSignedSectionVerificationLib.inf
+  
#NULL|$(CLIENT_COMMON_PACKAGE)/Library/DxeSignedSectionVerificationLib/DxeSignedSectionVerificationLib.inf
+  
NULL|SecurityPkg\Library\DxeRsa2048Sha256GuidedSectionExtractLib\DxeRsa2048Sha256GuidedSectionExtractLib.inf
 !endif
 !if gPlatformModuleTokenSpaceGuid.PcdDxeCrc32SectionEnable == TRUE
   
NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
diff --git a/KabylakePlatSamplePkg/PlatformPkg.fdf 
b/KabylakePlatSamplePkg/PlatformPkg.fdf
index d2e8ee3..9d3fa5d 100644
--- a/KabylakePlatSamplePkg/PlatformPkg.fdf
+++ b/KabylakePlatSamplePkg/PlatformPkg.fdf
@@ -406,7 +406,7 @@ INF  
$(PLATFORM_FEATURES_PATH)/Amt/AmtStatusCodePei/AmtStatusCodePei.inf
 
 INF $(PLATFORM_PACKAGE)/BiosInfo/BiosInfo.inf # AdvancedFeaturesContent
 !if gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == TRUE
-INF  
$(PLATFORM_PACKAGE)/Override/$(CLIENT_COMMON_PACKAGE)/Universal/BiosInfoChecker/BiosInfoChecker.inf
+#INF  
$(PLATFORM_PACKAGE)/Override/$(CLIENT_COMMON_PACKAGE)/Universal/BiosInfoChecker/BiosInfoChecker.inf
 !endif
 
 !if gSiPkgTokenSpaceGuid.PcdSleEnable == FALSE
@@ -462,12 +462,13 @@ INF 
$(PLATFORM_PACKAGE)/Platform/MsegSmramPei/MsegSmramPei.inf
 INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
 
 !if gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == TRUE
-INF $(CLIENT_COMMON_PACKAGE)/Universal/SignedSectionPei/SignedSectionPei.inf
-!if gPlatformModuleTokenSpaceGuid.PcdPubKeyHashBinEnable == TRUE
-FILE RAW = 31C17ABE-6071-435e-BAA4-0B8A8C3649F3 {
-$(PLATFORM_PACKAGE)/Tools/ToolScripts/SignFv/pubkeyhash.bin
-  }
-!endif # PcdPubKeyHashBinEnable
+INF MdeModulePkg/Universal/SectionExtractionPei/SectionExtractionPei.inf
+#INF $(CLIENT_COMMON_PACKAGE)/Universal/SignedSectionPei/SignedSectionPei.inf
+#!if gPlatformModuleTokenSpaceGuid.PcdPubKeyHashBinEnable == TRUE
+#FILE RAW = 31C17ABE-6071-435e-BAA4-0B8A8C3649F3 {
+#$(PLATFORM_PACKAGE)/Tools/ToolScripts/SignFv/pubkeyhash.bin
+#  }
+#!endif # PcdPubKeyHashBinEnable
 !endif # PcdSecureBootEnable
 
 !if gPlatformModuleTokenSpaceGuid.PcdTpmEnable == TRUE
@@ -604,7 +605,7 @@ APRIORI PEI {
 !endif
 
 !if gPlatformModuleTokenSpaceGuid.PcdSecureBootEnable == TRUE
-  INF  
$(PLATFORM_PACKAGE)/Override/$(CLIENT_COMMON_PACKAGE)/Universal/BiosInfoChecker/BiosInfoChecker.inf
  # RPPO-SKL-0031: RoyalParkOverrideContent
+  #INF  

Re: [edk2] [patch 2/3] MdeModulePkg/BdsDxe: Remove useless Pref Code

[Ni, Ruiyu]

On 1/24/2018 4:01 PM, Dandan Bi wrote:

Our new performance infrastructure can support to dump performance
date form ACPI table in OS. So we can remove the old pref code to
write performance data to OS.

Cc: Liming Gao 
Cc: Ruiyu Ni 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi 
---
  MdeModulePkg/Universal/BdsDxe/Bds.h  |  3 +-
  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf |  3 +-
  MdeModulePkg/Universal/BdsDxe/BdsEntry.c | 57 +---
  3 files changed, 3 insertions(+), 60 deletions(-)

diff --git a/MdeModulePkg/Universal/BdsDxe/Bds.h 
b/MdeModulePkg/Universal/BdsDxe/Bds.h
index 5658e61..63d961f 100644
--- a/MdeModulePkg/Universal/BdsDxe/Bds.h
+++ b/MdeModulePkg/Universal/BdsDxe/Bds.h
@@ -1,9 +1,9 @@
  /** @file
Head file for BDS Architectural Protocol implementation
  
-Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.

+Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
  This program and the accompanying materials
  are licensed and made available under the terms and conditions of the BSD 
License
  which accompanies this distribution.  The full text of the license may be 
found at
  http://opensource.org/licenses/bsd-license.php
  
@@ -16,11 +16,10 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

  #define _BDS_MODULE_H_
  
  #include 

  #include 
  #include 
-#include 
  #include 
  #include 
  
  #include 

  #include 
diff --git a/MdeModulePkg/Universal/BdsDxe/BdsDxe.inf 
b/MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
index a00b442..b8c5aa9 100644
--- a/MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+++ b/MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
@@ -3,11 +3,11 @@
  #
  #  When DxeCore dispatching all DXE driver, this module will produce 
architecture protocol
  #  gEfiBdsArchProtocolGuid. After DxeCore finish dispatching, DxeCore will 
invoke Entry
  #  interface of protocol gEfiBdsArchProtocolGuid, then BDS phase is entered.
  #
-#  Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+#  Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
  #  This program and the accompanying materials
  #  are licensed and made available under the terms and conditions of the BSD 
License
  #  which accompanies this distribution.  The full text of the license may be 
found at
  #  http://opensource.org/licenses/bsd-license.php
  #
@@ -76,11 +76,10 @@
  ## SOMETIMES_CONSUMES ## 
Variable:L"ConIn" (The device path of console in device)
  ## SOMETIMES_CONSUMES ## 
Variable:L"ConOut" (The device path of console out device)
  ## SOMETIMES_CONSUMES ## 
Variable:L"ErrOut" (The device path of error out device)
gConnectConInEventGuid## SOMETIMES_CONSUMES ## Event
gEdkiiStatusCodeDataTypeVariableGuid  ## SOMETIMES_CONSUMES ## GUID
-  gPerformanceProtocolGuid  ## SOMETIMES_PRODUCES ## 
Variable:L"PerfDataMemAddr" (The ACPI address of performance data)
gEfiEventReadyToBootGuid  ## CONSUMES   ## Event
  
  [Protocols]

gEfiBdsArchProtocolGuid   ## PRODUCES
gEfiSimpleTextInputExProtocolGuid ## CONSUMES
diff --git a/MdeModulePkg/Universal/BdsDxe/BdsEntry.c 
b/MdeModulePkg/Universal/BdsDxe/BdsEntry.c
index 2b24755..3191a98 100644
--- a/MdeModulePkg/Universal/BdsDxe/BdsEntry.c
+++ b/MdeModulePkg/Universal/BdsDxe/BdsEntry.c
@@ -3,11 +3,11 @@
When this module was dispatched by DxeCore, gEfiBdsArchProtocolGuid will be 
installed
which contains interface of BdsEntry.
After DxeCore finish DXE phase, gEfiBdsArchProtocolGuid->BdsEntry will be 
invoked
to enter BDS phase.
  
-Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.

+Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
  (C) Copyright 2016 Hewlett Packard Enterprise Development LP
  (C) Copyright 2015 Hewlett-Packard Development Company, L.P.
  This program and the accompanying materials
  are licensed and made available under the terms and conditions of the BSD 
License
  which accompanies this distribution.  The full text of the license may be 
found at
@@ -633,61 +633,10 @@ BdsFormalizeEfiGlobalVariable (
//
BdsFormalizeOSIndicationVariable ();
  }
  
  /**

-
-  Allocate a block of memory that will contain performance data to OS.
-
-**/
-VOID
-BdsAllocateMemoryForPerformanceData (
-  VOID
-  )
-{
-  EFI_STATUSStatus;
-  EFI_PHYSICAL_ADDRESS  AcpiLowMemoryBase;
-  EDKII_VARIABLE_LOCK_PROTOCOL  *VariableLock;
-
-  AcpiLowMemoryBase = 0x0ULL;
-
-  //
-  // Allocate a block of memory that will contain performance data to OS.
-  //
-  Status = gBS->AllocatePages (
-

[edk2] [PATCH] SecurityPkg/DxePhysicalPresenceLib: Reject illegal PCR bank allocation

[Zhang, Chao B]

According to TCG PP1.3 spec, error PCR bank allocation input should be rejected 
by
Physical Presence. Firmware has to ensure that at least one PCR banks is active.

Cc: Long Qin 
Cc: Yao Jiewen 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chao Zhang 
---
 .../DxeTcg2PhysicalPresenceLib/DxeTcg2PhysicalPresenceLib.c  | 12 
 1 file changed, 12 insertions(+)

diff --git 
a/SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/DxeTcg2PhysicalPresenceLib.c 
b/SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/DxeTcg2PhysicalPresenceLib.c
index 5bf95a1..830266b 100644
--- 
a/SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/DxeTcg2PhysicalPresenceLib.c
+++ 
b/SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/DxeTcg2PhysicalPresenceLib.c
@@ -186,6 +186,18 @@ Tcg2ExecutePhysicalPresence (
 case TCG2_PHYSICAL_PRESENCE_SET_PCR_BANKS:
   Status = Tpm2GetCapabilitySupportedAndActivePcrs 
(, );
   ASSERT_EFI_ERROR (Status);
+
+  //
+  // PP spec requirements:
+  //Firmware should check that all requested (set) hashing algorithms 
are supported with respective PCR banks. 
+  //Firmware has to ensure that at least one PCR banks is active
+  // If not, an error is returned and no action is taken
+  //
+  if (CommandParameter == 0 || (CommandParameter & 
(~TpmHashAlgorithmBitmap)) != 0) {
+DEBUG((DEBUG_ERROR, "PCR banks %x to allocate are not supported by 
TPM. Skip operation\n", CommandParameter));
+return TCG_PP_OPERATION_RESPONSE_BIOS_FAILURE
+  }
+  DEBUG((DEBUG_ERROR, "zhangchao TpmHashAlgorithmBitmap %x 
CommandParameter %x\n", TpmHashAlgorithmBitmap, CommandParameter));
   Status = Tpm2PcrAllocateBanks (PlatformAuth, TpmHashAlgorithmBitmap, 
CommandParameter);
   if (EFI_ERROR (Status)) {
 return TCG_PP_OPERATION_RESPONSE_BIOS_FAILURE;
-- 
1.9.5.msysgit.1

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[edk2] [PATCH] SecurityPkg:Tpm2DeviceLibDTpm: Support TPM command cancel

[Zhang, Chao B]

Support TPM Command cancel if executing command timeouts. Cancel could
happen in long running command case

Cc: Yao Jiewen 
Cc: Chinnusamy Rajkumar K 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chao Zhang 
---
 MdePkg/Include/IndustryStandard/TpmTis.h|  8 +--
 SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c | 24 +---
 SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c | 30 +
 3 files changed, 53 insertions(+), 9 deletions(-)

diff --git a/MdePkg/Include/IndustryStandard/TpmTis.h 
b/MdePkg/Include/IndustryStandard/TpmTis.h
index 519fa79..f25ca25 100644
--- a/MdePkg/Include/IndustryStandard/TpmTis.h
+++ b/MdePkg/Include/IndustryStandard/TpmTis.h
@@ -2,7 +2,7 @@
   TPM Interface Specification definition.
   It covers both TPM1.2 and TPM2.0.
 
-Copyright (c) 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -143,6 +143,10 @@ typedef TIS_PC_REGISTERS  *TIS_PC_REGISTERS_PTR;
 #define TIS_PC_ACC_ESTABLISHBIT0
 
 ///
+/// Write a 1 to this bit to notify TPM to cancel currently executing command
+///
+#define TIS_PC_STS_CANCEL   BIT24
+///
 /// This field indicates that STS_DATA and STS_EXPECT are valid
 ///
 #define TIS_PC_STS_VALIDBIT7
@@ -180,4 +184,4 @@ typedef TIS_PC_REGISTERS  *TIS_PC_REGISTERS_PTR;
 #define TIS_TIMEOUT_C   (750  * 1000)  // 750ms
 #define TIS_TIMEOUT_D   (750  * 1000)  // 750ms
 
-#endif
\ No newline at end of file
+#endif
diff --git a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c 
b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c
index ddd4bd0..d9df264 100644
--- a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c
+++ b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c
@@ -1,7 +1,7 @@
 /** @file
   PTP (Platform TPM Profile) CRB (Command Response Buffer) interface used by 
dTPM2.0 library.
 
-Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -240,8 +240,26 @@ PtpCrbTpmCommand (
  PTP_TIMEOUT_MAX
  );
   if (EFI_ERROR (Status)) {
-Status = EFI_DEVICE_ERROR;
-goto Exit;
+//
+// Command Completion check timeout. Cancel the currently executing 
command by writing TPM_CRB_CTRL_CANCEL,
+// Expect TPM_RC_CANCELLED or successfully completed response.
+//
+MmioWrite32((UINTN)>CrbControlCancel, PTP_CRB_CONTROL_CANCEL);
+Status = PtpCrbWaitRegisterBits (
+   >CrbControlStart,
+   0,
+   PTP_CRB_CONTROL_START,
+   PTP_TIMEOUT_B
+   );
+MmioWrite32((UINTN)>CrbControlCancel, 0);
+
+if (EFI_ERROR(Status)) {
+  //
+  // Still in Command Execution state. Try to goIdle, the behavior is 
agnostic.
+  //
+  Status = EFI_DEVICE_ERROR;
+  goto Exit;
+}
   }
 
   //
diff --git a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c 
b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c
index 6cd7030..0889162 100644
--- a/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c
+++ b/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Tis.c
@@ -1,7 +1,7 @@
 /** @file
   TIS (TPM Interface Specification) functions used by dTPM2.0 library.
   
-Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
 (C) Copyright 2015 Hewlett Packard Enterprise Development LP
 This program and the accompanying materials 
 are licensed and made available under the terms and conditions of the BSD 
License 
@@ -295,10 +295,32 @@ Tpm2TisTpmCommand (
  TIS_TIMEOUT_MAX
  );
   if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_ERROR, "Wait for Tpm2 response data time out!!\n"));
-Status = EFI_DEVICE_ERROR;
-goto Exit;
+//
+// dataAvail check timeout. Cancel the currently executing command by 
writing commandCancel,
+// Expect TPM_RC_CANCELLED or successfully completed response.
+//
+DEBUG ((DEBUG_ERROR, "Wait for Tpm2 response data time out. Trying to 
cancel the command!!\n"));
+
+MmioWrite32((UINTN)>Status, TIS_PC_STS_CANCEL);
+Status = TisPcWaitRegisterBits (
+   >Status,
+   (UINT8) (TIS_PC_VALID | TIS_PC_STS_DATA),
+   0,
+   TIS_TIMEOUT_B
+   );
+//
+// Do not clear CANCEL bit here bicoz Writes of 0 to this bit are ignored
+//
+if 

[edk2] [PATCH] SecurityPkg/PhysicalPresenceLib: Reject illegal PCR bank allocation

[Zhang, Chao B]

According to TCG PP1.3 spec, error PCR bank allocation input should be
rejected by Physical Presence. Firmware has to ensure that at least one
PCR banks is active.

Cc: Long Qin 
Cc: Yao Jiewen 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chao Zhang 
---
 .../DxeTcg2PhysicalPresenceLib/DxeTcg2PhysicalPresenceLib.c  | 12 
 1 file changed, 12 insertions(+)

diff --git 
a/SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/DxeTcg2PhysicalPresenceLib.c 
b/SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/DxeTcg2PhysicalPresenceLib.c
index 5bf95a1..28f0ca0 100644
--- 
a/SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/DxeTcg2PhysicalPresenceLib.c
+++ 
b/SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/DxeTcg2PhysicalPresenceLib.c
@@ -186,6 +186,18 @@ Tcg2ExecutePhysicalPresence (
 case TCG2_PHYSICAL_PRESENCE_SET_PCR_BANKS:
   Status = Tpm2GetCapabilitySupportedAndActivePcrs 
(, );
   ASSERT_EFI_ERROR (Status);
+
+  //
+  // PP spec requirements:
+  //Firmware should check that all requested (set) hashing algorithms 
are supported with respective PCR banks.
+  //Firmware has to ensure that at least one PCR banks is active.
+  // If not, an error is returned and no action is taken.
+  //
+  if (CommandParameter == 0 || (CommandParameter & 
(~TpmHashAlgorithmBitmap)) != 0) {
+DEBUG((DEBUG_ERROR, "PCR banks %x to allocate are not supported by 
TPM. Skip operation\n", CommandParameter));
+return TCG_PP_OPERATION_RESPONSE_BIOS_FAILURE
+  }
+  DEBUG((DEBUG_ERROR, "zhangchao TpmHashAlgorithmBitmap %x 
CommandParameter %x\n", TpmHashAlgorithmBitmap, CommandParameter));
   Status = Tpm2PcrAllocateBanks (PlatformAuth, TpmHashAlgorithmBitmap, 
CommandParameter);
   if (EFI_ERROR (Status)) {
 return TCG_PP_OPERATION_RESPONSE_BIOS_FAILURE;
-- 
1.9.5.msysgit.1

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Re: [edk2] setting the TLS cipher list for HTTPS booting

[Wu, Jiaxin]

Hi Laszlo,

The HttpDxe driver needs to install the Driver Binding Protocol so as to check 
if a specific controller is supported by HttpDxe. HttpDxe can only be started 
if the TcpServiceBindingProtocol existed. So, it has to follow the UEFI Driver 
Model. 

For the PCD usage, I think it should be fine to cover the configuration of UEFI 
Drivers through the PCD settings. The requirement of *.inf needs to include the 
PcdLib and the section of [Pcd]. We already have the similar pattern for this 
usage, for example, Ps2KeyboardDxe, PciBusDxe, PciSioSerialDxe, and etc in 
MdeModulePkg. Besides, there are some advantages by using PCD compared to the 
variable. First, PCD is one kind of interface that more formal than a private 
variable, the setting by PCD is more acceptable by the consumer. Secondly, from 
a *security* standpoint, variable can be dumped easily from the flash region. 
Here, even though it's no security impact towards the cipher list storage 
because it will be public shared to remote server, but we need to think and 
*align* with other configurations for TLS in HTTPS level. For example, in the 
future, we might support the HTTPS mutual authentication, than the host 
PrivateKey/Password (EfiTlsConfigDataTypeHostPrivateKey) *mustn't* be s
 aved as a variable due to its confidentiality, while PCD is good choice. At 
that time, we will also provide the PCD for EfiTlsConfigDataTypeCACertificate, 
which is currently setting by the variable (TlsCaCertificate), so as to align 
all the configuration setting on one line, which can reduce the complexity of 
platform usage. Finally, we can also save the variable space.

>From the above, the dynamic PCD is a solution I still preferred.

Thanks,
Jiaxin



> -Original Message-
> From: Laszlo Ersek [mailto:ler...@redhat.com]
> Sent: Thursday, January 25, 2018 12:13 AM
> To: Wu, Jiaxin ; Fu, Siyuan ; Ye,
> Ting ; Long, Qin ; Yao, Jiewen
> ; Hsiung, Harry L 
> Cc: edk2-devel-01 
> Subject: Re: setting the TLS cipher list for HTTPS booting
> 
> On 01/24/18 07:50, Wu, Jiaxin wrote:
> > Hi Laszlo,
> >
> > After the discussion with team member, we still prefer to use the PCD
> > solution. In HttpDxe driver, we don't want to locate/use a
> > nonstandard protocol. We think It's not a general solution for the
> > UEFI driver.
> Ah, I totally missed that NetworkPkg/HttpDxe was a UEFI_DRIVER! :)
> 
> In that case, I think *neither* the LocateProtocol() call for an
> edk2-specific protocol, *nor* a PcdGetPtr() call are appropriate.
> UEFI_DRIVER modules should preferably only use facilities from the UEFI
> spec, and the protocol for the dynamic PCDs comes from the PI spec, not
> the UEFI spec.
> 
> (This would be different if HttpDxe was a DXE_DRIVER -- in that case
> both approaches would be valid. I assumed HttpDxe was a DXE_DRIVER, not
> sure why.)
> 
> (1) So, given that HttpDxe is a UEFI_DRIVER, I think the right approach
> would be -- which I believe I also mentioned earlier -- to introduce
> another UEFI variable for the list of cipher suites, similarly to
> "TlsCaCertificate" (in a custom variable namespace GUID). This would
> stay within the framework of the UEFI spec.
> 
> 
> (2) Regarding the order between setting these UEFI variables in OVMF,
> and consuming them in HttpDxe, I think your argument is good. We can set
> the variables in some platform code (DXE_DRIVER) in OVMF, before
> End-of-DXE, and HttpDxe will only read them later in BDS.
> 
> "OvmfPkg/PlatformDxe" seems like a good candidate for setting these
> variables (both considering PlatformDxe's purpose, and because it
> already depends on "gEfiVariableWriteArchProtocolGuid").
> 
> 
> (3) Regardig the format (EFI_TLS_CIPHER): I agree with you. It seems we
> can modify the host environment to pass QEMU (and OVMF) a cipher list
> that is already in EFI_TLS_CIPHER format.
> 
> 
> So I think the only remaining question is if you like a new UEFI
> variable instead of the dynamic PCD, for the cipher list.
> 
> Thanks!
> Laszlo
> 
> 
> 
> >
> > Thanks,
> > Jiaxin
> >
> >> -Original Message-
> >> From: Wu, Jiaxin
> >> Sent: Wednesday, January 24, 2018 11:40 AM
> >> To: Wu, Jiaxin ; Laszlo Ersek ;
> Fu,
> >> Siyuan ; Ye, Ting ; Long, Qin
> >> ; Yao, Jiewen ; Hsiung, Harry
> L
> >> 
> >> Cc: edk2-devel-01 
> >> Subject: RE: setting the TLS cipher list for HTTPS booting
> >>
> >> Hi Laszlo,
> >>
> >> More comments:
> >>
> >>>
> >>> Dynamic PCDs is just one of the solutions for the required settings, just 
> >>> like
> >> the
> >>> platform protocol (HTTPS_CONFIG_PROTOCOL), provides the capability to
> >>> support the global HTTPS configuration.
> >>>
> >>> Each solutions 

Re: [edk2] [PATCH] BaseTools: Fix indentation

[Zhu, Yonghong]

Reviewed-by: Yonghong Zhu  

Best Regards,
Zhu Yonghong


-Original Message-
From: Gary Lin [mailto:g...@suse.com] 
Sent: Wednesday, January 17, 2018 12:06 PM
To: edk2-devel@lists.01.org
Cc: Zhu, Yonghong ; Gao, Liming 
Subject: [PATCH] BaseTools: Fix indentation

Mixing usage of spaces and tabs may confuse the python compiler/interpreter.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Gary Lin 
Cc: Yonghong Zhu 
Cc: Liming Gao 
---
 BaseTools/Source/Python/Ecc/CParser.py | 11 ++-  
BaseTools/Source/Python/Eot/CParser.py | 11 ++-
 2 files changed, 4 insertions(+), 18 deletions(-)

diff --git a/BaseTools/Source/Python/Ecc/CParser.py 
b/BaseTools/Source/Python/Ecc/CParser.py
index baa521f43c..41f2811430 100644
--- a/BaseTools/Source/Python/Ecc/CParser.py
+++ b/BaseTools/Source/Python/Ecc/CParser.py
@@ -98,16 +98,9 @@ class CParser(Parser):
 Parser.__init__(self, input)
 self.ruleMemo = {}
 
-   self.function_definition_stack = []
-   self.postfix_expression_stack = []
+self.function_definition_stack = []
+self.postfix_expression_stack = []
 
-
-
-
-
-
-  
-
 def printTokenInfo(self, line, offset, tokenText):
print str(line)+ ',' + str(offset) + ':' + str(tokenText)
 
diff --git a/BaseTools/Source/Python/Eot/CParser.py 
b/BaseTools/Source/Python/Eot/CParser.py
index baa521f43c..41f2811430 100644
--- a/BaseTools/Source/Python/Eot/CParser.py
+++ b/BaseTools/Source/Python/Eot/CParser.py
@@ -98,16 +98,9 @@ class CParser(Parser):
 Parser.__init__(self, input)
 self.ruleMemo = {}
 
-   self.function_definition_stack = []
-   self.postfix_expression_stack = []
+self.function_definition_stack = []
+self.postfix_expression_stack = []
 
-
-
-
-
-
-  
-
 def printTokenInfo(self, line, offset, tokenText):
print str(line)+ ',' + str(offset) + ':' + str(tokenText)
 
--
2.15.1

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Re: [edk2] [PATCH] MdeModulePkg PiSmmCore: Set ForwardLink to NULL in RemoveOldEntry()

[Yao, Jiewen]

Reviewed-by: jiewen@intel.com

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Star
> Zeng
> Sent: Thursday, January 25, 2018 11:23 AM
> To: edk2-devel@lists.01.org
> Cc: Yao, Jiewen ; Zeng, Star 
> Subject: [edk2] [PATCH] MdeModulePkg PiSmmCore: Set ForwardLink to NULL in
> RemoveOldEntry()
> 
> "Entry->Link.ForwardLink = NULL;" is present in RemoveMemoryMapEntry()
> for DxeCore, that is correct.
> "Entry->Link.ForwardLink = NULL;" is absent in RemoveOldEntry()
> for PiSmmCore, that is incorrect.
> 
> Without this fix, when FromStack in Entry is TRUE,
> the "InsertTailList ([mMapDepth].Link, >Link);" in
> following calling to CoreFreeMemoryMapStack() will fail as the entry
> at mMapStack[mMapDepth] actually has been removed from the list.
> 
> Cc: Jiewen Yao 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Star Zeng 
> ---
>  MdeModulePkg/Core/PiSmmCore/Page.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/MdeModulePkg/Core/PiSmmCore/Page.c
> b/MdeModulePkg/Core/PiSmmCore/Page.c
> index 8909d46a00a2..3699af742458 100644
> --- a/MdeModulePkg/Core/PiSmmCore/Page.c
> +++ b/MdeModulePkg/Core/PiSmmCore/Page.c
> @@ -1,7 +1,7 @@
>  /** @file
>SMM Memory page management functions.
> 
> -  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
> +  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
>This program and the accompanying materials are licensed and made
> available
>under the terms and conditions of the BSD License which accompanies this
>distribution.  The full text of the license may be found at
> @@ -246,6 +246,8 @@ RemoveOldEntry (
>)
>  {
>RemoveEntryList (>Link);
> +  Entry->Link.ForwardLink = NULL;
> +
>if (!Entry->FromStack) {
>  InsertTailList (, >Link);
>}
> --
> 2.7.0.windows.1
> 
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[edk2] [PATCH] MdeModulePkg PiSmmCore: Set ForwardLink to NULL in RemoveOldEntry()

[Star Zeng]

"Entry->Link.ForwardLink = NULL;" is present in RemoveMemoryMapEntry()
for DxeCore, that is correct.
"Entry->Link.ForwardLink = NULL;" is absent in RemoveOldEntry()
for PiSmmCore, that is incorrect.

Without this fix, when FromStack in Entry is TRUE,
the "InsertTailList ([mMapDepth].Link, >Link);" in
following calling to CoreFreeMemoryMapStack() will fail as the entry
at mMapStack[mMapDepth] actually has been removed from the list.

Cc: Jiewen Yao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng 
---
 MdeModulePkg/Core/PiSmmCore/Page.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/MdeModulePkg/Core/PiSmmCore/Page.c 
b/MdeModulePkg/Core/PiSmmCore/Page.c
index 8909d46a00a2..3699af742458 100644
--- a/MdeModulePkg/Core/PiSmmCore/Page.c
+++ b/MdeModulePkg/Core/PiSmmCore/Page.c
@@ -1,7 +1,7 @@
 /** @file
   SMM Memory page management functions.
 
-  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials are licensed and made available
   under the terms and conditions of the BSD License which accompanies this
   distribution.  The full text of the license may be found at
@@ -246,6 +246,8 @@ RemoveOldEntry (
   )
 {
   RemoveEntryList (>Link);
+  Entry->Link.ForwardLink = NULL;
+
   if (!Entry->FromStack) {
 InsertTailList (, >Link);
   }
-- 
2.7.0.windows.1

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Re: [edk2] [Patch] BaseTools: CommonLib Fix Crash to write the last byte

[Zhu, Yonghong]

Reviewed-by: Yonghong Zhu 

Best Regards,
Zhu Yonghong


-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Liming 
Gao
Sent: Thursday, January 25, 2018 9:42 AM
To: edk2-devel@lists.01.org
Subject: [edk2] [Patch] BaseTools: CommonLib Fix Crash to write the last byte

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao 
---
 BaseTools/Source/C/Common/PcdValueCommon.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/BaseTools/Source/C/Common/PcdValueCommon.c 
b/BaseTools/Source/C/Common/PcdValueCommon.c
index 32963e6..92328da 100644
--- a/BaseTools/Source/C/Common/PcdValueCommon.c
+++ b/BaseTools/Source/C/Common/PcdValueCommon.c
@@ -335,7 +335,7 @@ Returns:
   printf("%x\n", Byte);
   Value = End + 1;
 }
-Buffer = malloc(*Size);
+Buffer = malloc(*Size + 1);
 if (Buffer == NULL) {
   *Size = 0;
   return NULL;
-- 
2.8.0.windows.1

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[edk2] [PATCH] IntelSiliconPkg/MicrocodeUpdateDxe: Refine debug messages

[Hao Wu]

Refine the debug messages during the verification of microcode to make
them more clear.

Cc: Jiewen Yao 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hao Wu 
---
 .../Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.c| 21 +++--
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git 
a/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.c 
b/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.c
index b99221c969..6167e0b584 100644
--- a/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.c
+++ b/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.c
@@ -8,7 +8,7 @@
 
   MicrocodeWrite() and VerifyMicrocode() will receive untrusted input and do 
basic validation.
 
-  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -437,7 +437,7 @@ VerifyMicrocode (
 return EFI_VOLUME_CORRUPTED;
   }
   if (TotalSize != ImageSize) {
-DEBUG((DEBUG_ERROR, "VerifyMicrocode - fail on TotalSize\n"));
+DEBUG((DEBUG_ERROR, "VerifyMicrocode - TotalSize not equal to 
ImageSize\n"));
 *LastAttemptStatus = LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT;
 if (AbortReason != NULL) {
   *AbortReason = AllocateCopyPool(sizeof(L"InvalidTotalSize"), 
L"InvalidTotalSize");
@@ -496,16 +496,25 @@ VerifyMicrocode (
   //
   if ((ExtendedTableLength > sizeof(CPU_MICROCODE_EXTENDED_TABLE_HEADER)) 
&& ((ExtendedTableLength & 0x3) == 0)) {
 CheckSum32 = CalculateSum32((UINT32 *)ExtendedTableHeader, 
ExtendedTableLength);
-if (CheckSum32 == 0) {
+if (CheckSum32 != 0) {
+  //
+  // Checksum incorrect
+  //
+  DEBUG((DEBUG_ERROR, "VerifyMicrocode - The extended checksum is 
incorrect\n"));
+} else {
   //
   // Checksum correct
   //
   ExtendedTableCount = ExtendedTableHeader->ExtendedSignatureCount;
-  if (ExtendedTableCount <= (ExtendedTableLength - 
sizeof(CPU_MICROCODE_EXTENDED_TABLE_HEADER)) / 
sizeof(CPU_MICROCODE_EXTENDED_TABLE)) {
+  if (ExtendedTableCount > (ExtendedTableLength - 
sizeof(CPU_MICROCODE_EXTENDED_TABLE_HEADER)) / 
sizeof(CPU_MICROCODE_EXTENDED_TABLE)) {
+DEBUG((DEBUG_ERROR, "VerifyMicrocode - ExtendedTableCount too 
big\n"));
+  } else {
 ExtendedTable = (CPU_MICROCODE_EXTENDED_TABLE 
*)(ExtendedTableHeader + 1);
 for (Index = 0; Index < ExtendedTableCount; Index++) {
   CheckSum32 = CalculateSum32((UINT32 *)ExtendedTable, 
sizeof(CPU_MICROCODE_EXTENDED_TABLE));
-  if (CheckSum32 == 0) {
+  if (CheckSum32 != 0) {
+DEBUG((DEBUG_ERROR, "VerifyMicrocode - Checksum is incorrect 
for ExtendedTable with index 0x%x\n", Index));
+  } else {
 //
 // Verify Header
 //
@@ -526,7 +535,7 @@ VerifyMicrocode (
 }
 if (!CorrectMicrocode) {
   if (TryLoad) {
-DEBUG((DEBUG_ERROR, "VerifyMicrocode - fail on 
CurrentProcessorSignature/ProcessorFlags\n"));
+DEBUG((DEBUG_ERROR, "VerifyMicrocode - fail on Current 
ProcessorSignature/ProcessorFlags\n"));
   }
   *LastAttemptStatus = LAST_ATTEMPT_STATUS_ERROR_INCORRECT_VERSION;
   if (AbortReason != NULL) {
-- 
2.12.0.windows.1

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[edk2] [Patch] BaseTools: CommonLib Fix Crash to write the last byte

[Liming Gao]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao 
---
 BaseTools/Source/C/Common/PcdValueCommon.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/BaseTools/Source/C/Common/PcdValueCommon.c 
b/BaseTools/Source/C/Common/PcdValueCommon.c
index 32963e6..92328da 100644
--- a/BaseTools/Source/C/Common/PcdValueCommon.c
+++ b/BaseTools/Source/C/Common/PcdValueCommon.c
@@ -335,7 +335,7 @@ Returns:
   printf("%x\n", Byte);
   Value = End + 1;
 }
-Buffer = malloc(*Size);
+Buffer = malloc(*Size + 1);
 if (Buffer == NULL) {
   *Size = 0;
   return NULL;
-- 
2.8.0.windows.1

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Re: [edk2] [PATCH] UefiCpuPkg/MpInitLib: fix issue in wakeup buffer initialization

[Wang, Jian J]

Considering that there's a similar assignment in "else" block

ExchangeInfo->ModeTransitionMemory = (UINT32)
  (ExchangeInfo->BufferStart + CpuMpData->AddressMap.ModeTransitionOffset);

I would rather keep the assignment statement you mentioned inside "if" block.

Actually there's another issue in this part of code. To fix it, the assignment 
to
ModeHighMemory and ModeHighSegment will be moved outside the "if" block.
>From this fix perspective, it'd be also better to keep all assignments to
ModeTransitionMemory inside "if/else" block. You'll see it in a new patch later.

Anyway, thanks for the comments.

Regards,
Jian


> -Original Message-
> From: Laszlo Ersek [mailto:ler...@redhat.com]
> Sent: Wednesday, January 24, 2018 11:30 PM
> To: Wang, Jian J ; edk2-devel@lists.01.org
> Cc: Ni, Ruiyu ; Dong, Eric 
> Subject: Re: [PATCH] UefiCpuPkg/MpInitLib: fix issue in wakeup buffer
> initialization
> 
> On 01/24/18 03:08, Jian J Wang wrote:
> > To fix an issue in which enabling NX feature will mark the AP wakeup
> > buffer as non-executable and fail the AP init, the buffer was split
> > into two part: the lower part in memory within 1MB and the higher part
> > within allocated executable memory (EfiBootServicesCode). But the
> > address of higher part memory was stored in lower part memory, which
> > is actually shared with legacy components and will be overwritten by
> > LegacyBiosDxe driver if CSM is enabled.
> >
> > This patch fixes this issue by storing the address of higher part
> > memory in CpuMpData instead of ExchangeInfo.
> >
> > Cc: Ruiyu Ni 
> > Cc: Eric Dong 
> > Cc: Laszlo Ersek 
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Jian J Wang 
> > ---
> >  UefiCpuPkg/Library/MpInitLib/MpLib.c | 20 ++--
> >  UefiCpuPkg/Library/MpInitLib/MpLib.h |  1 +
> >  2 files changed, 11 insertions(+), 10 deletions(-)
> >
> > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > index 6231968c74..42011d6231 100644
> > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > @@ -823,19 +823,20 @@ FillExchangeInfoData (
> >// Copy all 32-bit code and 64-bit code into memory with type of
> >// EfiBootServicesCode to avoid page fault if NX memory protection is
> enabled.
> >//
> > -  if (ExchangeInfo->ModeTransitionMemory != 0) {
> > +  if (CpuMpData->WakeupBufferHigh != 0) {
> >  Size = CpuMpData->AddressMap.RendezvousFunnelSize -
> > CpuMpData->AddressMap.ModeTransitionOffset;
> >  CopyMem (
> > -  (VOID *)(UINTN)ExchangeInfo->ModeTransitionMemory,
> > +  (VOID *)CpuMpData->WakeupBufferHigh,
> >CpuMpData->AddressMap.RendezvousFunnelAddress +
> >CpuMpData->AddressMap.ModeTransitionOffset,
> >Size
> >);
> >
> > -ExchangeInfo->ModeHighMemory = ExchangeInfo-
> >ModeTransitionMemory;
> > -ExchangeInfo->ModeHighMemory += (UINT32)ExchangeInfo->ModeOffset
> -
> > -   (UINT32)CpuMpData->AddressMap.ModeTransitionOffset;
> > +ExchangeInfo->ModeTransitionMemory = (UINT32)CpuMpData-
> >WakeupBufferHigh;
> > +ExchangeInfo->ModeHighMemory = (UINT32)CpuMpData-
> >WakeupBufferHigh +
> > +   (UINT32)ExchangeInfo->ModeOffset -
> > +   
> > (UINT32)CpuMpData->AddressMap.ModeTransitionOffset;
> >  ExchangeInfo->ModeHighSegment = (UINT16)ExchangeInfo->CodeSegment;
> >} else {
> >  ExchangeInfo->ModeTransitionMemory = (UINT32)
> > @@ -916,11 +917,10 @@ AllocateResetVector (
> >  CpuMpData->WakeupBuffer  = GetWakeupBuffer (ApResetVectorSize);
> >  CpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN)
> >  (CpuMpData->WakeupBuffer + CpuMpData-
> >AddressMap.RendezvousFunnelSize);
> > -CpuMpData->MpCpuExchangeInfo->ModeTransitionMemory = (UINT32)
> > -GetModeTransitionBuffer (
> > -  CpuMpData->AddressMap.RendezvousFunnelSize -
> > -  CpuMpData->AddressMap.ModeTransitionOffset
> > -  );
> > +CpuMpData->WakeupBufferHigh  = GetModeTransitionBuffer (
> > +
> > CpuMpData->AddressMap.RendezvousFunnelSize -
> > +
> > CpuMpData->AddressMap.ModeTransitionOffset
> > +);
> >}
> >BackupAndPrepareWakeupBuffer (CpuMpData);
> >  }
> > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h
> b/UefiCpuPkg/Library/MpInitLib/MpLib.h
> > index 0232fe896a..e7f9a4de0a 100644
> > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h
> > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h
> > @@ -208,6 +208,7 @@ struct _CPU_MP_DATA {
> >UINTN  CpuApStackSize;
> >   

Re: [edk2] [PATCH edk2-platforms v1 04/14] Hisilicon D03/D05: Add capsule upgrade support

[Huangming (Mark)]

On 2018/1/24 19:21, Ard Biesheuvel wrote:
> On 24 January 2018 at 11:10, Huangming (Mark)  wrote:
>>
>>
>> On 2018/1/20 18:50, Ard Biesheuvel wrote:
>>> On 18 January 2018 at 15:01, Ming Huang  wrote:
 From: Jason Zhang 

 Contributed-under: TianoCore Contribution Agreement 1.1
 Signed-off-by: Jason Zhang 
 Signed-off-by: Ming Huang 
 Signed-off-by: Heyi Guo 
 ---
  
 Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
  |  45 +
  Platform/Hisilicon/D03/D03.dsc
|  17 +++-
  Platform/Hisilicon/D03/D03.fdf
|  70 +
  
 Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
  |  45 +
  Platform/Hisilicon/D05/D05.dsc
|  19 +++-
  Platform/Hisilicon/D05/D05.fdf
|  70 +
  
 Silicon/Hisilicon/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
  |  81 +++
  
 Silicon/Hisilicon/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
   |  50 +
  
 Silicon/Hisilicon/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
  |  70 +
  Silicon/Hisilicon/Hisilicon.dsc.inc   
|  11 +-
  Silicon/Hisilicon/Hisilicon.fdf.inc   
|   9 ++
  
 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c
  | 106 
  
 Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf
|  51 ++
  13 files changed, 641 insertions(+), 3 deletions(-)

>>>
>>> Excellent!! Very happy to see this added.
>>>
 diff --git 
 a/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
  
 b/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
 new file mode 100644
 index 000..fc834d9
 --- /dev/null
 +++ 
 b/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
 @@ -0,0 +1,45 @@
 +#
 +#  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
 +#  Copyright (c) 2018, Linaro Limited. All rights reserved.
 +#  Copyright (c) 2016, Intel Corporation. All rights reserved.
 +#
 +#  This program and the accompanying materials
 +#  are licensed and made available under the terms and conditions of the 
 BSD License
 +#  which accompanies this distribution.  The full text of the license may 
 be found at
 +#  http://opensource.org/licenses/bsd-license.php
 +#
 +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
 IMPLIED.
 +#
 +##
 +
 +[Head]
 +NumOfUpdate = 3
 +NumOfRecovery = 0
 +Update0 = SysFvMain
 +Update1 = SysCustom
 +Update2 = SysNvRam
 +
 +[SysFvMain]
 +FirmwareType  = 0 # 0 - SystemFirmware, 1 - NvRam
 +AddressType   = 0 # 0 - relative address, 1 - absolute 
 address.
 +BaseAddress   = 0x# Base address offset on flash
 +Length= 0x002D# Length
 +ImageOffset   = 0x# Image offset of this SystemFirmware image
 +FileGuid  = 642e4fcf-2df7-4415-8b70-a03909c57b55  # 
 PcdEdkiiSystemFirmwareFileGuid
 +
 +[SysCustom]
 +FirmwareType  = 0 # 0 - SystemFirmware, 1 - NvRam
 +AddressType   = 0 # 0 - relative address, 1 - absolute 
 address.
 +BaseAddress   = 0x002F# Base address offset on flash
 +Length= 0x0001# Length
 +ImageOffset   = 0x002F# Image offset of this SystemFirmware image
 +FileGuid  = 642e4fcf-2df7-4415-8b70-a03909c57b55  # 
 PcdEdkiiSystemFirmwareFileGuid
 +
 +[SysNvRam]
 +FirmwareType  = 1 # 0 - SystemFirmware, 1 - NvRam
 +AddressType   = 0 # 0 - relative address, 1 - absolute 
 address.
 +BaseAddress   = 0x002D# Base address offset on flash
 +Length= 0x0002# Length
 +ImageOffset   = 0x002D# Image offset of this SystemFirmware image
 +FileGuid  = 642e4fcf-2df7-4415-8b70-a03909c57b55  # 
 PcdEdkiiSystemFirmwareFileGuid
 diff --git a/Platform/Hisilicon/D03/D03.dsc 
 

[edk2] [PATCH] CorebootPayloadPkg: Use correct BytesPerScanLine

[arthur]

From: Arthur Heymans 

Fetch BytesPerScanLine from coreboot table to reflect how the actual
framebuffer is set up instead of guessing it from the horizontal
resolution.

This fixes a garbled display when HorizontalResolution * (BitsPerPixel
/ 8) and pFbInfo->BytesPerScanLine don't match.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Arthur Heymans 

diff --git a/CorebootPayloadPkg/FbGop/FbGop.c b/CorebootPayloadPkg/FbGop/FbGop.c
index 37d6def7f7..6790617033 100644
--- a/CorebootPayloadPkg/FbGop/FbGop.c
+++ b/CorebootPayloadPkg/FbGop/FbGop.c
@@ -822,7 +822,7 @@ FbGopCheckForVbe (
   BitsPerPixel = pFbInfo->BitsPerPixel;
   HorizontalResolution = pFbInfo->HorizontalResolution;
   VerticalResolution   = pFbInfo->VerticalResolution;
-  BytesPerScanLine = HorizontalResolution * (BitsPerPixel / 8);
+  BytesPerScanLine = pFbInfo->BytesPerScanLine;
   
   ModeBuffer = (FB_VIDEO_MODE_DATA *) AllocatePool (


ModeNumber * sizeof (FB_VIDEO_MODE_DATA)
-- 
2.16.1

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Re: [edk2] setting the TLS cipher list for HTTPS booting

[Laszlo Ersek]

On 01/24/18 07:50, Wu, Jiaxin wrote:
> Hi Laszlo,
> 
> After the discussion with team member, we still prefer to use the PCD
> solution. In HttpDxe driver, we don't want to locate/use a
> nonstandard protocol. We think It's not a general solution for the
> UEFI driver.
Ah, I totally missed that NetworkPkg/HttpDxe was a UEFI_DRIVER! :)

In that case, I think *neither* the LocateProtocol() call for an
edk2-specific protocol, *nor* a PcdGetPtr() call are appropriate.
UEFI_DRIVER modules should preferably only use facilities from the UEFI
spec, and the protocol for the dynamic PCDs comes from the PI spec, not
the UEFI spec.

(This would be different if HttpDxe was a DXE_DRIVER -- in that case
both approaches would be valid. I assumed HttpDxe was a DXE_DRIVER, not
sure why.)

(1) So, given that HttpDxe is a UEFI_DRIVER, I think the right approach
would be -- which I believe I also mentioned earlier -- to introduce
another UEFI variable for the list of cipher suites, similarly to
"TlsCaCertificate" (in a custom variable namespace GUID). This would
stay within the framework of the UEFI spec.


(2) Regarding the order between setting these UEFI variables in OVMF,
and consuming them in HttpDxe, I think your argument is good. We can set
the variables in some platform code (DXE_DRIVER) in OVMF, before
End-of-DXE, and HttpDxe will only read them later in BDS.

"OvmfPkg/PlatformDxe" seems like a good candidate for setting these
variables (both considering PlatformDxe's purpose, and because it
already depends on "gEfiVariableWriteArchProtocolGuid").


(3) Regardig the format (EFI_TLS_CIPHER): I agree with you. It seems we
can modify the host environment to pass QEMU (and OVMF) a cipher list
that is already in EFI_TLS_CIPHER format.


So I think the only remaining question is if you like a new UEFI
variable instead of the dynamic PCD, for the cipher list.

Thanks!
Laszlo



> 
> Thanks,
> Jiaxin
> 
>> -Original Message-
>> From: Wu, Jiaxin
>> Sent: Wednesday, January 24, 2018 11:40 AM
>> To: Wu, Jiaxin ; Laszlo Ersek ; Fu,
>> Siyuan ; Ye, Ting ; Long, Qin
>> ; Yao, Jiewen ; Hsiung, Harry L
>> 
>> Cc: edk2-devel-01 
>> Subject: RE: setting the TLS cipher list for HTTPS booting
>>
>> Hi Laszlo,
>>
>> More comments:
>>
>>>
>>> Dynamic PCDs is just one of the solutions for the required settings, just 
>>> like
>> the
>>> platform protocol (HTTPS_CONFIG_PROTOCOL), provides the capability to
>>> support the global HTTPS configuration.
>>>
>>> Each solutions have its own advantages and disadvantages:
>>> 1) PCD can simplify the problem and it's easy to use for the other platform
>> not
>>> only OVMF, but as you said, it's perhaps overkill.
>>> 2) The additional platform protocol looks flexible and reasonably, but it
>> makes
>>> the specific platform have the optional dependency ["OVMF hooks a NULL-
>> class
>>> library into HttpDxe that introduces a new DEPEX on the protocol. Other
>>> platforms would not delay HttpDxe."]. If the user doesn't want HTTPS feature
>>> but only HTTP, it has to include one NULL protocol.
>>>
>>
>> I checked the PciHostBridgeDxe driver to call the EDKII_IOMMU_PROTOCOL,
>> which makes me better understanding your comments.
>>
>>   MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
>> 
>>   ...
>>   NULL|OvmfPkg/Library/PlatformHasIoMmuLib/PlatformHasIoMmuLib.inf
>>   }
>>
>> So, as you said, it's just the platform behavior so as to hook the platform
>> produces the EDKII_IOMMU_PROTOCOL protocol first, then dispatch
>> PciHostBridgeDxe driver. That's good to me.
>>
>> For HTTPS configuration, the HttpDxe configuration is only happened during 
>> the
>> protocol instance calling, which is created by service binding protocol. So, 
>> it
>> looks only happened after EndofDxe phase. If so, it will be no such optional
>> dependency to wait for the platform DXE driver produces the
>> EDKII_PLATFORM_HTTPS_CONFIG_PROTOCOL.
>>
>> Anyway, for above two solutions, I need review them with other colleagues and
>> help to collect the comments for both of them, then feedback to you. Thank 
>> you
>> so such.
>>
>>
>>> Now, I think we are discussing the most appropriate way for the HTTPS
>>> controlling. It's NOT related to who should be responsible for the solution
>>> coding, you know we are always thinking from the user's perspective:).
>>>
>>>
>
> If you really think that HttpDxe should only care about these two items
> (CA cert and cipher list), then I have another question: do you think it
> makes sense to introduce another non-volatile UEFI variable, for the
> cipher suites too? This would make things uniform, and perhaps
> TlsAuthConfigDxe could expose the cipher suites too, as a list of
> checkboxes. Just an idea.

 So, apparently we indeed care about these two options 

Re: [edk2] [patch 1/3] UefiCpuPkg/S3Resume: Remove useless pref code

[Laszlo Ersek]

On 01/24/18 09:01, Dandan Bi wrote:
> Our new performance infrastructure can support to dump performance
> date form ACPI table in OS. So we can remove the old pref code to
> write performance data to OS.
> 
> Cc: Eric Dong 
> Cc: Laszlo Ersek 
> Cc: Liming Gao 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Dandan Bi 
> ---
>  UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c  | 131 
> -
>  .../Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf   |   3 +-
>  2 files changed, 1 insertion(+), 133 deletions(-)
> 
> diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c 
> b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
> index d7d2a4d..4d77689 100644
> --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
> +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
> @@ -20,11 +20,10 @@
>  
>  #include 
>  
>  #include 
>  #include 
> -#include 
>  #include 
>  #include 
>  #include 
>  #include 
>  #include 
> @@ -284,136 +283,10 @@ GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT mGdtEntries[] = 
> {
>  GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt = {
>sizeof (mGdtEntries) - 1,
>(UINTN) mGdtEntries
>};
>  
> -/**
> -  Performance measure function to get S3 detailed performance data.
> -
> -  This function will getS3 detailed performance data and saved in 
> pre-reserved ACPI memory.
> -**/
> -VOID
> -WriteToOsS3PerformanceData (
> -  VOID
> -  )
> -{
> -  EFI_STATUSStatus;
> -  EFI_PHYSICAL_ADDRESS  mAcpiLowMemoryBase;
> -  PERF_HEADER   *PerfHeader;
> -  PERF_DATA *PerfData;
> -  UINT64Ticker;
> -  UINTN Index;
> -  EFI_PEI_READ_ONLY_VARIABLE2_PPI   *VariableServices;
> -  UINTN VarSize;
> -  UINTN LogEntryKey;
> -  CONST VOID*Handle;
> -  CONST CHAR8   *Token;
> -  CONST CHAR8   *Module;
> -  UINT64StartTicker;
> -  UINT64EndTicker;
> -  UINT64StartValue;
> -  UINT64EndValue;
> -  BOOLEAN   CountUp;
> -  UINT64Freq;
> -
> -  //
> -  // Retrieve time stamp count as early as possible
> -  //
> -  Ticker = GetPerformanceCounter ();
> -
> -  Freq   = GetPerformanceCounterProperties (, );
> -
> -  Freq   = DivU64x32 (Freq, 1000);
> -
> -  Status = PeiServicesLocatePpi (
> - ,
> - 0,
> - NULL,
> - (VOID **) 
> - );
> -  if (EFI_ERROR (Status)) {
> -return;
> -  }
> -
> -  VarSize   = sizeof (EFI_PHYSICAL_ADDRESS);
> -  Status = VariableServices->GetVariable (
> -   VariableServices,
> -   L"PerfDataMemAddr",
> -   ,
> -   NULL,
> -   ,
> -   
> -   );
> -  if (EFI_ERROR (Status)) {
> -DEBUG ((EFI_D_ERROR, "Fail to retrieve variable to log S3 performance 
> data \n"));
> -return;
> -  }
> -
> -  PerfHeader = (PERF_HEADER *) (UINTN) mAcpiLowMemoryBase;
> -
> -  if (PerfHeader->Signiture != PERFORMANCE_SIGNATURE) {
> -DEBUG ((EFI_D_ERROR, "Performance data in ACPI memory get corrupted! 
> \n"));
> -return;
> -  }
> -
> -  //
> -  // Record total S3 resume time.
> -  //
> -  if (EndValue >= StartValue) {
> -PerfHeader->S3Resume = Ticker - StartValue;
> -CountUp  = TRUE;
> -  } else {
> -PerfHeader->S3Resume = StartValue - Ticker;
> -CountUp  = FALSE;
> -  }
> -
> -  //
> -  // Get S3 detailed performance data
> -  //
> -  Index = 0;
> -  LogEntryKey = 0;
> -  while ((LogEntryKey = GetPerformanceMeasurement (
> -  LogEntryKey,
> -  ,
> -  ,
> -  ,
> -  ,
> -  )) != 0) {
> -if (EndTicker != 0) {
> -  PerfData = >S3Entry[Index];
> -
> -  //
> -  // Use File Handle to specify the different performance log for PEIM.
> -  // File Handle is the base address of PEIM FFS file.
> -  //
> -  if ((AsciiStrnCmp (Token, "PEIM", PEI_PERFORMANCE_STRING_SIZE) == 0) 
> && (Handle != NULL)) {
> -AsciiSPrint (PerfData->Token, PERF_TOKEN_LENGTH, "0x%11p", Handle);
> -  } else {
> -AsciiStrnCpyS (PerfData->Token, PERF_TOKEN_SIZE, Token, 
> PERF_TOKEN_LENGTH);
> -

Re: [edk2] [patch] UefiCpuPkg/S3Resume: Add more perf enrty for S3 phase

[Laszlo Ersek]

On 01/24/18 08:59, Dandan Bi wrote:
> Add more perf entry to hook BootScriptDonePpi/EndOfPeiPpi/
> EndOfS3Resume.
> 
> Notes: This patch depends on the new performance
> infrastructure.

Since this statement is going into the commit log, please be more
specific about the "new performance infrastructure" (TianoCore BZ or
commit hashes etc).

Also, how is the dependency established? For example, OVMF uses
BasePerformanceLibNull; so I think it will see no changes.

Do you mean the PERF_INMODULE_START_ID macro, from
"ExtendedFirmwarePerformance.h"? Ah, that's not committed yet. In this
case, please add a reference to the mailing list message (subject and
archive URL) that adds it.

(Actually, the best solution is to reference the TianoCore BZ, and then
add the mailing list URL for each patch set submission to the TianoCore BZ.)

> 
> Cc: Eric Dong 
> Cc: Laszlo Ersek 
> Cc: Liming Gao 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Dandan Bi 
> ---
>  UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 15 ++-
>  1 file changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c 
> b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
> index b597ac7..d7d2a4d 100644
> --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
> +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
> @@ -2,11 +2,11 @@
>This module produces the EFI_PEI_S3_RESUME2_PPI.
>This module works with StandAloneBootScriptExecutor to S3 resume to OS.
>This module will execute the boot script saved during last boot and after 
> that,
>control is passed to OS waking up handler.
>  
> -  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
> +  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
>Copyright (c) 2017, AMD Incorporated. All rights reserved.
>  
>This program and the accompanying materials
>are licensed and made available under the terms and conditions
>of the BSD License which accompanies this distribution.  The
> @@ -21,10 +21,11 @@
>  #include 
>  
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
>  #include 
>  #include 
> @@ -551,13 +552,17 @@ S3ResumeBootOs (
>PERF_END (NULL, "ScriptExec", NULL, 0);
>  
>//
>// Install BootScriptDonePpi
>//
> +  PERF_START_EX (NULL, "BootScriptDonePpi", NULL, 0, PERF_INMODULE_START_ID);
> +

My question here is not really specific to this patch, but I guess
asking it this time is just as good as any other time:

- Why do we pass NULL for Module, rather than gEfiCallerBaseName?

- We already have START and END calls for the performance measurement;
why do we use different Identifier values for the records added?

(These questions are more for my education than about possible issues in
the patch.)

Thanks!
Laszlo


>Status = PeiServicesInstallPpi ();
>ASSERT_EFI_ERROR (Status);
>  
> +  PERF_END_EX (NULL, "BootScriptDonePpi", NULL, 0, PERF_INMODULE_END_ID);
> +
>//
>// Get ACPI Table Address
>//
>Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) 
> (AcpiS3Context->AcpiFacsTable));
>  
> @@ -576,18 +581,26 @@ S3ResumeBootOs (
>}
>  
>//
>// Install EndOfPeiPpi
>//
> +  PERF_START_EX (NULL, "EndOfPeiPpi", NULL, 0, PERF_INMODULE_START_ID);
> +
>Status = PeiServicesInstallPpi ();
>ASSERT_EFI_ERROR (Status);
>  
> +  PERF_END_EX (NULL, "EndOfPeiPpi", NULL, 0, PERF_INMODULE_END_ID);
> +
>//
>// Signal EndOfS3Resume event.
>//
> +  PERF_START_EX (NULL, "EndOfS3Resume", NULL, 0, PERF_INMODULE_START_ID);
> +
>SignalEndOfS3Resume ();
>  
> +  PERF_END_EX (NULL, "EndOfS3Resume", NULL, 0, PERF_INMODULE_END_ID);
> +
>//
>// report status code on S3 resume
>//
>REPORT_STATUS_CODE (EFI_PROGRESS_CODE, EFI_SOFTWARE_PEI_MODULE | 
> EFI_SW_PEI_PC_OS_WAKE);
>  
> 

___
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Re: [edk2] [PATCH] UefiCpuPkg/MpInitLib: fix issue in wakeup buffer initialization

[Laszlo Ersek]

On 01/24/18 03:08, Jian J Wang wrote:
> To fix an issue in which enabling NX feature will mark the AP wakeup
> buffer as non-executable and fail the AP init, the buffer was split
> into two part: the lower part in memory within 1MB and the higher part
> within allocated executable memory (EfiBootServicesCode). But the
> address of higher part memory was stored in lower part memory, which
> is actually shared with legacy components and will be overwritten by
> LegacyBiosDxe driver if CSM is enabled.
> 
> This patch fixes this issue by storing the address of higher part
> memory in CpuMpData instead of ExchangeInfo.
> 
> Cc: Ruiyu Ni 
> Cc: Eric Dong 
> Cc: Laszlo Ersek 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Jian J Wang 
> ---
>  UefiCpuPkg/Library/MpInitLib/MpLib.c | 20 ++--
>  UefiCpuPkg/Library/MpInitLib/MpLib.h |  1 +
>  2 files changed, 11 insertions(+), 10 deletions(-)
> 
> diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c 
> b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> index 6231968c74..42011d6231 100644
> --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> @@ -823,19 +823,20 @@ FillExchangeInfoData (
>// Copy all 32-bit code and 64-bit code into memory with type of
>// EfiBootServicesCode to avoid page fault if NX memory protection is 
> enabled.
>//
> -  if (ExchangeInfo->ModeTransitionMemory != 0) {
> +  if (CpuMpData->WakeupBufferHigh != 0) {
>  Size = CpuMpData->AddressMap.RendezvousFunnelSize -
> CpuMpData->AddressMap.ModeTransitionOffset;
>  CopyMem (
> -  (VOID *)(UINTN)ExchangeInfo->ModeTransitionMemory,
> +  (VOID *)CpuMpData->WakeupBufferHigh,
>CpuMpData->AddressMap.RendezvousFunnelAddress +
>CpuMpData->AddressMap.ModeTransitionOffset,
>Size
>);
>  
> -ExchangeInfo->ModeHighMemory = ExchangeInfo->ModeTransitionMemory;
> -ExchangeInfo->ModeHighMemory += (UINT32)ExchangeInfo->ModeOffset -
> -   (UINT32)CpuMpData->AddressMap.ModeTransitionOffset;
> +ExchangeInfo->ModeTransitionMemory = (UINT32)CpuMpData->WakeupBufferHigh;
> +ExchangeInfo->ModeHighMemory = (UINT32)CpuMpData->WakeupBufferHigh +
> +   (UINT32)ExchangeInfo->ModeOffset -
> +   
> (UINT32)CpuMpData->AddressMap.ModeTransitionOffset;
>  ExchangeInfo->ModeHighSegment = (UINT16)ExchangeInfo->CodeSegment;
>} else {
>  ExchangeInfo->ModeTransitionMemory = (UINT32)
> @@ -916,11 +917,10 @@ AllocateResetVector (
>  CpuMpData->WakeupBuffer  = GetWakeupBuffer (ApResetVectorSize);
>  CpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN)
>  (CpuMpData->WakeupBuffer + 
> CpuMpData->AddressMap.RendezvousFunnelSize);
> -CpuMpData->MpCpuExchangeInfo->ModeTransitionMemory = (UINT32)
> -GetModeTransitionBuffer (
> -  CpuMpData->AddressMap.RendezvousFunnelSize -
> -  CpuMpData->AddressMap.ModeTransitionOffset
> -  );
> +CpuMpData->WakeupBufferHigh  = GetModeTransitionBuffer (
> +
> CpuMpData->AddressMap.RendezvousFunnelSize -
> +
> CpuMpData->AddressMap.ModeTransitionOffset
> +);
>}
>BackupAndPrepareWakeupBuffer (CpuMpData);
>  }
> diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h 
> b/UefiCpuPkg/Library/MpInitLib/MpLib.h
> index 0232fe896a..e7f9a4de0a 100644
> --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h
> +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h
> @@ -208,6 +208,7 @@ struct _CPU_MP_DATA {
>UINTN  CpuApStackSize;
>MP_ASSEMBLY_ADDRESS_MAPAddressMap;
>UINTN  WakeupBuffer;
> +  UINTN  WakeupBufferHigh;
>UINTN  BackupBuffer;
>UINTN  BackupBufferSize;
>  
> 

As far as I see, all the values stored by FillExchangeInfoData() remain
the same. The difference is that "ModeTransitionMemory" becomes an
*output* field for FillExchangeInfoData(), from being an input field. We
now explicitly store the value to it that we previously *assumed* it
would hold (preserve), from AllocateResetVector().

The input now comes through WakeupBufferHigh, from the
AllocateResetVector() function.

Thus, I think the patch could have been written a bit more simply: we
could have added the assignment

ExchangeInfo->ModeTransitionMemory = (UINT32)CpuMpData->WakeupBufferHigh

before the "if" in FillExchangeInfoData(), and then the rest of
FillExchangeInfoData() would have needed no changes. But perhaps that
would have been harder to understand.

Reviewed-by: Laszlo Ersek 

Thanks
Laszlo
___

Re: [edk2] [PATCH edk2-platforms v1 01/14] Hisilicon/D05: Add PPTT support

[graeme . gregory]

On Mon, Jan 22, 2018 at 01:53:18PM +, Leif Lindholm wrote:
> Detailed commit description, please.
> 
> Graeme - any comments on ACPIness?
> 
I think Jeremy probably gave it a much more in depth review than I can
below.

Once he is happy Ill be happy.

Graeme

> On Thu, Jan 18, 2018 at 11:01:30PM +0800, Ming Huang wrote:
> > From: Jason Zhang 
> > 
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Jason Zhang 
> > Signed-off-by: Ming Huang 
> > Signed-off-by: Heyi Guo 
> > ---
> >  Platform/Hisilicon/D05/D05.dsc  |   1 +
> >  Platform/Hisilicon/D05/D05.fdf  |   1 +
> >  Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h |  27 ++
> >  Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc  |  31 +-
> >  Silicon/Hisilicon/Hi1616/Pptt/Pptt.c| 447 
> > 
> >  Silicon/Hisilicon/Hi1616/Pptt/Pptt.h| 142 +++
> >  Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf  |  55 +++
> >  7 files changed, 677 insertions(+), 27 deletions(-)
> > 
> > diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
> > index 77a89fd..710339c 100644
> > --- a/Platform/Hisilicon/D05/D05.dsc
> > +++ b/Platform/Hisilicon/D05/D05.dsc
> > @@ -506,6 +506,7 @@
> >MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
> >  
> >Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
> > +  Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
> >Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
> >  
> >#
> > diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
> > index 78ab0c8..97de4d2 100644
> > --- a/Platform/Hisilicon/D05/D05.fdf
> > +++ b/Platform/Hisilicon/D05/D05.fdf
> > @@ -241,6 +241,7 @@ READ_LOCK_STATUS   = TRUE
> >INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
> >  
> >INF RuleOverride=ACPITABLE 
> > Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
> > +  INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf
> >INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
> >  
> >#
> > diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h 
> > b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
> > index 808219a..f1927e8 100644
> > --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
> > +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
> 
> As far as I can tell, all of the changes to this file (and the
> resulting counterpart in
> Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc) are
> non-functional.
> 
> Please break these changes out as a separate patch.
> This is good cleanup, but unrelated to the stated change.
> 
> > @@ -19,6 +19,7 @@
> >  
> >  #ifndef _HI1610_PLATFORM_H_
> >  #define _HI1610_PLATFORM_H_
> > +#include 
> >  
> >  //
> >  // ACPI table information used to initialize tables.
> > @@ -44,5 +45,31 @@
> >}
> >  
> >  #define HI1616_WATCHDOG_COUNT  2
> > +#define HI1616_GIC_STRUCTURE_COUNT  64
> > +
> > +#define HI1616_MPID_TA_BASE  0x1
> > +#define HI1616_MPID_TB_BASE  0x3
> > +#define HI1616_MPID_TA_2_BASE  0x5
> > +#define HI1616_MPID_TB_2_BASE  0x7
> > +
> > +// Differs from Juno, we have another affinity level beyond cluster and 
> > core
> > +#define PLATFORM_GET_MPID_TA(ClusterId, CoreId)   (HI1616_MPID_TA_BASE | 
> > ((ClusterId) << 8) | (CoreId))
> > +#define PLATFORM_GET_MPID_TB(ClusterId, CoreId)   (HI1616_MPID_TB_BASE | 
> > ((ClusterId) << 8) | (CoreId))
> > +#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId)   (HI1616_MPID_TA_2_BASE 
> > | ((ClusterId) << 8) | (CoreId))
> > +#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId)   (HI1616_MPID_TB_2_BASE 
> > | ((ClusterId) << 8) | (CoreId))
> > +
> > +//
> > +// Multiple APIC Description Table
> > +//
> > +#pragma pack (1)
> > +
> > +typedef struct {
> > +  EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
> > +  EFI_ACPI_6_1_GIC_STRUCTURE
> > GicInterfaces[HI1616_GIC_STRUCTURE_COUNT];
> > +  EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
> > +  EFI_ACPI_6_1_GIC_ITS_STRUCTUREGicITS[8];
> > +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
> > +
> > +#pragma pack ()
> >  
> >  #endif
> > diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc 
> > b/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
> > index 169ee72..33dca03 100644
> > --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
> > +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
> > @@ -1,9 +1,9 @@
> >  /** @file
> >  *  Multiple APIC Description Table (MADT)
> >  *
> > -*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
> > -*  Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved.
> > -*  Copyright (c) 2015 - 2016, Linaro Limited. 

Re: [edk2] [PATCH edk2-platforms v1 06/14] Hisilicon D03/D05: Open SnpPlatform source code

[Leif Lindholm]

On Wed, Jan 24, 2018 at 08:31:38PM +0800, Huangming (Mark) wrote:
> On 2018/1/23 22:07, Leif Lindholm wrote:
> > On Thu, Jan 18, 2018 at 11:01:35PM +0800, Ming Huang wrote:
> >> From: Jason Zhang 
> >>
> >> 1. Open driver source code.
> > 
> > Please describe what this driver does.
> > 
> >> 2. This code includes network sequence correction
> >>solution.
> > 
> > Which correction?
> > Is there an existing bug report somewhere this can refer to?
> > 
> > .
> > 
> 
> Fixed bug:Confusing Ethernet port sequence.
> Move the most right Ethernet port (when looking from the front of the chassis)
> to the first one in BootManage for PXE boot.
> https://bugs.linaro.org/show_bug.cgi?id=2657

Yes, that works - please add in v2.

/
Leif
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Re: [edk2] [PATCH edk2-platforms v1 06/14] Hisilicon D03/D05: Open SnpPlatform source code

[Huangming (Mark)]

On 2018/1/23 22:07, Leif Lindholm wrote:
> On Thu, Jan 18, 2018 at 11:01:35PM +0800, Ming Huang wrote:
>> From: Jason Zhang 
>>
>> 1. Open driver source code.
> 
> Please describe what this driver does.
> 
>> 2. This code includes network sequence correction
>>solution.
> 
> Which correction?
> Is there an existing bug report somewhere this can refer to?
> 
> .
> 

Fixed bug:Confusing Ethernet port sequence.
Move the most right Ethernet port (when looking from the front of the chassis)
to the first one in BootManage for PXE boot.
https://bugs.linaro.org/show_bug.cgi?id=2657

Thanks.

-- 
Best Regards,

Ming

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Re: [edk2] [PATCH v2] Silicon/SynQuacer/PlatformDxe: enable spread spectrum mode for ASM1061 SATA

[Leif Lindholm]

On Wed, Jan 24, 2018 at 11:57:11AM +, Ard Biesheuvel wrote:
> The ASM1061 SATA controller integrated into the DeveloperBox board
> emits too much electromagnetic radiation, so it needs spread spectrum
> mode enabled.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel 

Reviewed-by: Leif Lindholm 

> ---
> v2: - rename AsmediaXXX.c to Pci.c
> - rename RegisterAsm1184Notifier() to RegisterPciIoNotifier() and make
>   its invocation unconditional (rather than only if PCI domain #0 is
>   not limited to Gen1 speed)
> - use switch() rather than if() in PID/VID check

Thanks!

> 
>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/{Asmedia118x.c => Pci.c} | 
> 87 +++-
>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c| 
> 18 ++--
>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h|  
> 5 +-
>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf  |  
> 2 +-
>  4 files changed, 80 insertions(+), 32 deletions(-)
> 
> diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c 
> b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c
> similarity index 63%
> rename from Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c
> rename to Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c
> index c4cbacd3dff9..7ac96ab22b7a 100644
> --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c
> +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c
> @@ -15,9 +15,12 @@
>  #include "PlatformDxe.h"
>  
>  #define ASMEDIA_VID 0x1b21
> +#define ASM1061_PID 0x0612
>  #define ASM1182E_PID0x1182
>  #define ASM1184E_PID0x1184
>  
> +#define ASM1061_SSC_OFFSET  0xA10
> +
>  #define ASM118x_PCIE_CAPABILITY_OFFSET  0x80
>  #define ASM118x_PCIE_LINK_CONTROL_OFFSET(ASM118x_PCIE_CAPABILITY_OFFSET 
> + \
>   OFFSET_OF 
> (PCI_CAPABILITY_PCIEXP, \
> @@ -39,24 +42,10 @@ RetrainAsm1184eDownstreamPort (
>IN  EFI_PCI_IO_PROTOCOL   *PciIo
>)
>  {
> -  UINT16PciVidPid[2];
>EFI_STATUSStatus;
>PCIE_CAP  Cap;
>PCI_REG_PCIE_LINK_CONTROL LinkControl;
>  
> -  Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET,
> -ARRAY_SIZE (PciVidPid), );
> -  if (EFI_ERROR (Status)) {
> -DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n",
> -  __FUNCTION__, Status));
> -return;
> -  }
> -
> -  if (PciVidPid[0] != ASMEDIA_VID ||
> -  (PciVidPid[1] != ASM1182E_PID && PciVidPid[1] != ASM1184E_PID)) {
> -return;
> -  }
> -
>//
>// The upstream and downstream ports share the same PID/VID, so check
>// the port type. This assumes the PCIe Express capability block lives
> @@ -91,6 +80,34 @@ RetrainAsm1184eDownstreamPort (
>  
>  STATIC
>  VOID
> +EnableAsm1061SpreadSpectrum (
> +  IN  EFI_PCI_IO_PROTOCOL   *PciIo
> +  )
> +{
> +  EFI_STATUS  Status;
> +  UINT8   SscVal;
> +
> +  DEBUG ((DEBUG_INFO, "%a: enabling spread spectrum mode 0 for ASM1061\n",
> +__FUNCTION__));
> +
> +  // SSC mode 0~-4000 ppm, 1:1 modulation
> +
> +  SscVal = 0;
> +  Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ASM1061_SSC_OFFSET, 
> 1,
> +);
> +  ASSERT_EFI_ERROR (Status);
> +
> +  MemoryFence ();
> +  gBS->Stall (1); // delay at least 100 ns between writes of the same 
> register
> +
> +  SscVal = 1;
> +  Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ASM1061_SSC_OFFSET, 
> 1,
> +);
> +  ASSERT_EFI_ERROR (Status);
> +}
> +
> +STATIC
> +VOID
>  EFIAPI
>  OnPciIoProtocolNotify (
>IN EFI_EVENT  Event,
> @@ -101,6 +118,7 @@ OnPciIoProtocolNotify (
>EFI_STATUSStatus;
>EFI_HANDLEHandleBuffer;
>UINTN BufferSize;
> +  UINT16PciVidPid[2];
>  
>while (TRUE) {
>  BufferSize = sizeof (EFI_HANDLE);
> @@ -114,18 +132,45 @@ OnPciIoProtocolNotify (
>  (VOID **));
>  ASSERT_EFI_ERROR (Status);
>  
> -//
> -// The ASM1184E 4-port PCIe switch on the DeveloperBox board (and its
> -// 2-port sibling of which samples were used in development) needs a
> -// little nudge to get it to train the downstream links at Gen2 speed.
> -//
> -RetrainAsm1184eDownstreamPort (PciIo);
> +Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 
> PCI_VENDOR_ID_OFFSET,
> +  ARRAY_SIZE (PciVidPid), );
> +if (EFI_ERROR (Status)) {
> +  DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n",
> +__FUNCTION__, Status));
> +  continue;
> +}
> +
> +if (PciVidPid[0] != ASMEDIA_VID) {
> +   

[edk2] [PATCH v2] Silicon/SynQuacer/PlatformDxe: enable spread spectrum mode for ASM1061 SATA

[Ard Biesheuvel]

The ASM1061 SATA controller integrated into the DeveloperBox board
emits too much electromagnetic radiation, so it needs spread spectrum
mode enabled.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
---
v2: - rename AsmediaXXX.c to Pci.c
- rename RegisterAsm1184Notifier() to RegisterPciIoNotifier() and make
  its invocation unconditional (rather than only if PCI domain #0 is
  not limited to Gen1 speed)
- use switch() rather than if() in PID/VID check

 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/{Asmedia118x.c => Pci.c} | 87 
+++-
 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c| 18 
++--
 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h|  5 
+-
 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf  |  2 
+-
 4 files changed, 80 insertions(+), 32 deletions(-)

diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c 
b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c
similarity index 63%
rename from Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c
rename to Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c
index c4cbacd3dff9..7ac96ab22b7a 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c
+++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c
@@ -15,9 +15,12 @@
 #include "PlatformDxe.h"
 
 #define ASMEDIA_VID 0x1b21
+#define ASM1061_PID 0x0612
 #define ASM1182E_PID0x1182
 #define ASM1184E_PID0x1184
 
+#define ASM1061_SSC_OFFSET  0xA10
+
 #define ASM118x_PCIE_CAPABILITY_OFFSET  0x80
 #define ASM118x_PCIE_LINK_CONTROL_OFFSET(ASM118x_PCIE_CAPABILITY_OFFSET + \
  OFFSET_OF (PCI_CAPABILITY_PCIEXP, 
\
@@ -39,24 +42,10 @@ RetrainAsm1184eDownstreamPort (
   IN  EFI_PCI_IO_PROTOCOL   *PciIo
   )
 {
-  UINT16PciVidPid[2];
   EFI_STATUSStatus;
   PCIE_CAP  Cap;
   PCI_REG_PCIE_LINK_CONTROL LinkControl;
 
-  Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET,
-ARRAY_SIZE (PciVidPid), );
-  if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n",
-  __FUNCTION__, Status));
-return;
-  }
-
-  if (PciVidPid[0] != ASMEDIA_VID ||
-  (PciVidPid[1] != ASM1182E_PID && PciVidPid[1] != ASM1184E_PID)) {
-return;
-  }
-
   //
   // The upstream and downstream ports share the same PID/VID, so check
   // the port type. This assumes the PCIe Express capability block lives
@@ -91,6 +80,34 @@ RetrainAsm1184eDownstreamPort (
 
 STATIC
 VOID
+EnableAsm1061SpreadSpectrum (
+  IN  EFI_PCI_IO_PROTOCOL   *PciIo
+  )
+{
+  EFI_STATUS  Status;
+  UINT8   SscVal;
+
+  DEBUG ((DEBUG_INFO, "%a: enabling spread spectrum mode 0 for ASM1061\n",
+__FUNCTION__));
+
+  // SSC mode 0~-4000 ppm, 1:1 modulation
+
+  SscVal = 0;
+  Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ASM1061_SSC_OFFSET, 1,
+);
+  ASSERT_EFI_ERROR (Status);
+
+  MemoryFence ();
+  gBS->Stall (1); // delay at least 100 ns between writes of the same register
+
+  SscVal = 1;
+  Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ASM1061_SSC_OFFSET, 1,
+);
+  ASSERT_EFI_ERROR (Status);
+}
+
+STATIC
+VOID
 EFIAPI
 OnPciIoProtocolNotify (
   IN EFI_EVENT  Event,
@@ -101,6 +118,7 @@ OnPciIoProtocolNotify (
   EFI_STATUSStatus;
   EFI_HANDLEHandleBuffer;
   UINTN BufferSize;
+  UINT16PciVidPid[2];
 
   while (TRUE) {
 BufferSize = sizeof (EFI_HANDLE);
@@ -114,18 +132,45 @@ OnPciIoProtocolNotify (
 (VOID **));
 ASSERT_EFI_ERROR (Status);
 
-//
-// The ASM1184E 4-port PCIe switch on the DeveloperBox board (and its
-// 2-port sibling of which samples were used in development) needs a
-// little nudge to get it to train the downstream links at Gen2 speed.
-//
-RetrainAsm1184eDownstreamPort (PciIo);
+Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET,
+  ARRAY_SIZE (PciVidPid), );
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n",
+__FUNCTION__, Status));
+  continue;
+}
+
+if (PciVidPid[0] != ASMEDIA_VID) {
+  continue;
+}
+
+switch (PciVidPid[1]) {
+case ASM1061_PID:
+  //
+  // The ASM1061 SATA controller as integrated into the DeveloperBox design
+  // emits too much electromagnetic radiation. So enable spread spectrum
+  // mode.
+  //
+  EnableAsm1061SpreadSpectrum (PciIo);
+  break;
+case ASM1182E_PID:
+case ASM1184E_PID:
+  //
+  // The ASM1184E 

Re: [edk2] [PATCH edk2-non-osi v1 0/2] Update binary of trusted-firmware

[Huangming (Mark)]

On 2018/1/23 22:40, Leif Lindholm wrote:
> On Sat, Jan 20, 2018 at 09:50:40AM +, Ard Biesheuvel wrote:
>> On 20 January 2018 at 03:56, Heyi Guo  wrote:
>>> Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75 #1214.
>>>
>>> Heyi Guo (2):
>>>   Hisilicon/D03: Update binary of trusted-firmware
>>>   Hisilicon/D05: Update binary of trusted-firmware
>>>
>>>  Platform/Hisilicon/D03/bl1.bin | Bin 14336 -> 12416 bytes
>>>  Platform/Hisilicon/D03/fip.bin | Bin 62513 -> 66758 bytes
>>>  Platform/Hisilicon/D05/bl1.bin | Bin 14344 -> 12424 bytes
>>>  Platform/Hisilicon/D05/fip.bin | Bin 41493 -> 37546 bytes
>>>  4 files changed, 0 insertions(+), 0 deletions(-)
>>>
>>
>> Reviewed-by: Ard Biesheuvel 
>>
>> Good to see that you have incorporated these mitigations for 18.02
>>
>> Where is the branch I can pull these from?
> 
> Same question from me.
> 
> Also, can you clarify whether these are simple rebuilds of the 17.10
> sources with only these workarounds enabled or whether they include
> additional changes?
> 
> /
> Leif
> 
> .
> 
They include upgrade trusted firmware to 1.4.
I will add this to the message.

They can be found in github: https://github.com/hisilicon/OpenPlatformPkg.git
branch: rp-1802-osi-v1

Thanks.

-- 
Best Regards,

Ming

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Re: [edk2] [PATCH] Silicon/SynQuacer/PlatformDxe: enable spread spectrum mode for ASM1061 SATA

[Leif Lindholm]

On Wed, Jan 24, 2018 at 11:13:17AM +, Ard Biesheuvel wrote:
> >> +if (PciVidPid[1] == ASM1061_PID) {
> >> +  //
> >> +  // The ASM1061 SATA controller as integrated into the DeveloperBox 
> >> design
> >> +  // emits too much electromagnetic radiation. So enable spread 
> >> spectrum
> >> +  // mode.
> >> +  //
> >> +  EnableAsm1061SpreadSpectrum (PciIo);
> >> +} else if (PciVidPid[1] == ASM1182E_PID || PciVidPid[1] == 
> >> ASM1184E_PID) {
> >
> > Does this "else if" prevent the SATA controller from training GEN2?
> > Could it be just another if?
> >
> 
> Only if PciVidPid[1] equals ASM1061_PID and ASM1182E_PID/ASM1184E_PID
> at the same time.

Ah, gotcha.
The flattened topology threw me off :)

/
Leif
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Re: [edk2] [PATCH edk2-platforms v2 15/18] ARM/VExpressPkg: New DP500/DP550/DP650 platform library.

[Ard Biesheuvel]

On 24 January 2018 at 11:27, Alexei Fedorov  wrote:
> Hi Ard,
>
>
> You wrote:
>
>
>> > +  Status = gDS->SetMemorySpaceAttributes (
>> > +  *VramBaseAddress,
>> > +  *VramSize,
>> > +  EFI_MEMORY_WC
>>
>> Please add EFI_MEMORY_XP here
>>
>
>
> Setting EFI_MEMORY_XP causes assertion because
> gDS->SetMemorySpaceAttributes() returns Unsupported in
> edk2\MdeModulePkg\Core\Dxe\Gcd\Gcd.c  with Status set at line #834:
>
>
>   if ((Entry->Capabilities & Attributes) != Attributes) {
>
> //***AF
> DEBUG ((DEBUG_GCD, " @%d EFI_UNSUPPORTED: Capabilitie=0x%lX
> Attributes=0x%lX\n",
> __LINE__, Entry->Capabilities, Attributes));
>
> Status = EFI_UNSUPPORTED;
> goto Done;
>   }
>
> because Entry->Capabilities don't have EFI_MEMORY_XP set, see debug output
> below:
>



> If  gDS->SetMemorySpaceAttributes() call is replaced with
> Cpu->SetMemoryAttributes(), attributes are set successfully with eXecute bit
> for frame buffer being cleared.
>

Ugh. The GCD map conflates capabilities of the region (i.e., this
region can be configured as read-only by the MMU) with permissions
(i.e., the contents of this region should not be modified by the
program), which is why nobody bothers to set these attributes for the
GCD region. If you do set those bits in the GCD map, all allocations
carved out of it will be read-only and non-executable (because, hey,
why would you allocate writable or executable memory from a region
that can be configured as read-only or non-executable?).

In any case, your solution is the correct one: use the arch CPU
protocol directly instead (although there is something  in the PI spec
that bans it). Having an executable frame buffer is a much bigger deal
IMHO, especially when all other allocations are being locked down, and
so my preference is to switch to the arch CPU protocol here.

Thanks,
Ard.
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Re: [edk2] [PATCH edk2-platforms v2 15/18] ARM/VExpressPkg: New DP500/DP550/DP650 platform library.

[Alexei Fedorov]

Hi Ard,


You wrote:


> > +  Status = gDS->SetMemorySpaceAttributes (
> > +  *VramBaseAddress,
> > +  *VramSize,
> > +  EFI_MEMORY_WC
>
> Please add EFI_MEMORY_XP here
>


Setting EFI_MEMORY_XP causes assertion because  gDS->SetMemorySpaceAttributes() 
returns Unsupported in edk2\MdeModulePkg\Core\Dxe\Gcd\Gcd.c  with Status set at 
line #834:


  if ((Entry->Capabilities & Attributes) != Attributes) {

//***AF
DEBUG ((DEBUG_GCD, " @%d EFI_UNSUPPORTED: Capabilitie=0x%lX 
Attributes=0x%lX\n",
__LINE__, Entry->Capabilities, Attributes));

Status = EFI_UNSUPPORTED;
goto Done;
  }

because Entry->Capabilities don't have EFI_MEMORY_XP set, see debug output 
below:


===

 Framebuffer @0xF98A4000 0x400
GCD:SetMemorySpaceAttributes(Base=F98A4000,Length=0400)
  Attributes  = 4002
 @834 EFI_UNSUPPORTED: Capabilities=0x800E Attributes=0x4002
  Status = Unsupported
GCDMemType Range Capabilities Attributes
== =  
NonExist   -07FF  
MMIO   0800-0BFF C001 8001
NonExist   0C00-1C16  
MMIO   1C17-1C170FFF C001 8001
NonExist   1C171000-4FFF  
MMIO   5000-501F C001 0001*
MMIO   5020-57FF C001 0001
NonExist   5800-7FFF  
SystemMem  8000-FEFF 800E 0008*
NonExist   FF00-00087FFF  
SystemMem  00088000-0009 800E 0008*
NonExist   000A-003F  
MMIO   0040-004F C001 0001*
MMIO   00400010-0040 C001 0001
NonExist   0041-  

ASSERT_EFI_ERROR (Status = Unsupported)
ASSERT [HdLcdGraphicsDxe] 
n:\edk2\ArmPlatformPkg\ArmJunoPkg\Library\HdLcdArmJunoLib\HdLcdArmJuno.c(254): 
!EFI_ERROR (Status)
===

If  gDS->SetMemorySpaceAttributes() call is replaced with 
Cpu->SetMemoryAttributes(), attributes are set successfully with eXecute bit 
for frame buffer being cleared.


Alexei.


From: edk2-devel  on behalf of Evan Lloyd 

Sent: 08 January 2018 18:51:12
To: Ard Biesheuvel
Cc: "matteo.carl...@arm.com"@arm.com; "leif.lindh...@linaro.org"@arm.com; 
"n...@arm.com"@arm.com; edk2-devel@lists.01.org; Arvind Chauhan; 
"ard.biesheu...@linaro.org"@arm.com; Thomas Abraham
Subject: Re: [edk2] [PATCH edk2-platforms v2 15/18] ARM/VExpressPkg: New 
DP500/DP550/DP650 platform library.



> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: 23 December 2017 16:07
> To: Evan Lloyd 
> Cc: edk2-devel@lists.01.org; Arvind Chauhan ;
> Daniil Egranov ; Thomas Abraham
> ; "ard.biesheu...@linaro.org"@arm.com;
> "leif.lindh...@linaro.org"@arm.com;
> "matteo.carl...@arm.com"@arm.com; "n...@arm.com"@arm.com
> Subject: Re: [PATCH edk2-platforms v2 15/18] ARM/VExpressPkg: New
> DP500/DP550/DP650 platform library.
>
> On 22 December 2017 at 19:08,   wrote:
> > From: Girish Pathak 
> >
...
> > +
> > +/* Internal helper function to allocate memory if memory is not
> > +already
> > +  reserved for framebuffer
> > +
> > +  @param[in]  VramSize  Requested framebuffer size in bytes.
> > +  @param[out] VramBaseAddress   Pointer to memory allocated for
> framebuffer.
> > +
> > +  @retval EFI_SUCCESS   Framebuffer memory allocated successfully.
> > +  @retval EFI_UNSUPPORTED   Allocated address wider than 40 bits.
> > +  @retval !EFI_SUCCESS  Other errors.
> > +**/
> > +STATIC
> > +EFI_STATUS
> > +GetVram (
> > +  IN  UINTN CONST  VramSize,
> > +  OUT EFI_PHYSICAL_ADDRESS *CONST  VramBaseAddress
> > +  )
> > +{
> > +  EFI_STATUS Status;
> > +
> > +  // Check if memory is already reserved for the framebuffer.
> > +#if (FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase) != 0)
> > +
>
> Please don't use CPP conditionals for control flow
>
> > +#if (!DP_VALID_BASE_ADDR (FixedPcdGet64
> > +(PcdArmLcdDdrFrameBufferBase))) #error ARM Mali DP framebuffer
> base address cannot be wider than 40 bits.
> > +#else
> > +  *VramBaseAddress =
> > +

Re: [edk2] [PATCH edk2-platforms v1 04/14] Hisilicon D03/D05: Add capsule upgrade support

[Ard Biesheuvel]

On 24 January 2018 at 11:10, Huangming (Mark)  wrote:
>
>
> On 2018/1/20 18:50, Ard Biesheuvel wrote:
>> On 18 January 2018 at 15:01, Ming Huang  wrote:
>>> From: Jason Zhang 
>>>
>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>> Signed-off-by: Jason Zhang 
>>> Signed-off-by: Ming Huang 
>>> Signed-off-by: Heyi Guo 
>>> ---
>>>  
>>> Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
>>>  |  45 +
>>>  Platform/Hisilicon/D03/D03.dsc 
>>>   |  17 +++-
>>>  Platform/Hisilicon/D03/D03.fdf 
>>>   |  70 +
>>>  
>>> Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
>>>  |  45 +
>>>  Platform/Hisilicon/D05/D05.dsc 
>>>   |  19 +++-
>>>  Platform/Hisilicon/D05/D05.fdf 
>>>   |  70 +
>>>  
>>> Silicon/Hisilicon/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
>>>  |  81 +++
>>>  
>>> Silicon/Hisilicon/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
>>>   |  50 +
>>>  
>>> Silicon/Hisilicon/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
>>>  |  70 +
>>>  Silicon/Hisilicon/Hisilicon.dsc.inc
>>>   |  11 +-
>>>  Silicon/Hisilicon/Hisilicon.fdf.inc
>>>   |   9 ++
>>>  
>>> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c
>>>  | 106 
>>>  
>>> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf
>>>|  51 ++
>>>  13 files changed, 641 insertions(+), 3 deletions(-)
>>>
>>
>> Excellent!! Very happy to see this added.
>>
>>> diff --git 
>>> a/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
>>>  
>>> b/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
>>> new file mode 100644
>>> index 000..fc834d9
>>> --- /dev/null
>>> +++ 
>>> b/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
>>> @@ -0,0 +1,45 @@
>>> +#
>>> +#  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
>>> +#  Copyright (c) 2018, Linaro Limited. All rights reserved.
>>> +#  Copyright (c) 2016, Intel Corporation. All rights reserved.
>>> +#
>>> +#  This program and the accompanying materials
>>> +#  are licensed and made available under the terms and conditions of the 
>>> BSD License
>>> +#  which accompanies this distribution.  The full text of the license may 
>>> be found at
>>> +#  http://opensource.org/licenses/bsd-license.php
>>> +#
>>> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>>> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
>>> IMPLIED.
>>> +#
>>> +##
>>> +
>>> +[Head]
>>> +NumOfUpdate = 3
>>> +NumOfRecovery = 0
>>> +Update0 = SysFvMain
>>> +Update1 = SysCustom
>>> +Update2 = SysNvRam
>>> +
>>> +[SysFvMain]
>>> +FirmwareType  = 0 # 0 - SystemFirmware, 1 - NvRam
>>> +AddressType   = 0 # 0 - relative address, 1 - absolute address.
>>> +BaseAddress   = 0x# Base address offset on flash
>>> +Length= 0x002D# Length
>>> +ImageOffset   = 0x# Image offset of this SystemFirmware image
>>> +FileGuid  = 642e4fcf-2df7-4415-8b70-a03909c57b55  # 
>>> PcdEdkiiSystemFirmwareFileGuid
>>> +
>>> +[SysCustom]
>>> +FirmwareType  = 0 # 0 - SystemFirmware, 1 - NvRam
>>> +AddressType   = 0 # 0 - relative address, 1 - absolute address.
>>> +BaseAddress   = 0x002F# Base address offset on flash
>>> +Length= 0x0001# Length
>>> +ImageOffset   = 0x002F# Image offset of this SystemFirmware image
>>> +FileGuid  = 642e4fcf-2df7-4415-8b70-a03909c57b55  # 
>>> PcdEdkiiSystemFirmwareFileGuid
>>> +
>>> +[SysNvRam]
>>> +FirmwareType  = 1 # 0 - SystemFirmware, 1 - NvRam
>>> +AddressType   = 0 # 0 - relative address, 1 - absolute address.
>>> +BaseAddress   = 0x002D# Base address offset on flash
>>> +Length= 0x0002# Length
>>> +ImageOffset   = 0x002D# Image offset of this SystemFirmware image
>>> +FileGuid  = 642e4fcf-2df7-4415-8b70-a03909c57b55  # 
>>> PcdEdkiiSystemFirmwareFileGuid
>>> diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
>>> index b2eae7d..69bc7b4 100644
>>> --- a/Platform/Hisilicon/D03/D03.dsc
>>> +++ b/Platform/Hisilicon/D03/D03.dsc
>>> @@ -66,7 +66,6 @@
>>>
>>> 

Re: [edk2] [PATCH edk2-platforms v1 04/14] Hisilicon D03/D05: Add capsule upgrade support

[Huangming (Mark)]

On 2018/1/20 18:50, Ard Biesheuvel wrote:
> On 18 January 2018 at 15:01, Ming Huang  wrote:
>> From: Jason Zhang 
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Jason Zhang 
>> Signed-off-by: Ming Huang 
>> Signed-off-by: Heyi Guo 
>> ---
>>  
>> Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
>>  |  45 +
>>  Platform/Hisilicon/D03/D03.dsc  
>>  |  17 +++-
>>  Platform/Hisilicon/D03/D03.fdf  
>>  |  70 +
>>  
>> Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
>>  |  45 +
>>  Platform/Hisilicon/D05/D05.dsc  
>>  |  19 +++-
>>  Platform/Hisilicon/D05/D05.fdf  
>>  |  70 +
>>  
>> Silicon/Hisilicon/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
>>  |  81 +++
>>  
>> Silicon/Hisilicon/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
>>   |  50 +
>>  
>> Silicon/Hisilicon/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
>>  |  70 +
>>  Silicon/Hisilicon/Hisilicon.dsc.inc 
>>  |  11 +-
>>  Silicon/Hisilicon/Hisilicon.fdf.inc 
>>  |   9 ++
>>  
>> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c 
>> | 106 
>>  
>> Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf
>>|  51 ++
>>  13 files changed, 641 insertions(+), 3 deletions(-)
>>
> 
> Excellent!! Very happy to see this added.
> 
>> diff --git 
>> a/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
>>  
>> b/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
>> new file mode 100644
>> index 000..fc834d9
>> --- /dev/null
>> +++ 
>> b/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
>> @@ -0,0 +1,45 @@
>> +#
>> +#  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
>> +#  Copyright (c) 2018, Linaro Limited. All rights reserved.
>> +#  Copyright (c) 2016, Intel Corporation. All rights reserved.
>> +#
>> +#  This program and the accompanying materials
>> +#  are licensed and made available under the terms and conditions of the 
>> BSD License
>> +#  which accompanies this distribution.  The full text of the license may 
>> be found at
>> +#  http://opensource.org/licenses/bsd-license.php
>> +#
>> +#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
>> IMPLIED.
>> +#
>> +##
>> +
>> +[Head]
>> +NumOfUpdate = 3
>> +NumOfRecovery = 0
>> +Update0 = SysFvMain
>> +Update1 = SysCustom
>> +Update2 = SysNvRam
>> +
>> +[SysFvMain]
>> +FirmwareType  = 0 # 0 - SystemFirmware, 1 - NvRam
>> +AddressType   = 0 # 0 - relative address, 1 - absolute address.
>> +BaseAddress   = 0x# Base address offset on flash
>> +Length= 0x002D# Length
>> +ImageOffset   = 0x# Image offset of this SystemFirmware image
>> +FileGuid  = 642e4fcf-2df7-4415-8b70-a03909c57b55  # 
>> PcdEdkiiSystemFirmwareFileGuid
>> +
>> +[SysCustom]
>> +FirmwareType  = 0 # 0 - SystemFirmware, 1 - NvRam
>> +AddressType   = 0 # 0 - relative address, 1 - absolute address.
>> +BaseAddress   = 0x002F# Base address offset on flash
>> +Length= 0x0001# Length
>> +ImageOffset   = 0x002F# Image offset of this SystemFirmware image
>> +FileGuid  = 642e4fcf-2df7-4415-8b70-a03909c57b55  # 
>> PcdEdkiiSystemFirmwareFileGuid
>> +
>> +[SysNvRam]
>> +FirmwareType  = 1 # 0 - SystemFirmware, 1 - NvRam
>> +AddressType   = 0 # 0 - relative address, 1 - absolute address.
>> +BaseAddress   = 0x002D# Base address offset on flash
>> +Length= 0x0002# Length
>> +ImageOffset   = 0x002D# Image offset of this SystemFirmware image
>> +FileGuid  = 642e4fcf-2df7-4415-8b70-a03909c57b55  # 
>> PcdEdkiiSystemFirmwareFileGuid
>> diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
>> index b2eae7d..69bc7b4 100644
>> --- a/Platform/Hisilicon/D03/D03.dsc
>> +++ b/Platform/Hisilicon/D03/D03.dsc
>> @@ -66,7 +66,6 @@
>>
>> OemAddressMapLib|Platform/Hisilicon/D03/Library/OemAddressMap2P/OemAddressMap2PHi1610.inf
>>
>> PlatformSysCtrlLib|Silicon/Hisilicon/Hi1610/Library/PlatformSysCtrlLibHi1610/PlatformSysCtrlLibHi1610.inf
>>
>> -  

Re: [edk2] [PATCH] Silicon/SynQuacer/PlatformDxe: enable spread spectrum mode for ASM1061 SATA

[Leif Lindholm]

On Wed, Jan 24, 2018 at 10:40:52AM +, Ard Biesheuvel wrote:
> The ASM1061 SATA controller integrated into the DeveloperBox board
> emits too much electromagnetic radiation, so it needs spread spectrum
> mode enabled.

I presume the spectrum mode is on the PCIe side rather than the SATA
side? Can this be explicitly mentioned?

> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel 
> ---
>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/{Asmedia118x.c => Asmedia.c} 
> | 79 +++-

Since you started renaming things, I invoke the right of bikeshedding.

The SATA controller is only Asmedia as well due to happenstance - if
this file is becoming "various PCI tweaks", can we just call it Pci.c
(or PciTweaks.c by all means)?

>  Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf  
> |  2 +-
>  2 files changed, 60 insertions(+), 21 deletions(-)
> 
> diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c 
> b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia.c
> similarity index 64%
> rename from Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c
> rename to Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia.c
> index c4cbacd3dff9..6c289fa1892e 100644
> --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c
> +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia.c
> @@ -15,9 +15,12 @@
>  #include "PlatformDxe.h"
>  
>  #define ASMEDIA_VID 0x1b21
> +#define ASM1061_PID 0x0612
>  #define ASM1182E_PID0x1182
>  #define ASM1184E_PID0x1184
>  
> +#define ASM1061_SSC_OFFSET  0xA10
> +
>  #define ASM118x_PCIE_CAPABILITY_OFFSET  0x80
>  #define ASM118x_PCIE_LINK_CONTROL_OFFSET(ASM118x_PCIE_CAPABILITY_OFFSET 
> + \
>   OFFSET_OF 
> (PCI_CAPABILITY_PCIEXP, \
> @@ -39,24 +42,10 @@ RetrainAsm1184eDownstreamPort (
>IN  EFI_PCI_IO_PROTOCOL   *PciIo
>)
>  {
> -  UINT16PciVidPid[2];
>EFI_STATUSStatus;
>PCIE_CAP  Cap;
>PCI_REG_PCIE_LINK_CONTROL LinkControl;
>  
> -  Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET,
> -ARRAY_SIZE (PciVidPid), );
> -  if (EFI_ERROR (Status)) {
> -DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n",
> -  __FUNCTION__, Status));
> -return;
> -  }
> -
> -  if (PciVidPid[0] != ASMEDIA_VID ||
> -  (PciVidPid[1] != ASM1182E_PID && PciVidPid[1] != ASM1184E_PID)) {
> -return;
> -  }
> -
>//
>// The upstream and downstream ports share the same PID/VID, so check
>// the port type. This assumes the PCIe Express capability block lives
> @@ -91,6 +80,34 @@ RetrainAsm1184eDownstreamPort (
>  
>  STATIC
>  VOID
> +EnableAsm1061SpreadSpectrum (
> +  IN  EFI_PCI_IO_PROTOCOL   *PciIo
> +  )
> +{
> +  EFI_STATUS  Status;
> +  UINT8   SscVal;
> +
> +  DEBUG ((DEBUG_INFO, "%a: enabling spread spectrum mode 0 for ASM1061\n",
> +__FUNCTION__));
> +
> +  // SSC mode 0~-4000 ppm, 1:1 modulation
> +
> +  SscVal = 0;
> +  Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ASM1061_SSC_OFFSET, 
> 1,
> +);
> +  ASSERT_EFI_ERROR (Status);
> +
> +  MemoryFence ();
> +  gBS->Stall (1); // delay at least 100 ns between writes of the same 
> register
> +
> +  SscVal = 1;
> +  Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ASM1061_SSC_OFFSET, 
> 1,
> +);
> +  ASSERT_EFI_ERROR (Status);
> +}
> +
> +STATIC
> +VOID
>  EFIAPI
>  OnPciIoProtocolNotify (
>IN EFI_EVENT  Event,
> @@ -101,6 +118,7 @@ OnPciIoProtocolNotify (
>EFI_STATUSStatus;
>EFI_HANDLEHandleBuffer;
>UINTN BufferSize;
> +  UINT16PciVidPid[2];
>  
>while (TRUE) {
>  BufferSize = sizeof (EFI_HANDLE);
> @@ -114,12 +132,33 @@ OnPciIoProtocolNotify (
>  (VOID **));
>  ASSERT_EFI_ERROR (Status);
>  
> -//
> -// The ASM1184E 4-port PCIe switch on the DeveloperBox board (and its
> -// 2-port sibling of which samples were used in development) needs a
> -// little nudge to get it to train the downstream links at Gen2 speed.
> -//
> -RetrainAsm1184eDownstreamPort (PciIo);
> +Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 
> PCI_VENDOR_ID_OFFSET,
> +  ARRAY_SIZE (PciVidPid), );
> +if (EFI_ERROR (Status)) {
> +  DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n",
> +__FUNCTION__, Status));
> +  continue;
> +}
> +
> +if (PciVidPid[0] != ASMEDIA_VID) {
> +  continue;
> +}
> +
> +if (PciVidPid[1] == ASM1061_PID) {
> +  //
> +  // The ASM1061 SATA controller as integrated into the 

[edk2] [PATCH] Silicon/SynQuacer/PlatformDxe: enable spread spectrum mode for ASM1061 SATA

[Ard Biesheuvel]

The ASM1061 SATA controller integrated into the DeveloperBox board
emits too much electromagnetic radiation, so it needs spread spectrum
mode enabled.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel 
---
 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/{Asmedia118x.c => Asmedia.c} | 
79 +++-
 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf  | 
 2 +-
 2 files changed, 60 insertions(+), 21 deletions(-)

diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c 
b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia.c
similarity index 64%
rename from Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c
rename to Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia.c
index c4cbacd3dff9..6c289fa1892e 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c
+++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia.c
@@ -15,9 +15,12 @@
 #include "PlatformDxe.h"
 
 #define ASMEDIA_VID 0x1b21
+#define ASM1061_PID 0x0612
 #define ASM1182E_PID0x1182
 #define ASM1184E_PID0x1184
 
+#define ASM1061_SSC_OFFSET  0xA10
+
 #define ASM118x_PCIE_CAPABILITY_OFFSET  0x80
 #define ASM118x_PCIE_LINK_CONTROL_OFFSET(ASM118x_PCIE_CAPABILITY_OFFSET + \
  OFFSET_OF (PCI_CAPABILITY_PCIEXP, 
\
@@ -39,24 +42,10 @@ RetrainAsm1184eDownstreamPort (
   IN  EFI_PCI_IO_PROTOCOL   *PciIo
   )
 {
-  UINT16PciVidPid[2];
   EFI_STATUSStatus;
   PCIE_CAP  Cap;
   PCI_REG_PCIE_LINK_CONTROL LinkControl;
 
-  Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET,
-ARRAY_SIZE (PciVidPid), );
-  if (EFI_ERROR (Status)) {
-DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n",
-  __FUNCTION__, Status));
-return;
-  }
-
-  if (PciVidPid[0] != ASMEDIA_VID ||
-  (PciVidPid[1] != ASM1182E_PID && PciVidPid[1] != ASM1184E_PID)) {
-return;
-  }
-
   //
   // The upstream and downstream ports share the same PID/VID, so check
   // the port type. This assumes the PCIe Express capability block lives
@@ -91,6 +80,34 @@ RetrainAsm1184eDownstreamPort (
 
 STATIC
 VOID
+EnableAsm1061SpreadSpectrum (
+  IN  EFI_PCI_IO_PROTOCOL   *PciIo
+  )
+{
+  EFI_STATUS  Status;
+  UINT8   SscVal;
+
+  DEBUG ((DEBUG_INFO, "%a: enabling spread spectrum mode 0 for ASM1061\n",
+__FUNCTION__));
+
+  // SSC mode 0~-4000 ppm, 1:1 modulation
+
+  SscVal = 0;
+  Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ASM1061_SSC_OFFSET, 1,
+);
+  ASSERT_EFI_ERROR (Status);
+
+  MemoryFence ();
+  gBS->Stall (1); // delay at least 100 ns between writes of the same register
+
+  SscVal = 1;
+  Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ASM1061_SSC_OFFSET, 1,
+);
+  ASSERT_EFI_ERROR (Status);
+}
+
+STATIC
+VOID
 EFIAPI
 OnPciIoProtocolNotify (
   IN EFI_EVENT  Event,
@@ -101,6 +118,7 @@ OnPciIoProtocolNotify (
   EFI_STATUSStatus;
   EFI_HANDLEHandleBuffer;
   UINTN BufferSize;
+  UINT16PciVidPid[2];
 
   while (TRUE) {
 BufferSize = sizeof (EFI_HANDLE);
@@ -114,12 +132,33 @@ OnPciIoProtocolNotify (
 (VOID **));
 ASSERT_EFI_ERROR (Status);
 
-//
-// The ASM1184E 4-port PCIe switch on the DeveloperBox board (and its
-// 2-port sibling of which samples were used in development) needs a
-// little nudge to get it to train the downstream links at Gen2 speed.
-//
-RetrainAsm1184eDownstreamPort (PciIo);
+Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET,
+  ARRAY_SIZE (PciVidPid), );
+if (EFI_ERROR (Status)) {
+  DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n",
+__FUNCTION__, Status));
+  continue;
+}
+
+if (PciVidPid[0] != ASMEDIA_VID) {
+  continue;
+}
+
+if (PciVidPid[1] == ASM1061_PID) {
+  //
+  // The ASM1061 SATA controller as integrated into the DeveloperBox design
+  // emits too much electromagnetic radiation. So enable spread spectrum
+  // mode.
+  //
+  EnableAsm1061SpreadSpectrum (PciIo);
+} else if (PciVidPid[1] == ASM1182E_PID || PciVidPid[1] == ASM1184E_PID) {
+  //
+  // The ASM1184E 4-port PCIe switch on the DeveloperBox board (and its
+  // 2-port sibling of which samples were used in development) needs a
+  // little nudge to get it to train the downstream links at Gen2 speed.
+  //
+  RetrainAsm1184eDownstreamPort (PciIo);
+}
   }
 }
 
diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf 

[edk2] EDK debug question

[JUNWEN JIA]

Hi, Andrew:
 Thanks a lot and I really appreciate your suggestion. But the assembly 
language code is for getting started, 
and I may have to write C language embedded with assembly language and compile 
through EDK. That is why 
I have to use assembly language to achieve the restart function. 
And I have some doubts, if I call functions that already exists in 
BaseLib->Ia32,for example:
 #include
　Void main()
　{
　WriteMsr64(0,0);
　}
　This can be compiled successfully and .efi file can be generated.
　
　Best regards!
　

发送自 Windows 10 版邮件应用

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[edk2] [patch 2/3] MdeModulePkg/BdsDxe: Remove useless Pref Code

[Dandan Bi]

Our new performance infrastructure can support to dump performance
date form ACPI table in OS. So we can remove the old pref code to
write performance data to OS.

Cc: Liming Gao 
Cc: Ruiyu Ni 
Cc: Star Zeng 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi 
---
 MdeModulePkg/Universal/BdsDxe/Bds.h  |  3 +-
 MdeModulePkg/Universal/BdsDxe/BdsDxe.inf |  3 +-
 MdeModulePkg/Universal/BdsDxe/BdsEntry.c | 57 +---
 3 files changed, 3 insertions(+), 60 deletions(-)

diff --git a/MdeModulePkg/Universal/BdsDxe/Bds.h 
b/MdeModulePkg/Universal/BdsDxe/Bds.h
index 5658e61..63d961f 100644
--- a/MdeModulePkg/Universal/BdsDxe/Bds.h
+++ b/MdeModulePkg/Universal/BdsDxe/Bds.h
@@ -1,9 +1,9 @@
 /** @file
   Head file for BDS Architectural Protocol implementation
 
-Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
 http://opensource.org/licenses/bsd-license.php
 
@@ -16,11 +16,10 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER 
EXPRESS OR IMPLIED.
 #define _BDS_MODULE_H_
 
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 
 #include 
 #include 
diff --git a/MdeModulePkg/Universal/BdsDxe/BdsDxe.inf 
b/MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
index a00b442..b8c5aa9 100644
--- a/MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+++ b/MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
@@ -3,11 +3,11 @@
 #
 #  When DxeCore dispatching all DXE driver, this module will produce 
architecture protocol 
 #  gEfiBdsArchProtocolGuid. After DxeCore finish dispatching, DxeCore will 
invoke Entry
 #  interface of protocol gEfiBdsArchProtocolGuid, then BDS phase is entered.
 #  
-#  Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+#  Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
 #  which accompanies this distribution.  The full text of the license may be 
found at
 #  http://opensource.org/licenses/bsd-license.php
 #
@@ -76,11 +76,10 @@
 ## SOMETIMES_CONSUMES ## 
Variable:L"ConIn" (The device path of console in device)
 ## SOMETIMES_CONSUMES ## 
Variable:L"ConOut" (The device path of console out device)
 ## SOMETIMES_CONSUMES ## 
Variable:L"ErrOut" (The device path of error out device)
   gConnectConInEventGuid## SOMETIMES_CONSUMES ## Event
   gEdkiiStatusCodeDataTypeVariableGuid  ## SOMETIMES_CONSUMES ## GUID
-  gPerformanceProtocolGuid  ## SOMETIMES_PRODUCES ## 
Variable:L"PerfDataMemAddr" (The ACPI address of performance data)
   gEfiEventReadyToBootGuid  ## CONSUMES   ## Event
 
 [Protocols]
   gEfiBdsArchProtocolGuid   ## PRODUCES
   gEfiSimpleTextInputExProtocolGuid ## CONSUMES
diff --git a/MdeModulePkg/Universal/BdsDxe/BdsEntry.c 
b/MdeModulePkg/Universal/BdsDxe/BdsEntry.c
index 2b24755..3191a98 100644
--- a/MdeModulePkg/Universal/BdsDxe/BdsEntry.c
+++ b/MdeModulePkg/Universal/BdsDxe/BdsEntry.c
@@ -3,11 +3,11 @@
   When this module was dispatched by DxeCore, gEfiBdsArchProtocolGuid will be 
installed
   which contains interface of BdsEntry.
   After DxeCore finish DXE phase, gEfiBdsArchProtocolGuid->BdsEntry will be 
invoked
   to enter BDS phase.
 
-Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
 (C) Copyright 2016 Hewlett Packard Enterprise Development LP
 (C) Copyright 2015 Hewlett-Packard Development Company, L.P.
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -633,61 +633,10 @@ BdsFormalizeEfiGlobalVariable (
   //
   BdsFormalizeOSIndicationVariable ();
 }
 
 /**
-
-  Allocate a block of memory that will contain performance data to OS.
-
-**/
-VOID
-BdsAllocateMemoryForPerformanceData (
-  VOID
-  )
-{
-  EFI_STATUSStatus;
-  EFI_PHYSICAL_ADDRESS  AcpiLowMemoryBase;
-  EDKII_VARIABLE_LOCK_PROTOCOL  *VariableLock;
-
-  AcpiLowMemoryBase = 0x0ULL;
-
-  //
-  // Allocate a block of memory that will contain performance data to OS.
-  //
-  Status = gBS->AllocatePages (
-  AllocateMaxAddress,
-  EfiReservedMemoryType,
-  

[edk2] [patch 0/3] Remove the useless pref codes

[Dandan Bi]

Our new performance infrastructure can support to dump performance
date form ACPI table in OS. So we can remove the old pref code to
write performance data to OS.

Cc: Eric Dong 
Cc: Laszlo Ersek 
Cc: Liming Gao 
Cc: Ruiyu Ni 
Cc: Star Zeng 
Dandan Bi (3):
  UefiCpuPkg/S3Resume: Remove useless pref code
  MdeModulePkg/BdsDxe: Remove useless Pref Code
  MdeModulePkg/UefiBootManagerLib: Remove the useless pref codes

 MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c   |  30 +-
 .../Library/UefiBootManagerLib/BmPerformance.c | 317 -
 .../Library/UefiBootManagerLib/InternalBm.h|   1 -
 .../UefiBootManagerLib/UefiBootManagerLib.inf  |   4 +-
 MdeModulePkg/Universal/BdsDxe/Bds.h|   3 +-
 MdeModulePkg/Universal/BdsDxe/BdsDxe.inf   |   3 +-
 MdeModulePkg/Universal/BdsDxe/BdsEntry.c   |  57 +---
 UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c  | 131 -
 .../Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf   |   3 +-
 9 files changed, 32 insertions(+), 517 deletions(-)
 delete mode 100644 MdeModulePkg/Library/UefiBootManagerLib/BmPerformance.c

-- 
1.9.5.msysgit.1

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[edk2] [patch] UefiCpuPkg/S3Resume: Add more perf enrty for S3 phase

[Dandan Bi]

Add more perf entry to hook BootScriptDonePpi/EndOfPeiPpi/
EndOfS3Resume.

Notes: This patch depends on the new performance
infrastructure.

Cc: Eric Dong 
Cc: Laszlo Ersek 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi 
---
 UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c 
b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
index b597ac7..d7d2a4d 100644
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
@@ -2,11 +2,11 @@
   This module produces the EFI_PEI_S3_RESUME2_PPI.
   This module works with StandAloneBootScriptExecutor to S3 resume to OS.
   This module will execute the boot script saved during last boot and after 
that,
   control is passed to OS waking up handler.
 
-  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
   Copyright (c) 2017, AMD Incorporated. All rights reserved.
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions
   of the BSD License which accompanies this distribution.  The
@@ -21,10 +21,11 @@
 #include 
 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
@@ -551,13 +552,17 @@ S3ResumeBootOs (
   PERF_END (NULL, "ScriptExec", NULL, 0);
 
   //
   // Install BootScriptDonePpi
   //
+  PERF_START_EX (NULL, "BootScriptDonePpi", NULL, 0, PERF_INMODULE_START_ID);
+
   Status = PeiServicesInstallPpi ();
   ASSERT_EFI_ERROR (Status);
 
+  PERF_END_EX (NULL, "BootScriptDonePpi", NULL, 0, PERF_INMODULE_END_ID);
+
   //
   // Get ACPI Table Address
   //
   Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) 
(AcpiS3Context->AcpiFacsTable));
 
@@ -576,18 +581,26 @@ S3ResumeBootOs (
   }
 
   //
   // Install EndOfPeiPpi
   //
+  PERF_START_EX (NULL, "EndOfPeiPpi", NULL, 0, PERF_INMODULE_START_ID);
+
   Status = PeiServicesInstallPpi ();
   ASSERT_EFI_ERROR (Status);
 
+  PERF_END_EX (NULL, "EndOfPeiPpi", NULL, 0, PERF_INMODULE_END_ID);
+
   //
   // Signal EndOfS3Resume event.
   //
+  PERF_START_EX (NULL, "EndOfS3Resume", NULL, 0, PERF_INMODULE_START_ID);
+
   SignalEndOfS3Resume ();
 
+  PERF_END_EX (NULL, "EndOfS3Resume", NULL, 0, PERF_INMODULE_END_ID);
+
   //
   // report status code on S3 resume
   //
   REPORT_STATUS_CODE (EFI_PROGRESS_CODE, EFI_SOFTWARE_PEI_MODULE | 
EFI_SW_PEI_PC_OS_WAKE);
 
-- 
1.9.5.msysgit.1

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