[edk2] [PATCH] UefiCpuPkg/SecPeiDxeTimerLibUefiCpu: Add GetIntendFsbFrequency()
The current implementation gets CPU FSB frequency by PcdFSBClock. However, IA32
SDM defined accurate FSB for some specific processors. Actually, we could try to
get FSB frequency by hardware instead of by PcdFSBClock. If FSB frequency is not
documented by IA32 SDM, we still could get it by PcdFSBClock.
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Cc: Ruiyu Ni <ruiyu...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c | 114 -
1 file changed, 111 insertions(+), 3 deletions(-)
diff --git a/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c
b/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c
index f703d7e..606ad0a 100644
--- a/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c
+++ b/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c
@@ -3,7 +3,7 @@
This library uses the local APIC library so that it supports x2APIC mode.
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -20,6 +20,108 @@
#include
#include
#include
+#include
+#include
+
+//
+// The following array is FSB frequencies defined in Pentinum 4 family, Core,
Core 2
+// and Atom CPUs, its value unit is HZ.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED
+CONST UINT32 mPentinum4FSBFrequencies[] = {
+ 26667,
+ 1,
+ 2,
+ 16667,
+ 3,
+ 1,
+ 4
+};
+
+//
+// The following array is FSB frequencies defined in SivlerMont, Airmont
+// CPUs, its value unit is HZ.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED
+CONST UINT32 mSivlerMontFSBFrequencies[] = {
+ 8333,
+ 1,
+ 1,
+ 11667,
+ 8000,
+ 9333,
+ 9000,
+ 8889,
+ 8750
+};
+
+/**
+ The function to get CPU intended FSB frequency.
+
+ This function reads the type of CPU by CPUID and returns FSB frequecny,
+
+ @retval CPU intended FSB frequency.
+
+**/
+UINT32
+GetIntendFsbFrequency (
+ VOID
+ )
+{
+ CPUID_VERSION_INFO_EAX Eax;
+ CPUID_VERSION_INFO_ECX Ecx;
+ CPUID_VERSION_INFO_EDX Edx;
+ UINT32 DisplayedFamily;
+ UINT32 DisplayedModel;
+ MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER Pentium4Msr;
+ MSR_CORE_FSB_FREQ_REGISTER CoreMsr;
+ MSR_SILVERMONT_FSB_FREQ_REGISTER SilvermontMsr;
+ UINT32 Freq;
+ UINTNFrequencyIndex;
+
+ AsmCpuid (CPUID_VERSION_INFO, , NULL, , );
+
+ DisplayedFamily = Eax.Bits.FamilyId;
+ if (Eax.Bits.FamilyId == 0x0F) {
+DisplayedFamily |= (Eax.Bits.ExtendedFamilyId << 4);
+ }
+
+ DisplayedModel = Eax.Bits.Model;
+ if (Eax.Bits.FamilyId == 0x06 || Eax.Bits.FamilyId == 0x0f) {
+DisplayedModel |= (Eax.Bits.ExtendedModelId << 4);
+ }
+
+ Freq = 0;
+ if (IS_PENTIUM_4_PROCESSOR (DisplayedFamily, DisplayedModel)) {
+Pentium4Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID);
+FrequencyIndex = Pentium4Msr.Bits.ScalableBusSpeed;
+if (FrequencyIndex == 0 && DisplayedModel == 0x02) {
+ //
+ // FrequencyIndex:000B DisplayedModel:2 is 100 MHz
+ //
+ Freq = 1;
+}
+ASSERT (FrequencyIndex < (sizeof (mPentinum4FSBFrequencies) / sizeof
(UINT32)));
+Freq = mPentinum4FSBFrequencies[FrequencyIndex];
+ } else if (IS_CORE_PROCESSOR (DisplayedFamily, DisplayedModel) ||
+ IS_CORE2_PROCESSOR (DisplayedFamily, DisplayedModel) ||
+ IS_ATOM_PROCESSOR (DisplayedFamily, DisplayedModel)) {
+CoreMsr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);
+FrequencyIndex = CoreMsr.Bits.ScalableBusSpeed;
+ASSERT (FrequencyIndex < (sizeof (mPentinum4FSBFrequencies) / sizeof
(UINT32)));
+Freq = mPentinum4FSBFrequencies[FrequencyIndex];
+ } else if (IS_SILVERMONT_PROCESSOR (DisplayedFamily, DisplayedModel)) {
+SilvermontMsr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);
+FrequencyIndex = SilvermontMsr.Bits.ScalableBusSpeed;
+ASSERT (FrequencyIndex < (sizeof (mSivlerMontFSBFrequencies) / sizeof
(UINT32)));
+Freq = mSivlerMontFSBFrequencies[FrequencyIndex];
+ }
+
+ //
+ // If processor is not in supported list, then 0 will be return
+ //
+ return Freq;
+}
/**
Internal function to return the frequency of the local APIC timer.
@@ -33,10 +135,16 @@ InternalX86GetTimerFrequency (
VOID
)
{
- UINTN Divisor;
+ UINT32 Freq;
+ UINTN Divisor;
+
[edk2] [PATCH v3 3/3] UefiCpuPkg/MpInitLib: Force to enable X2APIC if CPU number > 255
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/MpInitLib/MpLib.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index c6f8191..df19b43 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -451,6 +451,12 @@ CollectProcessorCount (
CpuPause ();
}
+ if (CpuMpData->CpuCount > 255) {
+//
+// If there are more than 255 processor found, force to enable X2APIC
+//
+CpuMpData->X2ApicEnable = TRUE;
+ }
if (CpuMpData->X2ApicEnable) {
DEBUG ((DEBUG_INFO, "Force x2APIC mode!\n"));
//
@@ -1412,7 +1418,7 @@ MpInitLibInitialize (
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;
for (Index = 0; Index < CpuMpData->CpuCount; Index++) {
InitializeSpinLock(>CpuData[Index].ApLock);
- if (CpuInfoInHob[Index].InitialApicId >= 255) {
+ if (CpuInfoInHob[Index].InitialApicId >= 255 || Index > 254) {
CpuMpData->X2ApicEnable = TRUE;
}
CpuMpData->CpuData[Index].CpuHealthy = (CpuInfoInHob[Index].Health ==
0)? TRUE:FALSE;
--
2.9.3.windows.2
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[edk2] [PATCH v3 2/3] UefiCpuPkg/MpInitLib: Check APIC mode change around AP function
If APIC ID values are changed during AP functions execution, we need to update
new APIC ID values in local data structure accordingly.
But if APIC mode change happened during AP function execution, we do not support
APIC ID value changed.
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/MpInitLib/MpLib.c | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 735e099..c6f8191 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -547,6 +547,7 @@ ApWakeupFunction (
volatile UINT32*ApStartupSignalBuffer;
CPU_INFO_IN_HOB*CpuInfoInHob;
UINT64 ApTopOfStack;
+ UINTN CurrentApicMode;
//
// AP finished assembly code and begin to execute C code
@@ -560,6 +561,7 @@ ApWakeupFunction (
ProgramVirtualWireMode ();
SyncLocalApicTimerSetting (CpuMpData);
+ CurrentApicMode = GetApicMode ();
while (TRUE) {
if (CpuMpData->InitFlag == ApInitConfig) {
//
@@ -627,11 +629,23 @@ ApWakeupFunction (
ApStartupSignalBuffer =
CpuMpData->CpuData[ProcessorNumber].StartupApSignal;
CpuInfoInHob[ProcessorNumber].ApTopOfStack =
CpuInfoInHob[CpuMpData->NewBspNumber].ApTopOfStack;
} else {
-//
-// Re-get the CPU APICID and Initial APICID
-//
-CpuInfoInHob[ProcessorNumber].ApicId= GetApicId ();
-CpuInfoInHob[ProcessorNumber].InitialApicId = GetInitialApicId ();
+if (CpuInfoInHob[ProcessorNumber].ApicId != GetApicId () ||
+CpuInfoInHob[ProcessorNumber].InitialApicId !=
GetInitialApicId ()) {
+ if (CurrentApicMode != GetApicMode ()) {
+//
+// If APIC mode change happened during AP function execution,
+// we do not support APIC ID value changed.
+//
+ASSERT (FALSE);
+CpuDeadLoop ();
+ } else {
+//
+// Re-get the CPU APICID and Initial APICID if they are changed
+//
+CpuInfoInHob[ProcessorNumber].ApicId= GetApicId ();
+CpuInfoInHob[ProcessorNumber].InitialApicId = GetInitialApicId
();
+ }
+}
}
}
SetApState (>CpuData[ProcessorNumber], CpuStateFinished);
--
2.9.3.windows.2
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[edk2] [PATCH v3 0/3] Enable X2APIC after MP service is ready
https://bugzilla.tianocore.org/show_bug.cgi?id=575 v2: Updated #1 comments v3: 1. Remove ASSERT() in #1 if X2APIC enable but user configuration is FALSE. 2. Add #3 to force X2APIC mode if CPU number > 255. Jeff Fan (3): UefiCpuPkg/CpuCommonFeaturesLib: Support X2APIC enable UefiCpuPkg/MpInitLib: Check APIC mode change around AP function UefiCpuPkg/MpInitLib: Force to enable X2APIC if CPU number > 255 .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 15 + .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c| 2 +- UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 72 +++--- UefiCpuPkg/Library/MpInitLib/MpLib.c | 32 -- 4 files changed, 104 insertions(+), 17 deletions(-) -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH v3 1/3] UefiCpuPkg/CpuCommonFeaturesLib: Support X2APIC enable
Current X2APIC is enabled in MpInitLib (used by CpuMpPei and CpuDxe) to follow
SDM suggestion. That means we only enable X2APIC if we found there are any
initial CPU ID value >= 255.
This patch is to provide one chance for platform to enable X2APIC even there is
no any initial CPU ID value >= 255.
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../CpuCommonFeaturesLib/CpuCommonFeatures.h | 15 +
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c| 2 +-
UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 72 +++---
3 files changed, 78 insertions(+), 11 deletions(-)
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
index aa6d112..9a7afed 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
@@ -798,6 +798,21 @@ C1eInitialize (
);
/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+X2ApicGetConfigData (
+ IN UINTN NumberOfProcessors
+ );
+
+/**
Detects if X2Apci feature supported on current processor.
Detect if X2Apci has been already enabled.
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
index 3390aa8..793a095 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
@@ -211,7 +211,7 @@ CpuCommonFeaturesLibConstructor (
if (IsCpuFeatureSupported (CPU_FEATURE_X2APIC)) {
Status = RegisterCpuFeature (
"X2Apic",
- NULL,
+ X2ApicGetConfigData,
X2ApicSupport,
X2ApicInitialize,
CPU_FEATURE_X2APIC,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
index 9c2ad9a..fe36368 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
@@ -15,6 +15,28 @@
#include "CpuCommonFeatures.h"
/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+X2ApicGetConfigData (
+ IN UINTN NumberOfProcessors
+ )
+{
+ BOOLEAN*ConfigData;
+
+ ConfigData = AllocateZeroPool (sizeof (BOOLEAN) * NumberOfProcessors);
+ ASSERT (ConfigData != NULL);
+ return ConfigData;
+}
+
+/**
Detects if X2Apci feature supported on current processor.
Detect if X2Apci has been already enabled.
@@ -39,8 +61,17 @@ X2ApicSupport (
IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
IN VOID *ConfigData OPTIONAL
)
-{
- return (GetApicMode () == LOCAL_APIC_MODE_X2APIC);
+{
+ BOOLEAN*X2ApicEnabled;
+
+ ASSERT (ConfigData != NULL);
+ X2ApicEnabled = (BOOLEAN *) ConfigData;
+ //
+ // *ConfigData indicates if X2APIC enabled on current processor
+ //
+ X2ApicEnabled[ProcessorNumber] = (GetApicMode () == LOCAL_APIC_MODE_X2APIC)
? TRUE : FALSE;
+
+ return (CpuInfo->CpuIdVersionInfoEcx.Bits.x2APIC == 1);
}
/**
@@ -69,13 +100,34 @@ X2ApicInitialize (
IN BOOLEAN State
)
{
- PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (
-ProcessorNumber,
-Msr,
-MSR_IA32_APIC_BASE,
-MSR_IA32_APIC_BASE_REGISTER,
-Bits.EXTD,
-(State) ? 1 : 0
-);
+ BOOLEAN*X2ApicEnabled;
+
+ ASSERT (ConfigData != NULL);
+ X2ApicEnabled = (BOOLEAN *) ConfigData;
+ if (X2ApicEnabled[ProcessorNumber]) {
+PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (
+ ProcessorNumber,
+ Msr,
+ MSR_IA32_APIC_BASE,
+ MSR_IA32_APIC_BASE_REGISTER,
+ Bits.EXTD,
+ 1
+ );
+ } else {
+//
+// Enable X2APIC mode only if X2APIC is not enabled,
+// Needn't to disabe X2APIC mode again if X2APIC is not enabled
+//
+if (State) {
+ CPU_REGISTER_TABLE_WRITE_FIELD (
+ProcessorNumber,
+Msr,
+MSR_IA32_APIC_BASE,
+MSR_IA32_APIC_BASE_REGISTER,
+Bits.EXTD,
+1
+);
+}
+ }
return RETURN_SUCCESS;
}
--
2.9.3.windows.2
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[edk2] [PATCH v2 2/2] UefiCpuPkg/MpInitLib: Check APIC mode change around AP function
If APIC ID values are changed during AP functions execution, we need to update
new APIC ID values in local data structure accordingly.
But if APIC mode change happened during AP function execution, we do not support
APIC ID value changed.
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/MpInitLib/MpLib.c | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 735e099..c6f8191 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -547,6 +547,7 @@ ApWakeupFunction (
volatile UINT32*ApStartupSignalBuffer;
CPU_INFO_IN_HOB*CpuInfoInHob;
UINT64 ApTopOfStack;
+ UINTN CurrentApicMode;
//
// AP finished assembly code and begin to execute C code
@@ -560,6 +561,7 @@ ApWakeupFunction (
ProgramVirtualWireMode ();
SyncLocalApicTimerSetting (CpuMpData);
+ CurrentApicMode = GetApicMode ();
while (TRUE) {
if (CpuMpData->InitFlag == ApInitConfig) {
//
@@ -627,11 +629,23 @@ ApWakeupFunction (
ApStartupSignalBuffer =
CpuMpData->CpuData[ProcessorNumber].StartupApSignal;
CpuInfoInHob[ProcessorNumber].ApTopOfStack =
CpuInfoInHob[CpuMpData->NewBspNumber].ApTopOfStack;
} else {
-//
-// Re-get the CPU APICID and Initial APICID
-//
-CpuInfoInHob[ProcessorNumber].ApicId= GetApicId ();
-CpuInfoInHob[ProcessorNumber].InitialApicId = GetInitialApicId ();
+if (CpuInfoInHob[ProcessorNumber].ApicId != GetApicId () ||
+CpuInfoInHob[ProcessorNumber].InitialApicId !=
GetInitialApicId ()) {
+ if (CurrentApicMode != GetApicMode ()) {
+//
+// If APIC mode change happened during AP function execution,
+// we do not support APIC ID value changed.
+//
+ASSERT (FALSE);
+CpuDeadLoop ();
+ } else {
+//
+// Re-get the CPU APICID and Initial APICID if they are changed
+//
+CpuInfoInHob[ProcessorNumber].ApicId= GetApicId ();
+CpuInfoInHob[ProcessorNumber].InitialApicId = GetInitialApicId
();
+ }
+}
}
}
SetApState (>CpuData[ProcessorNumber], CpuStateFinished);
--
2.9.3.windows.2
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[edk2] [PATCH v2 1/2] UefiCpuPkg/CpuCommonFeaturesLib: Support X2APIC enable
Current X2APIC is enabled in MpInitLib (used by CpuMpPei and CpuDxe) to follow
SDM suggestion. That means we only enable X2APIC if we found there are any
initial CPU ID value >= 255.
This patch is to provide one chance for platform to enable X2APIC even there is
no any initial CPU ID value >= 255.
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../CpuCommonFeaturesLib/CpuCommonFeatures.h | 15 +
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c| 2 +-
UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 77 +++---
3 files changed, 83 insertions(+), 11 deletions(-)
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
index aa6d112..9a7afed 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
@@ -798,6 +798,21 @@ C1eInitialize (
);
/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+X2ApicGetConfigData (
+ IN UINTN NumberOfProcessors
+ );
+
+/**
Detects if X2Apci feature supported on current processor.
Detect if X2Apci has been already enabled.
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
index 3390aa8..793a095 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
@@ -211,7 +211,7 @@ CpuCommonFeaturesLibConstructor (
if (IsCpuFeatureSupported (CPU_FEATURE_X2APIC)) {
Status = RegisterCpuFeature (
"X2Apic",
- NULL,
+ X2ApicGetConfigData,
X2ApicSupport,
X2ApicInitialize,
CPU_FEATURE_X2APIC,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
index 9c2ad9a..6673c95 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
@@ -15,6 +15,28 @@
#include "CpuCommonFeatures.h"
/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+X2ApicGetConfigData (
+ IN UINTN NumberOfProcessors
+ )
+{
+ BOOLEAN*ConfigData;
+
+ ConfigData = AllocateZeroPool (sizeof (BOOLEAN) * NumberOfProcessors);
+ ASSERT (ConfigData != NULL);
+ return ConfigData;
+}
+
+/**
Detects if X2Apci feature supported on current processor.
Detect if X2Apci has been already enabled.
@@ -39,8 +61,17 @@ X2ApicSupport (
IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
IN VOID *ConfigData OPTIONAL
)
-{
- return (GetApicMode () == LOCAL_APIC_MODE_X2APIC);
+{
+ BOOLEAN*X2ApicEnabled;
+
+ ASSERT (ConfigData != NULL);
+ X2ApicEnabled = (BOOLEAN *) ConfigData;
+ //
+ // *ConfigData indicates if X2APIC enabled on current processor
+ //
+ X2ApicEnabled[ProcessorNumber] = (GetApicMode () == LOCAL_APIC_MODE_X2APIC)
? TRUE : FALSE;
+
+ return (CpuInfo->CpuIdVersionInfoEcx.Bits.x2APIC == 1);
}
/**
@@ -69,13 +100,39 @@ X2ApicInitialize (
IN BOOLEAN State
)
{
- PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (
-ProcessorNumber,
-Msr,
-MSR_IA32_APIC_BASE,
-MSR_IA32_APIC_BASE_REGISTER,
-Bits.EXTD,
-(State) ? 1 : 0
-);
+ BOOLEAN*X2ApicEnabled;
+
+ ASSERT (ConfigData != NULL);
+ X2ApicEnabled = (BOOLEAN *) ConfigData;
+ if (X2ApicEnabled[ProcessorNumber]) {
+if (!State) {
+ DEBUG ((DEBUG_ERROR, "X2APIC should be enabled by
PcdCpuFeaturesUserConfiguration!\n"));
+ ASSERT (FALSE);
+} else {
+ PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (
+ProcessorNumber,
+Msr,
+MSR_IA32_APIC_BASE,
+MSR_IA32_APIC_BASE_REGISTER,
+Bits.EXTD,
+1
+);
+}
+ } else {
+//
+// Enable X2APIC mode only if X2APIC is not enabled,
+// Needn't to disabe X2APIC mode again if X2APIC is not enabled
+//
+if (State) {
+ CPU_REGISTER_TABLE_WRITE_FIELD (
+ProcessorNumber,
+Msr,
+MSR_IA32_APIC_BASE,
+MSR_IA32_APIC_BASE_REGISTER,
+Bits.EXTD,
+1
+);
+
[edk2] [PATCH v2 0/2] Enable X2APIC after MP service is ready
https://bugzilla.tianocore.org/show_bug.cgi?id=575 v2: Updated #1 comments. Jeff Fan (2): UefiCpuPkg/CpuCommonFeaturesLib: Support X2APIC enable UefiCpuPkg/MpInitLib: Check APIC mode change around AP function .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 15 + .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c| 2 +- UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 77 +++--- UefiCpuPkg/Library/MpInitLib/MpLib.c | 24 +-- 4 files changed, 102 insertions(+), 16 deletions(-) -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 2/2] UefiCpuPkg/MpInitLib: Check APIC mode change around AP function
If APIC ID values are changed during AP functions execution, we need to update
new APIC ID values in local data structure accordingly.
But if APIC mode change happened during AP function execution, we do not support
APIC ID value changed.
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/MpInitLib/MpLib.c | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 735e099..c6f8191 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -547,6 +547,7 @@ ApWakeupFunction (
volatile UINT32*ApStartupSignalBuffer;
CPU_INFO_IN_HOB*CpuInfoInHob;
UINT64 ApTopOfStack;
+ UINTN CurrentApicMode;
//
// AP finished assembly code and begin to execute C code
@@ -560,6 +561,7 @@ ApWakeupFunction (
ProgramVirtualWireMode ();
SyncLocalApicTimerSetting (CpuMpData);
+ CurrentApicMode = GetApicMode ();
while (TRUE) {
if (CpuMpData->InitFlag == ApInitConfig) {
//
@@ -627,11 +629,23 @@ ApWakeupFunction (
ApStartupSignalBuffer =
CpuMpData->CpuData[ProcessorNumber].StartupApSignal;
CpuInfoInHob[ProcessorNumber].ApTopOfStack =
CpuInfoInHob[CpuMpData->NewBspNumber].ApTopOfStack;
} else {
-//
-// Re-get the CPU APICID and Initial APICID
-//
-CpuInfoInHob[ProcessorNumber].ApicId= GetApicId ();
-CpuInfoInHob[ProcessorNumber].InitialApicId = GetInitialApicId ();
+if (CpuInfoInHob[ProcessorNumber].ApicId != GetApicId () ||
+CpuInfoInHob[ProcessorNumber].InitialApicId !=
GetInitialApicId ()) {
+ if (CurrentApicMode != GetApicMode ()) {
+//
+// If APIC mode change happened during AP function execution,
+// we do not support APIC ID value changed.
+//
+ASSERT (FALSE);
+CpuDeadLoop ();
+ } else {
+//
+// Re-get the CPU APICID and Initial APICID if they are changed
+//
+CpuInfoInHob[ProcessorNumber].ApicId= GetApicId ();
+CpuInfoInHob[ProcessorNumber].InitialApicId = GetInitialApicId
();
+ }
+}
}
}
SetApState (>CpuData[ProcessorNumber], CpuStateFinished);
--
2.9.3.windows.2
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[edk2] [PATCH 0/2] Enable X2APIC after MP service is ready
https://bugzilla.tianocore.org/show_bug.cgi?id=575 Jeff Fan (2): UefiCpuPkg/CpuCommonFeaturesLib: Support X2APIC enable UefiCpuPkg/MpInitLib: Check APIC mode change around AP function .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 15 + .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c| 2 +- UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 76 +++--- UefiCpuPkg/Library/MpInitLib/MpLib.c | 24 +-- 4 files changed, 101 insertions(+), 16 deletions(-) -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 1/2] UefiCpuPkg/CpuCommonFeaturesLib: Support X2APIC enable
Current X2APIC is enabled in MpInitLib (used by CpuMpPei and CpuDxe) to follow
SDM suggestion. That means we only enable X2APIC if we found there are any
initial CPU ID value >= 255.
This patch is to provide one chance for platform to enable X2APIC even there is
no any initial CPU ID value >= 255.
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../CpuCommonFeaturesLib/CpuCommonFeatures.h | 15 +
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c| 2 +-
UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 76 +++---
3 files changed, 82 insertions(+), 11 deletions(-)
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
index aa6d112..9a7afed 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
@@ -798,6 +798,21 @@ C1eInitialize (
);
/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+X2ApicGetConfigData (
+ IN UINTN NumberOfProcessors
+ );
+
+/**
Detects if X2Apci feature supported on current processor.
Detect if X2Apci has been already enabled.
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
index 3390aa8..793a095 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
@@ -211,7 +211,7 @@ CpuCommonFeaturesLibConstructor (
if (IsCpuFeatureSupported (CPU_FEATURE_X2APIC)) {
Status = RegisterCpuFeature (
"X2Apic",
- NULL,
+ X2ApicGetConfigData,
X2ApicSupport,
X2ApicInitialize,
CPU_FEATURE_X2APIC,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
index 9c2ad9a..03d42a3 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
@@ -15,6 +15,28 @@
#include "CpuCommonFeatures.h"
/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+X2ApicGetConfigData (
+ IN UINTN NumberOfProcessors
+ )
+{
+ BOOLEAN*ConfigData;
+
+ ConfigData = AllocateZeroPool (sizeof (BOOLEAN) * NumberOfProcessors);
+ ASSERT (ConfigData != NULL);
+ return ConfigData;
+}
+
+/**
Detects if X2Apci feature supported on current processor.
Detect if X2Apci has been already enabled.
@@ -39,8 +61,17 @@ X2ApicSupport (
IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
IN VOID *ConfigData OPTIONAL
)
-{
- return (GetApicMode () == LOCAL_APIC_MODE_X2APIC);
+{
+ BOOLEAN*X2ApicEnabled;
+
+ ASSERT (ConfigData != NULL);
+ X2ApicEnabled = (BOOLEAN *) ConfigData;
+ //
+ // *ConfigData indicates if X2APIC enabled on current processor
+ //
+ X2ApicEnabled[ProcessorNumber] = (GetApicMode () == LOCAL_APIC_MODE_X2APIC)
? TRUE : FALSE;
+
+ return (CpuInfo->CpuIdVersionInfoEcx.Bits.x2APIC == 1);
}
/**
@@ -69,13 +100,38 @@ X2ApicInitialize (
IN BOOLEAN State
)
{
- PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (
-ProcessorNumber,
-Msr,
-MSR_IA32_APIC_BASE,
-MSR_IA32_APIC_BASE_REGISTER,
-Bits.EXTD,
-(State) ? 1 : 0
-);
+ BOOLEAN*X2ApicEnabled;
+
+ ASSERT (ConfigData != NULL);
+ X2ApicEnabled = (BOOLEAN *) ConfigData;
+ if (X2ApicEnabled[ProcessorNumber]) {
+if (!State) {
+ DEBUG ((DEBUG_ERROR, "X2APIC should be enabled by
PcdCpuFeaturesUserConfiguration!\n"));
+ ASSERT (FALSE);
+} else {
+ PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (
+ProcessorNumber,
+Msr,
+MSR_IA32_APIC_BASE,
+MSR_IA32_APIC_BASE_REGISTER,
+Bits.EXTD,
+1
+);
+}
+ } else {
+if (State) {
+ //
+ //
+ //
+ CPU_REGISTER_TABLE_WRITE_FIELD (
+ProcessorNumber,
+Msr,
+MSR_IA32_APIC_BASE,
+MSR_IA32_APIC_BASE_REGISTER,
+Bits.EXTD,
+1
+);
+}
+ }
return RETURN_SUCCESS;
}
--
2.9.3.windows.2
___
edk2-devel
[edk2] [PATCH] UefiCpuPkg/DxeMpInitLib.inf: Add missing SynchronizationLib
Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Eric Dong <eric.d...@intel.com> Signed-off-by: Jeff Fan <jeff@intel.com> --- UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf index 9751ba1..39fdc07 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf @@ -1,7 +1,7 @@ ## @file # MP Initialize Library instance for DXE driver. # -# Copyright (c) 2016, Intel Corporation. All rights reserved. +# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved. # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License # which accompanies this distribution. The full text of the license may be found at @@ -56,6 +56,7 @@ UefiCpuLib UefiBootServicesTableLib DebugAgentLib + SynchronizationLib [Protocols] gEfiTimerArchProtocolGuid ## SOMETIMES_CONSUMES -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Fix logic check error
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index 2713b19..9588eaf 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -267,7 +267,7 @@ IsInSmmRanges (
{
UINTN Index;
- if ((Address < mCpuHotPlugData.SmrrBase) || (Address >=
mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
+ if ((Address >= mCpuHotPlugData.SmrrBase) && (Address <
mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
return TRUE;
}
for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
--
2.9.3.windows.2
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[edk2] [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Check ProcessorId == INVALID_APIC_ID
If PcdCpuHotPlugSupport is TRUE, gSmst->NumberOfCpus will be the
PcdCpuMaxLogicalProcessorNumber. If gSmst->SmmStartupThisAp() is invoked for
those un-existed processors, ASSERT() happened in ConfigSmmCodeAccessCheck().
This fix is to check if ProcessorId is valid before invoke
gSmst->SmmStartupThisAp() in ConfigSmmCodeAccessCheck() and to check if
ProcessorId is valid in InternalSmmStartupThisAp() to avoid unexpected DEBUG
error message displayed.
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 3 +++
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 7 ++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index e03f1e0..4ac5e8e 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -860,6 +860,9 @@ InternalSmmStartupThisAp (
DEBUG((DEBUG_ERROR, "CpuIndex(%d) ==
gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu\n", CpuIndex));
return EFI_INVALID_PARAMETER;
}
+ if (gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId == INVALID_APIC_ID) {
+return EFI_INVALID_PARAMETER;
+ }
if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) {
if (mSmmMpSyncData->EffectiveSyncMode == SmmCpuSyncModeTradition) {
DEBUG((DEBUG_ERROR, "!mSmmMpSyncData->CpuData[%d].Present\n", CpuIndex));
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 2d6b572..8e79642 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -1117,7 +1117,12 @@ ConfigSmmCodeAccessCheck (
//
for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
if (Index != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {
-
+ if (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID)
{
+//
+// If this processor does not exist
+//
+continue;
+ }
//
// Acquire Config SMM Code Access Check spin lock. The AP will release
the
// spin lock when it is done executing
ConfigSmmCodeAccessCheckOnCurrentProcessor().
--
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[edk2] [PATCH 0/2] Fix SmmCpuFeaturesLib issues
Jeff Fan (2): UefiCpuPkg/SmmCpuFeaturesLib: Fix Ia32/SmiEntry.asm build issue UefiCpuPkg/SmmCpuFeaturesLib: Correct print level UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm| 6 +++--- .../Library/SmmCpuFeaturesLib/Ia32/SmiException.asm | 15 ++- UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 8 3 files changed, 17 insertions(+), 12 deletions(-) -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Fix Ia32/SmiEntry.asm build issue
Cc: Jiewen Yao <jiewen@intel.com> Cc: Eric Dong <eric.d...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff@intel.com> --- UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm| 6 +++--- .../Library/SmmCpuFeaturesLib/Ia32/SmiException.asm | 15 ++- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm index 94888d5..91dc1eb 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm @@ -1,5 +1,5 @@ ;-- ; -; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved. +; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved. ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BSD License ; which accompanies this distribution. The full text of the license may be found at @@ -201,7 +201,7 @@ CommonHandler: calleax add esp, 4 -mov eax, gStmXdSupported +mov eax, offset gStmXdSupported mov al, [eax] cmp al, 0 jz @f @@ -221,7 +221,7 @@ _StmSmiHandler: ; Check XD disable bit ; xor esi, esi -mov eax, gStmXdSupported +mov eax, offset gStmXdSupported mov al, [eax] cmp al, 0 jz @StmXdDone diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm index 7c04ad9..d0ae147 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm @@ -1,5 +1,5 @@ ;-- ; -; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved. +; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved. ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BSD License ; which accompanies this distribution. The full text of the license may be found at @@ -26,11 +26,16 @@ EXTERNDEF gcStmPsd:BYTE EXTERNDEF SmmStmExceptionHandler:PROC EXTERNDEF SmmStmSetup:PROC EXTERNDEF SmmStmTeardown:PROC +EXTERNDEF gStmXdSupported:BYTE CODE_SEL= 08h DATA_SEL= 20h TSS_SEL = 40h +MSR_IA32_MISC_ENABLE EQU 1A0h +MSR_EFER EQU 0c080h +MSR_EFER_XD EQU 0800h + .data gcStmPsd LABEL BYTE @@ -88,7 +93,7 @@ _OnStmSetup PROC ; Check XD disable bit ; xor esi, esi -mov eax, gStmXdSupported +mov eax, offset gStmXdSupported mov al, [eax] cmp al, 0 jz @StmXdDone1 @@ -109,7 +114,7 @@ _OnStmSetup PROC call SmmStmSetup -mov eax, gStmXdSupported +mov eax, offset gStmXdSupported mov al, [eax] cmp al, 0 jz @f @@ -130,7 +135,7 @@ _OnStmTeardown PROC ; Check XD disable bit ; xor esi, esi -mov eax, gStmXdSupported +mov eax, offset gStmXdSupported mov al, [eax] cmp al, 0 jz @StmXdDone2 @@ -151,7 +156,7 @@ _OnStmTeardown PROC call SmmStmTeardown -mov eax, gStmXdSupported +mov eax, offset gStmXdSupported mov al, [eax] cmp al, 0 jz @f -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 2/2] UefiCpuPkg/SmmCpuFeaturesLib: Correct print level
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Eric Dong <eric.d...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
index 03937dc..45015b8 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
@@ -326,8 +326,8 @@ SmmCpuFeaturesInstallSmiHandler (
Psd->SmmSmiHandlerRsp = (UINTN)SmiStack + StackSize - sizeof(UINTN);
Psd->SmmCr3 = Cr3;
- DEBUG((DEBUG_ERROR, "CpuSmmStmExceptionStackSize - %x\n",
PcdGet32(PcdCpuSmmStmExceptionStackSize)));
- DEBUG((DEBUG_ERROR, "Pages - %x\n",
EFI_SIZE_TO_PAGES(PcdGet32(PcdCpuSmmStmExceptionStackSize;
+ DEBUG((DEBUG_INFO, "CpuSmmStmExceptionStackSize - %x\n",
PcdGet32(PcdCpuSmmStmExceptionStackSize)));
+ DEBUG((DEBUG_INFO, "Pages - %x\n",
EFI_SIZE_TO_PAGES(PcdGet32(PcdCpuSmmStmExceptionStackSize;
Psd->StmProtectionExceptionHandler.SpeRsp = (UINT64)(UINTN)AllocatePages
(EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize)));
Psd->StmProtectionExceptionHandler.SpeRsp += EFI_PAGES_TO_SIZE
(EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize)));
@@ -735,7 +735,7 @@ ValidateResource (
Resource = ResourceList;
for (Index = 0; Index < Count; Index++) {
-DEBUG ((DEBUG_ERROR, "ValidateResource (%d) - RscType(%x)\n", Index,
Resource->Header.RscType));
+DEBUG ((DEBUG_INFO, "ValidateResource (%d) - RscType(%x)\n", Index,
Resource->Header.RscType));
//
// Validate resource.
//
@@ -782,7 +782,7 @@ ValidateResource (
break;
case PCI_CFG_RANGE:
-DEBUG ((DEBUG_ERROR, "ValidateResource - PCI (0x%02x, 0x%08x, 0x%02x,
0x%02x)\n", Resource->PciCfg.OriginatingBusNumber,
Resource->PciCfg.LastNodeIndex, Resource->PciCfg.PciDevicePath[0].PciDevice,
Resource->PciCfg.PciDevicePath[0].PciFunction));
+DEBUG ((DEBUG_INFO, "ValidateResource - PCI (0x%02x, 0x%08x, 0x%02x,
0x%02x)\n", Resource->PciCfg.OriginatingBusNumber,
Resource->PciCfg.LastNodeIndex, Resource->PciCfg.PciDevicePath[0].PciDevice,
Resource->PciCfg.PciDevicePath[0].PciFunction));
if (Resource->Header.Length != sizeof (STM_RSC_PCI_CFG_DESC) +
(sizeof(STM_PCI_DEVICE_PATH_NODE) * Resource->PciCfg.LastNodeIndex)) {
return FALSE;
}
--
2.9.3.windows.2
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[edk2] [PATCH v2] UefiCpuPkg: Update package version to 0.80
Cc: Feng Tian <feng.t...@intel.com> Cc: Eric Dong <eric.d...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff@intel.com> --- UefiCpuPkg/UefiCpuPkg.dec | 2 +- UefiCpuPkg/UefiCpuPkg.dsc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 6f30ad0..e5b0334 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -18,7 +18,7 @@ PACKAGE_NAME = UefiCpuPkg PACKAGE_UNI_FILE = UefiCpuPkg.uni PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23 - PACKAGE_VERSION= 0.3 + PACKAGE_VERSION= 0.80 [Includes] Include diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 1336b0c..41cf809 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -16,7 +16,7 @@ [Defines] PLATFORM_NAME = UefiCpu PLATFORM_GUID = a1b7be22-78b3-4260-9569-8649e8c17d49 - PLATFORM_VERSION = 0.3 + PLATFORM_VERSION = 0.80 DSC_SPECIFICATION = 0x00010005 OUTPUT_DIRECTORY = Build/UefiCpu SUPPORTED_ARCHITECTURES= IA32|IPF|X64 -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH] UefiCpuPkg: Update package version to 0.80
Cc: Feng Tian <feng.t...@intel.com> Cc: Eric Dong <eric.d...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff@intel.com> --- UefiCpuPkg/UefiCpuPkg.dec | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 6f30ad0..e5b0334 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -18,7 +18,7 @@ PACKAGE_NAME = UefiCpuPkg PACKAGE_UNI_FILE = UefiCpuPkg.uni PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23 - PACKAGE_VERSION= 0.3 + PACKAGE_VERSION= 0.80 [Includes] Include -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH v2] UefiCpuPkg/MpLib.c: Set AP state after X2APIC mode enabled
After X2APIC mode is enabled, APs need to be set tp IDLE state, otherwise APs
cannot be waken up by MP PPI services.
https://bugzilla.tianocore.org/show_bug.cgi?id=505
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/MpInitLib/MpLib.c | 8
1 file changed, 8 insertions(+)
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 03d6c2d..e502e36 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -434,6 +434,8 @@ CollectProcessorCount (
IN CPU_MP_DATA *CpuMpData
)
{
+ UINTN Index;
+
//
// Send 1st broadcast IPI to APs to wakeup APs
//
@@ -465,6 +467,12 @@ CollectProcessorCount (
// Enable x2APIC on BSP
//
SetApicMode (LOCAL_APIC_MODE_X2APIC);
+//
+// Set BSP/Aps state to IDLE
+//
+for (Index = 0; Index < CpuMpData->CpuCount; Index++) {
+ SetApState (>CpuData[Index], CpuStateIdle);
+}
}
DEBUG ((DEBUG_INFO, "APIC MODE is %d\n", GetApicMode ()));
//
--
2.9.3.windows.2
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[edk2] [PATCH] UefiCpuPkg/MpLib.c: Set AP state after X2APIC mode enabled
After X2APIC mode is enabled, APs need to be set tp IDLE state, otherwise APs
cannot be waken up by MP PPI services.
https://bugzilla.tianocore.org/show_bug.cgi?id=500
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/MpInitLib/MpLib.c | 8
1 file changed, 8 insertions(+)
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 03d6c2d..e502e36 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -434,6 +434,8 @@ CollectProcessorCount (
IN CPU_MP_DATA *CpuMpData
)
{
+ UINTN Index;
+
//
// Send 1st broadcast IPI to APs to wakeup APs
//
@@ -465,6 +467,12 @@ CollectProcessorCount (
// Enable x2APIC on BSP
//
SetApicMode (LOCAL_APIC_MODE_X2APIC);
+//
+// Set BSP/Aps state to IDLE
+//
+for (Index = 0; Index < CpuMpData->CpuCount; Index++) {
+ SetApState (>CpuData[Index], CpuStateIdle);
+}
}
DEBUG ((DEBUG_INFO, "APIC MODE is %d\n", GetApicMode ()));
//
--
2.9.3.windows.2
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[edk2] [PATCH] PeCoffGetEntryPointLib: Fix spelling issue
*Serach* should be *Search*
Cc: Liming Gao <liming@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
MdePkg/Include/Library/PeCoffGetEntryPointLib.h | 2 +-
MdePkg/Library/BasePeCoffGetEntryPointLib/PeCoffGetEntryPoint.c | 2 +-
SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.c | 2 +-
UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c | 2 +-
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
b/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
index 647503b..f211cf5 100644
--- a/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
+++ b/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
@@ -115,7 +115,7 @@ PeCoffGetSizeOfHeaders (
**/
UINTN
EFIAPI
-PeCoffSerachImageBase (
+PeCoffSearchImageBase (
IN UINTNAddress
);
diff --git a/MdePkg/Library/BasePeCoffGetEntryPointLib/PeCoffGetEntryPoint.c
b/MdePkg/Library/BasePeCoffGetEntryPointLib/PeCoffGetEntryPoint.c
index 00f6d7d..e1ddc8b 100644
--- a/MdePkg/Library/BasePeCoffGetEntryPointLib/PeCoffGetEntryPoint.c
+++ b/MdePkg/Library/BasePeCoffGetEntryPointLib/PeCoffGetEntryPoint.c
@@ -332,7 +332,7 @@ PeCoffGetSizeOfHeaders (
**/
UINTN
EFIAPI
-PeCoffSerachImageBase (
+PeCoffSearchImageBase (
IN UINTNAddress
)
{
diff --git
a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.c
b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.c
index 6f3c419..f156fe2 100644
--- a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.c
+++ b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.c
@@ -206,7 +206,7 @@ FindAndReportModuleImageInfo (
//
// Find Image Base
//
- Pe32Data = PeCoffSerachImageBase ((UINTN) mErrorMsgVersionAlert);
+ Pe32Data = PeCoffSearchImageBase ((UINTN) mErrorMsgVersionAlert);
if (Pe32Data != 0) {
ImageContext.ImageAddress = Pe32Data;
ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN)
ImageContext.ImageAddress);
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
index 78ee182..dbfaae1 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
@@ -120,7 +120,7 @@ DumpModuleImageInfo (
VOID *PdbPointer;
VOID *EntryPoint;
- Pe32Data = PeCoffSerachImageBase (CurrentEip);
+ Pe32Data = PeCoffSearchImageBase (CurrentEip);
if (Pe32Data == 0) {
InternalPrintMessage (" Can't find image information. \n");
} else {
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 2cb0bbc..2d6b572 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -178,7 +178,7 @@ DumpModuleInfoByIp (
//
// Find Image Base
//
- Pe32Data = PeCoffSerachImageBase (CallerIpAddress);
+ Pe32Data = PeCoffSearchImageBase (CallerIpAddress);
if (Pe32Data != 0) {
DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)",
(VOID *) CallerIpAddress));
PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);
--
2.9.3.windows.2
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[edk2] [PATCH] PeCoffGetEntryPointLib: Fix spelling issue
*Serach* should be *Search*. This is an incompatible change of library API name. But this API was introduced a couple of weeks ago, this fix should be low impact. To make sure build pass on each commit, I create one single patch across packages updating for this typo fix. https://bugzilla.tianocore.org/show_bug.cgi?id=503 Cc: Liming Gao <liming@intel.com> Cc: Feng Tian <feng.t...@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff....@intel.com> Jeff Fan (1): PeCoffGetEntryPointLib: Fix spelling issue MdePkg/Include/Library/PeCoffGetEntryPointLib.h | 2 +- MdePkg/Library/BasePeCoffGetEntryPointLib/PeCoffGetEntryPoint.c | 2 +- SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.c | 2 +- UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c | 2 +- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 2/2] UefiCpuPkg/MpInitLib: needn't to allocate AP reset vector
Because we will always borrow the AP reset vector space for AP waking up. We
needn't allocate such range to prevent other module to use it. It could simply
the code.
https://bugzilla.tianocore.org/show_bug.cgi?id=500
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/MpInitLib/MpLib.h | 22 +--
UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 6 +-
UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 93 ---
3 files changed, 2 insertions(+), 119 deletions(-)
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h
b/UefiCpuPkg/Library/MpInitLib/MpLib.h
index 7a272d7..989b3f8 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.h
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h
@@ -1,7 +1,7 @@
/** @file
Common header file for MP Initialize Library.
- Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -542,26 +542,6 @@ IsMwaitSupport (
);
/**
- Notify function on End Of PEI PPI.
-
- On S3 boot, this function will restore wakeup buffer data.
- On normal boot, this function will flag wakeup buffer to be un-used type.
-
- @param[in] PeiServicesThe pointer to the PEI Services Table.
- @param[in] NotifyDescriptor Address of the notification descriptor data
structure.
- @param[in] PpiAddress of the PPI that was installed.
-
- @retval EFI_SUCCESSWhen everything is OK.
-**/
-EFI_STATUS
-EFIAPI
-CpuMpEndOfPeiCallback (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_NOTIFY_DESCRIPTOR*NotifyDescriptor,
- IN VOID *Ppi
- );
-
-/**
Get available system memory below 1MB by specified size.
@param[in] CpuMpData The pointer to CPU MP Data structure.
diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
index 0c6873d..fa84e39 100644
--- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
@@ -1,7 +1,7 @@
## @file
# MP Initialize Library instance for PEI driver.
#
-# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD
License
# which accompanies this distribution. The full text of the license may be
found at
@@ -50,15 +50,11 @@
LocalApicLib
MemoryAllocationLib
HobLib
- PeiServicesLib
MtrrLib
CpuLib
UefiCpuLib
SynchronizationLib
-[Ppis]
- gEfiEndOfPeiSignalPpiGuid ## NOTIFY
-
[Pcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds ## CONSUMES
diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
index 5ce5788..9ee5aca 100644
--- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
@@ -13,18 +13,6 @@
**/
#include "MpLib.h"
-#include
-#include
-
-//
-// Global PEI notify function descriptor on EndofPei event
-//
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_NOTIFY_DESCRIPTOR mMpInitLibNotifyList =
{
- (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- ,
- CpuMpEndOfPeiCallback
-};
-
/**
Enable Debug Agent to support source debugging on AP function.
@@ -77,64 +65,6 @@ SaveCpuMpData (
}
/**
- Notify function on End Of PEI PPI.
-
- On S3 boot, this function will restore wakeup buffer data.
- On normal boot, this function will flag wakeup buffer to be un-used type.
-
- @param[in] PeiServicesThe pointer to the PEI Services Table.
- @param[in] NotifyDescriptor Address of the notification descriptor data
structure.
- @param[in] PpiAddress of the PPI that was installed.
-
- @retval EFI_SUCCESSWhen everything is OK.
-**/
-EFI_STATUS
-EFIAPI
-CpuMpEndOfPeiCallback (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_NOTIFY_DESCRIPTOR*NotifyDescriptor,
- IN VOID *Ppi
- )
-{
- EFI_STATUSStatus;
- EFI_BOOT_MODE BootMode;
- CPU_MP_DATA *CpuMpData;
- EFI_PEI_HOB_POINTERS Hob;
- EFI_HOB_MEMORY_ALLOCATION *MemoryHob;
-
- DEBUG ((DEBUG_INFO, "PeiMpInitLib: CpuMpEndOfPeiCallback () invoked\n"));
-
- Status = PeiServicesGetBootMode ();
- ASSERT_EFI_ERROR (Status);
-
- CpuMpData = GetCpuMpData ()
[edk2] [PATCH 0/2] Borrow the space below 1MB for AP reset vector
Current, CpuMpPei will find the available memory space below 1MB for AP reset vector. And CpuMpPei will build resource HOB on this range to prevent other PEI modules to use this range. However, on some FSP usage model, this range maybe used by the code out of FSP. CpuMpPei may change the original memory contents and cause other code crash. We could update CpuMpPei not to change the original contents of this range around AP waking up. Thus, it will not impact the other code on FSP usage model. This updating is tiny and less impact on performance. https://bugzilla.tianocore.org/show_bug.cgi?id=500 Cc: Feng Tian <feng.t...@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff....@intel.com> Jeff Fan (2): UefiCpuPkg/MpInitLib: save/restore original contents UefiCpuPkg/MpInitLib: needn't to allocate AP reset vector UefiCpuPkg/Library/MpInitLib/MpLib.h | 22 +- UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 6 +- UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 107 +- 3 files changed, 5 insertions(+), 130 deletions(-) -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 1/2] UefiCpuPkg/MpInitLib: save/restore original contents
If APs is in HLT-LOOP mode, we need AP reset vector for waking up APs. This
updating is to save/restore original contents of AP reset vector around waking
up APs always.
https://bugzilla.tianocore.org/show_bug.cgi?id=500
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
index fb1d48f..5ce5788 100644
--- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
@@ -1,7 +1,7 @@
/** @file
MP initialize support functions for PEI phase.
- Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -129,10 +129,8 @@ CpuMpEndOfPeiCallback (
}
Hob.Raw = GET_NEXT_HOB (Hob);
}
- } else {
-CpuMpData->SaveRestoreFlag = TRUE;
-RestoreWakeupBuffer (CpuMpData);
}
+
return EFI_SUCCESS;
}
@@ -286,12 +284,8 @@ AllocateResetVector (
CpuMpData->WakeupBuffer = GetWakeupBuffer (ApResetVectorSize);
CpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN)
(CpuMpData->WakeupBuffer +
CpuMpData->AddressMap.RendezvousFunnelSize);
-BackupAndPrepareWakeupBuffer (CpuMpData);
- }
-
- if (CpuMpData->SaveRestoreFlag) {
-BackupAndPrepareWakeupBuffer (CpuMpData);
}
+ BackupAndPrepareWakeupBuffer (CpuMpData);
}
/**
@@ -304,9 +298,7 @@ FreeResetVector (
IN CPU_MP_DATA *CpuMpData
)
{
- if (CpuMpData->SaveRestoreFlag) {
-RestoreWakeupBuffer (CpuMpData);
- }
+ RestoreWakeupBuffer (CpuMpData);
}
/**
--
2.9.3.windows.2
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[edk2] [PATCH] UefiCpuPkg: Move ProgramVirtualWireMode() to MpInitLib
In PEI phase, BSP did not program vitural wired mode while APs did.
Move program virtual wired mode from CpuDxe to MpInitLib, thus it could benefit
on both CpuDxe and CpuMpPei.
https://bugzilla.tianocore.org/show_bug.cgi?id=496
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/CpuDxe/CpuDxe.c | 5 -
UefiCpuPkg/Library/MpInitLib/MpLib.c | 4
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c
index 4a5e282..8680656 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.c
@@ -1136,11 +1136,6 @@ InitializeCpu (
InitInterruptDescriptorTable ();
//
- // Enable the local APIC for Virtual Wire Mode.
- //
- ProgramVirtualWireMode ();
-
- //
// Install CPU Architectural Protocol
//
Status = gBS->InstallMultipleProtocolInterfaces (
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 03d6c2d..e5e211d 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -1364,6 +1364,10 @@ MpInitLibInitialize (
// Store BSP's MTRR setting
//
MtrrGetAllMtrrs (>MtrrTable);
+ //
+ // Enable the local APIC for Virtual Wire Mode.
+ //
+ ProgramVirtualWireMode ();
if (OldCpuMpData == NULL) {
if (MaxLogicalProcessorNumber > 1) {
--
2.9.3.windows.2
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[edk2] [PATCH] MdeModulePkg/FirmwarePerformanceDxe: Error Level is not used correctly
Cc: Feng Tian <feng.t...@intel.com>
Cc: Star Zeng <star.z...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
a/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.c
b/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.c
index 6f6ea07..b004cac 100644
---
a/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.c
+++
b/MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.c
@@ -5,7 +5,7 @@
for Firmware Basic Boot Performance Record and other boot performance
records,
and install FPDT to ACPI table.
- Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -876,7 +876,7 @@ FirmwarePerformanceDxeEntryPoint (
//
// SEC Performance Data Hob not found, ResetEnd in ACPI FPDT table will be
0.
//
-DEBUG ((EFI_D_ERROR, "FPDT: WARNING: SEC Performance Data Hob not found,
ResetEnd will be set to 0!\n"));
+DEBUG ((DEBUG_WARN, "FPDT: WARNING: SEC Performance Data Hob not found,
ResetEnd will be set to 0!\n"));
}
if (FeaturePcdGet (PcdFirmwarePerformanceDataTableS3Support)) {
--
2.9.3.windows.2
___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Lock should be acquired
SMM BSP's *busy* state should be acquired. We could use AcquireSpinLock() instead of AcquireSpinLockOrFail(). Cc: Hao Wu <hao.a...@intel.com> Cc: Feng Tian <feng.t...@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff@intel.com> --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index a1d16b4..e03f1e0 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -407,7 +407,7 @@ BSPHandler ( // // The BUSY lock is initialized to Acquired state // - AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[CpuIndex].Busy); + AcquireSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); // // Perform the pre tasks -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 1/3] MdeModulePkg: Error Level is not used correctly
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c | 10 +-
.../Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c | 4 ++--
MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c | 2 +-
MdeModulePkg/Universal/CapsulePei/UefiCapsule.c| 2 +-
.../Universal/CapsuleRuntimeDxe/X64/SaveLongModeContext.c | 4 ++--
MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.c | 10 +-
.../Universal/PlatformDriOverrideDxe/PlatDriOverrideDxe.c | 4 ++--
7 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
index 5147e66..4545d6e 100644
--- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
+++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/ScriptExecute.c
@@ -103,7 +103,7 @@ S3BootScriptExecutorEntryFunction (
//
// X64 S3 Resume
//
- DEBUG ((EFI_D_ERROR, "Call AsmDisablePaging64() to return to S3 Resume
in PEI Phase\n"));
+ DEBUG ((DEBUG_INFO, "Call AsmDisablePaging64() to return to S3 Resume in
PEI Phase\n"));
PeiS3ResumeState->AsmTransferControl =
(EFI_PHYSICAL_ADDRESS)(UINTN)AsmTransferControl32;
if ((Facs != NULL) &&
@@ -128,7 +128,7 @@ S3BootScriptExecutorEntryFunction (
//
// IA32 S3 Resume
//
- DEBUG ((EFI_D_ERROR, "Call SwitchStack() to return to S3 Resume in PEI
Phase\n"));
+ DEBUG ((DEBUG_INFO, "Call SwitchStack() to return to S3 Resume in PEI
Phase\n"));
PeiS3ResumeState->AsmTransferControl =
(EFI_PHYSICAL_ADDRESS)(UINTN)AsmTransferControl;
SwitchStack (
@@ -160,7 +160,7 @@ S3BootScriptExecutorEntryFunction (
//
// X64 long mode waking vector
//
- DEBUG (( EFI_D_ERROR, "Transfer to 64bit OS waking vector - %x\r\n",
(UINTN)Facs->XFirmwareWakingVector));
+ DEBUG ((DEBUG_INFO, "Transfer to 64bit OS waking vector - %x\r\n",
(UINTN)Facs->XFirmwareWakingVector));
if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
SwitchStack (
(SWITCH_STACK_ENTRY_POINT)(UINTN)Facs->XFirmwareWakingVector,
@@ -177,7 +177,7 @@ S3BootScriptExecutorEntryFunction (
//
// IA32 protected mode waking vector (Page disabled)
//
- DEBUG (( EFI_D_ERROR, "Transfer to 32bit OS waking vector - %x\r\n",
(UINTN)Facs->XFirmwareWakingVector));
+ DEBUG ((DEBUG_INFO, "Transfer to 32bit OS waking vector - %x\r\n",
(UINTN)Facs->XFirmwareWakingVector));
if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
AsmDisablePaging64 (
0x10,
@@ -199,7 +199,7 @@ S3BootScriptExecutorEntryFunction (
//
// 16bit Realmode waking vector
//
-DEBUG (( EFI_D_ERROR, "Transfer to 16bit OS waking vector - %x\r\n",
(UINTN)Facs->FirmwareWakingVector));
+DEBUG ((DEBUG_INFO, "Transfer to 16bit OS waking vector - %x\r\n",
(UINTN)Facs->FirmwareWakingVector));
AsmTransferControl (Facs->FirmwareWakingVector, 0x0);
}
diff --git
a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
index d433cf1..70eecf5 100644
--- a/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
+++ b/MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c
@@ -3,7 +3,7 @@
Set a IDT entry for interrupt vector 3 for debug purpose for x64 platform
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
@@ -234,7 +234,7 @@ PageFaultHandler (
UINTN PTIndex;
PFAddress = AsmReadCr2 ();
- DEBUG ((EFI_D_ERROR, "BootScript - PageFaultHandler: Cr2 - %lx\n",
PFAddress));
+ DEBUG ((DEBUG_INFO, "BootScript - PageFaultHandler: Cr2 - %lx\n",
PFAddress));
if (PFAddress >= mPhyMask + SIZE_4KB) {
return FALSE;
diff --git a/MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c
b/MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c
index dcfd61c..3c05558 100644
--- a/MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c
+++ b/MdeModulePkg/Universal/Acpi/S3SaveStateDxe/AcpiS3ContextSave.c
@@ -407,7 +407,7 @@ S3AllocatePageTablesBuffer (
}
TotalPageTableSize += ExtraPageTablePages;
-DEBUG ((EFI_D_ERROR, "AcpiS3ContextSave TotalPageTableSize - 0x%x
pages\n", TotalPageTableSize));
+DEBUG ((DEBUG_INFO, "AcpiS3ContextSave TotalPageTableSize - 0x%x pages\n",
TotalPageTableS
[edk2] [PATCH 0/3] Error Level is not used correctly
Some modules mis-used error level when outputting debug message. Jeff Fan (3): MdeModulePkg: Error Level is not used correctly SecurityPkg: Error Level is not used correctly UefiCpuPkg: Error Level is not used correctly .../Acpi/BootScriptExecutorDxe/ScriptExecute.c | 10 ++-- .../Acpi/BootScriptExecutorDxe/X64/SetIdtEntry.c | 4 +- .../Acpi/S3SaveStateDxe/AcpiS3ContextSave.c| 2 +- MdeModulePkg/Universal/CapsulePei/UefiCapsule.c| 2 +- .../CapsuleRuntimeDxe/X64/SaveLongModeContext.c| 4 +- .../Universal/LockBox/SmmLockBox/SmmLockBox.c | 10 ++-- .../PlatformDriOverrideDxe/PlatDriOverrideDxe.c| 4 +- .../Tpm2DeviceLibRouter/Tpm2DeviceLibRouterDxe.c | 4 +- .../Tpm2DeviceLibRouter/Tpm2DeviceLibRouterPei.c | 4 +- SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.c | 2 +- SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.c | 4 +- SecurityPkg/Tcg/TrEEDxe/TrEEDxe.c | 4 +- SecurityPkg/Tcg/TrEEPei/TrEEPei.c | 4 +- UefiCpuPkg/CpuDxe/CpuPageTable.c | 2 +- UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 68 +++--- 15 files changed, 64 insertions(+), 64 deletions(-) -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 2/3] SecurityPkg: Error Level is not used correctly
Cc: Jiewen Yao <jiewen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterDxe.c | 4 ++--
SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterPei.c | 4 ++--
SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.c| 2 +-
SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.c| 4 ++--
SecurityPkg/Tcg/TrEEDxe/TrEEDxe.c| 4 ++--
SecurityPkg/Tcg/TrEEPei/TrEEPei.c| 4 ++--
6 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterDxe.c
b/SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterDxe.c
index 1e8c354..eedc439 100644
--- a/SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterDxe.c
+++ b/SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterDxe.c
@@ -3,7 +3,7 @@
via PcdTpmInstanceGuid. Platform need make choice that which one will be
final one.
At most one TPM2 instance can be finally registered, and other will return
unsupported.
-Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -89,7 +89,7 @@ Tpm2RegisterTpm2DeviceLib (
)
{
if (!CompareGuid (PcdGetPtr(PcdTpmInstanceGuid), >ProviderGuid)){
-DEBUG ((EFI_D_ERROR, "WARNING: Tpm2RegisterTpm2DeviceLib - does not
support %g registration\n", >ProviderGuid));
+DEBUG ((DEBUG_WARN, "WARNING: Tpm2RegisterTpm2DeviceLib - does not support
%g registration\n", >ProviderGuid));
return EFI_UNSUPPORTED;
}
diff --git a/SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterPei.c
b/SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterPei.c
index 0211399..7470fe3 100644
--- a/SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterPei.c
+++ b/SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRouterPei.c
@@ -3,7 +3,7 @@
via PcdTpmInstanceGuid. Platform need make choice that which one will be
final one.
At most one TPM2 instance can be finally registered, and other will return
unsupported.
-Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -120,7 +120,7 @@ Tpm2RegisterTpm2DeviceLib (
TPM2_DEVICE_INTERFACE *Tpm2DeviceInterface;
if (!CompareGuid (PcdGetPtr(PcdTpmInstanceGuid), >ProviderGuid)){
-DEBUG ((EFI_D_ERROR, "WARNING: Tpm2RegisterTpm2DeviceLib - does not
support %g registration\n", >ProviderGuid));
+DEBUG ((DEBUG_WARN, "WARNING: Tpm2RegisterTpm2DeviceLib - does not support
%g registration\n", >ProviderGuid));
return EFI_UNSUPPORTED;
}
diff --git a/SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.c
b/SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.c
index 53de666..c2c52e3 100644
--- a/SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.c
+++ b/SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.c
@@ -2466,7 +2466,7 @@ DriverEntry (
if (CompareGuid (PcdGetPtr(PcdTpmInstanceGuid),
) ||
CompareGuid (PcdGetPtr(PcdTpmInstanceGuid),
)){
-DEBUG ((EFI_D_ERROR, "No TPM2 instance required!\n"));
+DEBUG ((DEBUG_INFO, "No TPM2 instance required!\n"));
return EFI_UNSUPPORTED;
}
diff --git a/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.c
b/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.c
index 209d843..69adad4 100644
--- a/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.c
+++ b/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.c
@@ -1,7 +1,7 @@
/** @file
Initialize TPM2 device and measure FVs before handing off control to DXE.
-Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -736,7 +736,7 @@ PeimEntryMA (
if (CompareGuid (PcdGetPtr(PcdTpmInstanceGuid),
) ||
CompareGuid (PcdGetPtr(PcdTpmInstanceGuid),
)){
-DEBUG ((EFI_D_ERROR, "No TPM2 instance required!\n"));
+DEBUG ((DEBUG_INFO, "No TPM2 instance required!\n"));
return EFI_UNSUPPORTED;
}
diff --git a/SecurityPkg/Tcg/TrEEDxe/TrEEDxe.c
b/SecurityPkg/Tcg/TrEEDxe/TrEEDxe.c
index fb69fa1..95e9d74 100644
--- a/SecurityPkg/Tcg/TrEEDxe/TrEEDxe.c
+++ b/SecurityPkg/Tcg/TrEEDxe/TrEEDxe.c
@@ -1,7 +1,7 @@
/*
[edk2] [PATCH 3/3] UefiCpuPkg: Error Level is not used correctly
Cc: Feng Tian <feng.t...@intel.com>
Cc: Jiewen Yao <jiewen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/CpuDxe/CpuPageTable.c | 2 +-
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 68 +++
2 files changed, 35 insertions(+), 35 deletions(-)
diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTable.c
index ab664b4..2c61e75 100644
--- a/UefiCpuPkg/CpuDxe/CpuPageTable.c
+++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c
@@ -634,10 +634,10 @@ ConvertMemoryPageAttributes (
switch(CurrentPagingContext.MachineType) {
case IMAGE_FILE_MACHINE_I386:
if (CurrentPagingContext.ContextData.Ia32.PageTableBase == 0) {
- DEBUG ((DEBUG_ERROR, "PageTable is 0!\n"));
if (Attributes == 0) {
return EFI_SUCCESS;
} else {
+DEBUG ((DEBUG_ERROR, "PageTable is 0!\n"));
return EFI_UNSUPPORTED;
}
}
diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
index a9d1042..e53ed21 100644
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
@@ -4,7 +4,7 @@
This module will execute the boot script saved during last boot and after
that,
control is passed to OS waking up handler.
- Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
This program and the accompanying materials
@@ -531,7 +531,7 @@ S3ResumeBootOs (
//
// X64 long mode waking vector
//
- DEBUG (( EFI_D_ERROR, "Transfer to 64bit OS waking vector - %x\r\n",
(UINTN)Facs->XFirmwareWakingVector));
+ DEBUG ((DEBUG_INFO, "Transfer to 64bit OS waking vector - %x\r\n",
(UINTN)Facs->XFirmwareWakingVector));
if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
AsmEnablePaging64 (
0x38,
@@ -557,7 +557,7 @@ S3ResumeBootOs (
//
// IA32 protected mode waking vector (Page disabled)
//
- DEBUG (( EFI_D_ERROR, "Transfer to 32bit OS waking vector - %x\r\n",
(UINTN)Facs->XFirmwareWakingVector));
+ DEBUG ((DEBUG_INFO, "Transfer to 32bit OS waking vector - %x\r\n",
(UINTN)Facs->XFirmwareWakingVector));
SwitchStack (
(SWITCH_STACK_ENTRY_POINT) (UINTN) Facs->XFirmwareWakingVector,
NULL,
@@ -569,7 +569,7 @@ S3ResumeBootOs (
//
// 16bit Realmode waking vector
//
-DEBUG (( EFI_D_ERROR, "Transfer to 16bit OS waking vector - %x\r\n",
(UINTN)Facs->FirmwareWakingVector));
+DEBUG ((DEBUG_INFO, "Transfer to 16bit OS waking vector - %x\r\n",
(UINTN)Facs->FirmwareWakingVector));
AsmTransferControl (Facs->FirmwareWakingVector, 0x0);
}
@@ -630,7 +630,7 @@ RestoreS3PageTables (
//
// The assumption is : whole page table is allocated in CONTINUOUS memory
and CR3 points to TOP page.
//
-DEBUG ((EFI_D_ERROR, "S3NvsPageTableAddress - %x (%x)\n",
(UINTN)S3NvsPageTableAddress, (UINTN)Build4GPageTableOnly));
+DEBUG ((DEBUG_INFO, "S3NvsPageTableAddress - %x (%x)\n",
(UINTN)S3NvsPageTableAddress, (UINTN)Build4GPageTableOnly));
//
// By architecture only one PageMapLevel4 exists - so lets allocate
storage for it.
@@ -783,7 +783,7 @@ S3ResumeExecuteBootScript (
PEI_S3_RESUME_STATE*PeiS3ResumeState;
BOOLEANInterruptStatus;
- DEBUG ((EFI_D_ERROR, "S3ResumeExecuteBootScript()\n"));
+ DEBUG ((DEBUG_INFO, "S3ResumeExecuteBootScript()\n"));
//
// Attempt to use content from SMRAM first
@@ -810,13 +810,13 @@ S3ResumeExecuteBootScript (
(VOID **)
);
if (!EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "Close all SMRAM regions before executing boot
script\n"));
+ DEBUG ((DEBUG_INFO, "Close all SMRAM regions before executing boot
script\n"));
for (Index = 0, Status = EFI_SUCCESS; !EFI_ERROR (Status); Index++) {
Status = SmmAccess->Close ((EFI_PEI_SERVICES
**)GetPeiServicesTablePointer (), SmmAccess, Index);
}
- DEBUG ((EFI_D_ERROR, "Lock all SMRAM regions before executing boot
script\n"));
+ DEBUG ((DEBUG_INFO, "Lock all SMRAM regions before executing boot
script\n"));
for (Index = 0, Status = EFI_SUCCESS; !EFI_ERROR (Status); Index++) {
Status = SmmAccess->Lock ((EFI_PEI_SERVICES
**)GetPeiServicesTablePointer (), SmmAccess, Index);
@@ -881,7 +881,7 @@ S3ResumeExecuteBootScript (
);
ASSERT (FALSE);
}
- DEBUG (( EFI_D_ERROR, "PeiS3ResumeState - %x\r\n", PeiS3Res
[edk2] [PATCH v2 4/5] UefiCpuPkg/PiSmmCpuDxeSmm: Consume new APIs
Consuming PeCoffSerachImageBase() from PeCoffGetEntrypointLib and consuming
DumpCpuContext() from CpuExceptionHandlerLib to replace its own implementation.
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 18 +
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 37 +++---
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 4 +--
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h | 6 +
UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c| 18 +
5 files changed, 18 insertions(+), 65 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
index 119810a..32ce595 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
@@ -1,7 +1,7 @@
/** @file
Page table manipulation functions for IA-32 processors
-Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
This program and the accompanying materials
@@ -88,8 +88,8 @@ SmiDefaultPFHandler (
VOID
EFIAPI
SmiPFHandler (
-IN EFI_EXCEPTION_TYPE InterruptType,
-IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINTN PFAddress;
@@ -108,6 +108,7 @@ SmiPFHandler (
//
if ((PFAddress >= mCpuHotPlugData.SmrrBase) &&
(PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) {
+DumpCpuContext (InterruptType, SystemContext);
CpuIndex = GetCpuIndex ();
GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex *
mSmmStackSize);
if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&
@@ -115,15 +116,6 @@ SmiPFHandler (
(PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) {
DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n"));
} else {
- DEBUG ((DEBUG_ERROR, "SMM exception data - 0x%x(",
SystemContext.SystemContextIa32->ExceptionData));
- DEBUG ((DEBUG_ERROR, "I:%x, R:%x, U:%x, W:%x, P:%x",
-(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0,
-(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_RSVD) !=
0,
-(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_US) != 0,
-(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_WR) != 0,
-(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_P) != 0
-));
- DEBUG ((DEBUG_ERROR, ")\n"));
if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) !=
0) {
DEBUG ((DEBUG_ERROR, "SMM exception at execution (0x%x)\n",
PFAddress));
DEBUG_CODE (
@@ -144,6 +136,7 @@ SmiPFHandler (
//
if ((PFAddress < mCpuHotPlugData.SmrrBase) ||
(PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
+DumpCpuContext (InterruptType, SystemContext);
if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0)
{
DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%x) out of SMM range after
SMM is locked!\n", PFAddress));
DEBUG_CODE (
@@ -166,6 +159,7 @@ SmiPFHandler (
SystemContext.SystemContextIa32->ExceptionData
);
} else {
+DumpCpuContext (InterruptType, SystemContext);
SmiDefaultPFHandler ();
}
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 47cba10..2cb0bbc 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -173,48 +173,17 @@ DumpModuleInfoByIp (
)
{
UINTNPe32Data;
- EFI_IMAGE_DOS_HEADER *DosHdr;
- EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;
VOID *PdbPointer;
- UINT64 DumpIpAddress;
//
// Find Image Base
//
- Pe32Data = CallerIpAddress & ~(SIZE_4KB - 1);
- while (Pe32Data != 0) {
-DosHdr = (EFI_IMAGE_DOS_HEADER *) Pe32Data;
-if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {
- //
- // DOS image header is present, so read the PE header after the DOS
image header.
- //
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Pe32Data + (UINTN)
((DosHdr->e_lfanew) & 0x0));
- //
- // Make sure PE header address does not overflow and is less than the
initial address.
- //
- if (((UINTN)Hdr.Pe32 > Pe32Data) && ((UINTN)Hdr.Pe32 < CallerIpAddress))
{
-if (Hdr.Pe32->Signature == EFI_I
[edk2] [PATCH v2 0/5] Export Dump CPU Context service
This serial of patches are: 1. Export PeCoffSerachImageBase() that could serach PE/COFF image base. 2. Export DumpCpuContext that could dump CPU context when exception happened. https://bugzilla.tianocore.org/show_bug.cgi?id=242 v2: Combine v1's patch 3-6 to v2's patch 3. Combine v1's patch 7, 8 to v2's patch 4. Cc: Jiewen Yao <jiewen@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Cc: Feng Tian <feng.t...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff....@intel.com> Jeff Fan (5): MdePkg/PeCoffGetEntryPointLib: Add PeCoffSerachImageBase() MdeModulePkg/CpuExceptionHandlerLib: Add DumpCpuContext() UefiCpuPkg/CpuExceptionHandlerLib: Add DumpCpuContext() implementation UefiCpuPkg/PiSmmCpuDxeSmm: Consume new APIs SourceLevelDebugPkg/DebugAgent.c: Consume PeCoffSerachImageBase() .../Include/Library/CpuExceptionHandlerLib.h | 15 +++- .../CpuExceptionHandlerLibNull.c | 16 - MdePkg/Include/Library/PeCoffGetEntryPointLib.h| 20 +- .../PeCoffGetEntryPoint.c | 72 ++- .../DebugAgent/DebugAgentCommon/DebugAgent.c | 50 ++--- .../CpuExceptionHandlerLib/CpuExceptionCommon.c| 82 ++ .../CpuExceptionHandlerLib/CpuExceptionCommon.h| 27 --- .../Library/CpuExceptionHandlerLib/DxeException.c | 7 +- .../Ia32/ArchExceptionHandler.c| 65 ++--- .../CpuExceptionHandlerLib/PeiCpuException.c | 6 +- .../CpuExceptionHandlerLib/PeiDxeSmmCpuException.c | 4 +- .../CpuExceptionHandlerLib/SecPeiCpuException.c| 8 +-- .../Library/CpuExceptionHandlerLib/SmmException.c | 7 +- .../X64/ArchExceptionHandler.c | 59 ++-- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 18 ++--- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 37 +- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 4 +- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h | 6 +- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c| 18 ++--- 19 files changed, 268 insertions(+), 253 deletions(-) -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH v2 1/5] MdePkg/PeCoffGetEntryPointLib: Add PeCoffSerachImageBase()
This new API only works on DEBUG build. It will search the PE/COFF image base
forward the input address in this PE/COFF image and returns it.
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Liming Gao <liming@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
MdePkg/Include/Library/PeCoffGetEntryPointLib.h| 20 +-
.../PeCoffGetEntryPoint.c | 72 +-
2 files changed, 90 insertions(+), 2 deletions(-)
diff --git a/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
b/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
index e517ca2..647503b 100644
--- a/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
+++ b/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
@@ -1,7 +1,7 @@
/** @file
Provides a service to retrieve the PE/COFF entry point from a PE/COFF image.
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available
under
the terms and conditions of the BSD License that accompanies this
distribution.
The full text of the license may be found at
@@ -101,4 +101,22 @@ PeCoffGetSizeOfHeaders (
IN VOID *Pe32Data
);
+/**
+ Returns PE/COFF image base specified by the address in this PE/COFF image.
+
+ On DEBUG build, searches the PE/COFF image base forward the address in this
+ PE/COFF image and returns it.
+
+ @param AddressAddress located in one PE/COFF image.
+
+ @retval 0 RELEASE build or cannot find the PE/COFF image base.
+ @retval others PE/COFF image base found.
+
+**/
+UINTN
+EFIAPI
+PeCoffSerachImageBase (
+ IN UINTNAddress
+ );
+
#endif
diff --git a/MdePkg/Library/BasePeCoffGetEntryPointLib/PeCoffGetEntryPoint.c
b/MdePkg/Library/BasePeCoffGetEntryPointLib/PeCoffGetEntryPoint.c
index 0fb7e84..00f6d7d 100644
--- a/MdePkg/Library/BasePeCoffGetEntryPointLib/PeCoffGetEntryPoint.c
+++ b/MdePkg/Library/BasePeCoffGetEntryPointLib/PeCoffGetEntryPoint.c
@@ -2,7 +2,7 @@
Provides the services to get the entry point to a PE/COFF image that has
either been
loaded into memory or is executing at it's linked address.
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
@@ -22,6 +22,8 @@
#include
+#define PE_COFF_IMAGE_ALIGN_SIZE4
+
/**
Retrieves and returns a pointer to the entry point to a PE/COFF image that
has been loaded
into system memory with the PE/COFF Loader Library functions.
@@ -316,3 +318,71 @@ PeCoffGetSizeOfHeaders (
return (UINT32) SizeOfHeaders;
}
+/**
+ Returns PE/COFF image base is loaded in system memory where the input
address is in.
+
+ On DEBUG build, searches the PE/COFF image base forward the input address and
+ returns it.
+
+ @param AddressAddress located in one PE/COFF image.
+
+ @retval 0 RELEASE build or cannot find the PE/COFF image base.
+ @retval others PE/COFF image base found.
+
+**/
+UINTN
+EFIAPI
+PeCoffSerachImageBase (
+ IN UINTNAddress
+ )
+{
+ UINTNPe32Data;
+
+ Pe32Data = 0;
+
+ DEBUG_CODE (
+EFI_IMAGE_DOS_HEADER *DosHdr;
+EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;
+
+//
+// Find Image Base
+//
+Pe32Data = Address & ~(PE_COFF_IMAGE_ALIGN_SIZE - 1);
+while (Pe32Data != 0) {
+ DosHdr = (EFI_IMAGE_DOS_HEADER *) Pe32Data;
+ if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {
+//
+// DOS image header is present, so read the PE header after the DOS
image header.
+//
+Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Pe32Data + (UINTN)
((DosHdr->e_lfanew) & 0x0));
+//
+// Make sure PE header address does not overflow and is less than the
initial address.
+//
+if (((UINTN)Hdr.Pe32 > Pe32Data) && ((UINTN)Hdr.Pe32 < Address)) {
+ if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {
+break;
+ }
+}
+ } else {
+//
+// DOS image header is not present, TE header is at the image base.
+//
+Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)Pe32Data;
+if ((Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) &&
+((Hdr.Te->Machine == IMAGE_FILE_MACHINE_I386) || (Hdr.Te->Machine
== IMAGE_FILE_MACHINE_IA64) ||
+ (Hdr.Te->Machine == IMAGE_FILE_MACHINE_EBC) || (Hdr.Te->Machine
== IMAGE_FILE_MACHINE_X64) ||
+ (Hdr.Te->Machine == IM
[edk2] [PATCH v2 2/5] MdeModulePkg/CpuExceptionHandlerLib: Add DumpCpuContext()
This API is used to display exception type and all processor context for debug
purpose.
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h| 15 ++-
.../CpuExceptionHandlerLibNull.c | 16 +++-
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
index b3016ee..6cd8230 100644
--- a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
+++ b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
@@ -2,7 +2,7 @@
CPU Exception library provides the default CPU interrupt/exception handler.
It also provides capability to register user interrupt/exception handler.
- Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -93,4 +93,17 @@ RegisterCpuInterruptHandler (
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
);
+/**
+ Display processor context.
+
+ @param[in] ExceptionType Exception type.
+ @param[in] SystemContext Processor context to be display.
+**/
+VOID
+EFIAPI
+DumpCpuContext (
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ );
+
#endif
diff --git
a/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.c
b/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.c
index 68ee9a9..cbe4768 100644
---
a/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.c
+++
b/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.c
@@ -1,7 +1,7 @@
/** @file
CPU Exception Handler library implementition with empty functions.
- Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -97,3 +97,17 @@ RegisterCpuInterruptHandler (
return EFI_UNSUPPORTED;
}
+/**
+ Display processor context.
+
+ @param[in] ExceptionType Exception type.
+ @param[in] SystemContext Processor context to be display.
+**/
+VOID
+EFIAPI
+DumpCpuContext (
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+}
--
2.9.3.windows.2
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[edk2] [PATCH v2 5/5] SourceLevelDebugPkg/DebugAgent.c: Consume PeCoffSerachImageBase()
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../DebugAgent/DebugAgentCommon/DebugAgent.c | 50 +++---
1 file changed, 6 insertions(+), 44 deletions(-)
diff --git
a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.c
b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.c
index edd0de1..6f3c419 100644
--- a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.c
+++ b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.c
@@ -4,7 +4,7 @@
read/write debug packet to communication with HOST based on transfer
protocol.
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -201,55 +201,17 @@ FindAndReportModuleImageInfo (
)
{
UINTNPe32Data;
- EFI_IMAGE_DOS_HEADER *DosHdr;
- EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;
PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;
//
// Find Image Base
//
- Pe32Data = ((UINTN)mErrorMsgVersionAlert) & ~(AlignSize - 1);
- while (Pe32Data != 0) {
-DosHdr = (EFI_IMAGE_DOS_HEADER *) Pe32Data;
-if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {
- //
- // DOS image header is present, so read the PE header after the DOS
image header.
- //
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Pe32Data + (UINTN)
((DosHdr->e_lfanew) & 0x0));
- //
- // Make sure PE header address does not overflow and is less than the
initial address.
- //
- if (((UINTN)Hdr.Pe32 > Pe32Data) && ((UINTN)Hdr.Pe32 <
(UINTN)mErrorMsgVersionAlert)) {
-if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {
- //
- // It's PE image.
- //
- break;
-}
- }
-} else {
- //
- // DOS image header is not present, TE header is at the image base.
- //
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)Pe32Data;
- if ((Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) &&
- ((Hdr.Te->Machine == IMAGE_FILE_MACHINE_I386) || Hdr.Te->Machine ==
IMAGE_FILE_MACHINE_X64)) {
-//
-// It's TE image, it TE header and Machine type match
-//
-break;
- }
-}
-
-//
-// Not found the image base, check the previous aligned address
-//
-Pe32Data -= AlignSize;
+ Pe32Data = PeCoffSerachImageBase ((UINTN) mErrorMsgVersionAlert);
+ if (Pe32Data != 0) {
+ImageContext.ImageAddress = Pe32Data;
+ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN)
ImageContext.ImageAddress);
+PeCoffLoaderRelocateImageExtraAction ();
}
-
- ImageContext.ImageAddress = Pe32Data;
- ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN)
ImageContext.ImageAddress);
- PeCoffLoaderRelocateImageExtraAction ();
}
/**
--
2.9.3.windows.2
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[edk2] [PATCH v2 3/5] UefiCpuPkg/CpuExceptionHandlerLib: Add DumpCpuContext() implementation
Export DumpCpuCotext() to display CPU Context. We will invoke
PeCoffGetEntrypointLib's PeCoffSerachImageBase() to get PE/COFF image base.
Display exception data bit value for page fault exception.
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../CpuExceptionHandlerLib/CpuExceptionCommon.c| 82 ++
.../CpuExceptionHandlerLib/CpuExceptionCommon.h| 27 ---
.../Library/CpuExceptionHandlerLib/DxeException.c | 7 +-
.../Ia32/ArchExceptionHandler.c| 65 ++---
.../CpuExceptionHandlerLib/PeiCpuException.c | 6 +-
.../CpuExceptionHandlerLib/PeiDxeSmmCpuException.c | 4 +-
.../CpuExceptionHandlerLib/SecPeiCpuException.c| 8 +--
.../Library/CpuExceptionHandlerLib/SmmException.c | 7 +-
.../X64/ArchExceptionHandler.c | 59 ++--
9 files changed, 125 insertions(+), 140 deletions(-)
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
index 3d85b0c..0537208 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
@@ -106,82 +106,44 @@ InternalPrintMessage (
/**
Find and display image base address and return image base and its entry
point.
-
+
@param CurrentEip Current instruction pointer.
- @param EntryPoint Return module entry point if module header is found.
-
- @return !0 Image base address.
- @return 0 Image header cannot be found.
+
**/
-UINTN
-FindModuleImageBase (
- IN UINTN CurrentEip,
- OUT UINTN *EntryPoint
+VOID
+DumpModuleImageInfo (
+ IN UINTN CurrentEip
)
{
+ EFI_STATUS Status;
UINTNPe32Data;
- EFI_IMAGE_DOS_HEADER *DosHdr;
- EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;
VOID *PdbPointer;
+ VOID *EntryPoint;
- //
- // Find Image Base
- //
- Pe32Data = CurrentEip & ~(mImageAlignSize - 1);
- while (Pe32Data != 0) {
-DosHdr = (EFI_IMAGE_DOS_HEADER *) Pe32Data;
-if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {
- //
- // DOS image header is present, so read the PE header after the DOS
image header.
- //
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Pe32Data + (UINTN)
((DosHdr->e_lfanew) & 0x0));
- //
- // Make sure PE header address does not overflow and is less than the
initial address.
- //
- if (((UINTN)Hdr.Pe32 > Pe32Data) && ((UINTN)Hdr.Pe32 < CurrentEip)) {
-if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {
- //
- // It's PE image.
- //
- InternalPrintMessage (" Find PE image ");
- *EntryPoint = (UINTN)Pe32Data +
(UINTN)(Hdr.Pe32->OptionalHeader.AddressOfEntryPoint & 0x0);
- break;
-}
- }
-} else {
- //
- // DOS image header is not present, TE header is at the image base.
- //
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)Pe32Data;
- if ((Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) &&
- ((Hdr.Te->Machine == IMAGE_FILE_MACHINE_I386) || Hdr.Te->Machine ==
IMAGE_FILE_MACHINE_X64)) {
-//
-// It's TE image, it TE header and Machine type match
-//
-InternalPrintMessage (" Find TE image ");
-*EntryPoint = (UINTN)Pe32Data + (UINTN)(Hdr.Te->AddressOfEntryPoint &
0x0) + sizeof(EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize;
-break;
- }
-}
-
+ Pe32Data = PeCoffSerachImageBase (CurrentEip);
+ if (Pe32Data == 0) {
+InternalPrintMessage (" Can't find image information. \n");
+ } else {
//
-// Not found the image base, check the previous aligned address
+// Find Image Base entry point
//
-Pe32Data -= mImageAlignSize;
- }
-
- if (Pe32Data != 0) {
+Status = PeCoffLoaderGetEntryPoint ((VOID *) Pe32Data, );
+if (EFI_ERROR (Status)) {
+ EntryPoint = NULL;
+}
+InternalPrintMessage (" Find image ");
PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);
if (PdbPointer != NULL) {
InternalPrintMessage ("%a", PdbPointer);
} else {
InternalPrintMessage ("(No PDB) " );
}
- } else {
-InternalPrintMessage (" Can't find image information. \n");
+InternalPrintMessage (
+ " (ImageBase=%016lp, EntryPoint=%016p) \n",
+ (VOID *) Pe32Data,
+ EntryPoint
+ );
}
-
- return Pe32Data;
}
[edk2] [PATCH] UefiCpuPkg/CpuFeatures: Change CPU features name to follow IA32 SDM
Cc: Feng Tian <feng.t...@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff@intel.com> --- UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h index 4765bc3..4aa3529 100644 --- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h @@ -45,8 +45,8 @@ #define CPU_FEATURE_C1E 16 #define CPU_FEATURE_C1_AUTO_DEMOTION17 #define CPU_FEATURE_C3_AUTO_DEMOTION18 -#define CPU_FEATURE_C1_AUTO_UNDEMOTION 19 -#define CPU_FEATURE_C3_AUTO_UNDEMOTION 20 +#define CPU_FEATURE_C1_UNDEMOTION 19 +#define CPU_FEATURE_C3_UNDEMOTION 20 #define CPU_FEATURE_C_STATE 21 #define CPU_FEATURE_TM 22 #define CPU_FEATURE_TM2 23 -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH] UefiCpuPkg/MpLib.c: Load microcode before mtrr sync per IA32 SDM
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=453 Cc: Jiewen Yao <jiewen@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Cc: Feng Tian <feng.t...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff@intel.com> --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index bb93526..03d6c2d 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -382,13 +382,13 @@ ApInitializeSync ( CpuMpData = (CPU_MP_DATA *) Buffer; // - // Sync BSP's MTRR table to AP - // - MtrrSetAllMtrrs (>MtrrTable); - // // Load microcode on AP // MicrocodeDetect (CpuMpData); + // + // Sync BSP's MTRR table to AP + // + MtrrSetAllMtrrs (>MtrrTable); } /** -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 6/9] UefiCpuPkg/CpuExceptionHandlerLib: Display PF Excption Data bit
Page-fault exception data bit displaying is very useful.
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../CpuExceptionHandlerLib/CpuExceptionCommon.h| 11 +
.../Ia32/ArchExceptionHandler.c| 26 --
.../X64/ArchExceptionHandler.c | 26 --
3 files changed, 49 insertions(+), 14 deletions(-)
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
index 5b3a9b9..e66a5df 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
@@ -30,6 +30,17 @@
#define CPU_INTERRUPT_NUM 256
#define HOOKAFTER_STUB_SIZE16
+//
+// Exception Error Code of Page-Fault Exception
+//
+#define IA32_PF_EC_PBIT0
+#define IA32_PF_EC_WR BIT1
+#define IA32_PF_EC_US BIT2
+#define IA32_PF_EC_RSVD BIT3
+#define IA32_PF_EC_ID BIT4
+#define IA32_PF_EC_PK BIT5
+#define IA32_PF_EC_SGX BIT15
+
#include "ArchInterruptDefs.h"
#define CPU_EXCEPTION_HANDLER_LIB_HOB_GUID \
diff --git
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
index 59ed058..013e19b 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
@@ -126,19 +126,31 @@ DumpCpuContext (
GetExceptionNameStr (ExceptionType),
GetApicId ()
);
-
+ if ((mErrorCodeFlag & (1 << ExceptionType)) != 0) {
+InternalPrintMessage (
+ "ExceptionData - %08x",
+ SystemContext.SystemContextIa32->ExceptionData
+ );
+if (ExceptionType == EXCEPT_IA32_PAGE_FAULT) {
+ InternalPrintMessage (
+" I:%x R:%x U:%x W:%x P:%x PK:%x S:%x",
+(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) !=
0,
+(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_RSVD) !=
0,
+(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_US) !=
0,
+(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_WR) !=
0,
+(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_P)!=
0,
+(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_PK) !=
0,
+(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SGX) != 0
+);
+}
+InternalPrintMessage ("\n");
+ }
InternalPrintMessage (
"EIP - %08x, CS - %08x, EFLAGS - %08x\n",
SystemContext.SystemContextIa32->Eip,
SystemContext.SystemContextIa32->Cs,
SystemContext.SystemContextIa32->Eflags
);
- if ((mErrorCodeFlag & (1 << ExceptionType)) != 0) {
-InternalPrintMessage (
- "ExceptionData - %08x\n",
- SystemContext.SystemContextIa32->ExceptionData
- );
- }
InternalPrintMessage (
"EAX - %08x, ECX - %08x, EDX - %08x, EBX - %08x\n",
SystemContext.SystemContextIa32->Eax,
diff --git
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
index 5199559..98a776f 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
@@ -131,19 +131,31 @@ DumpCpuContext (
GetExceptionNameStr (ExceptionType),
GetApicId ()
);
-
+ if ((mErrorCodeFlag & (1 << ExceptionType)) != 0) {
+InternalPrintMessage (
+ "ExceptionData - %016lx",
+ SystemContext.SystemContextX64->ExceptionData
+ );
+if (ExceptionType == EXCEPT_IA32_PAGE_FAULT) {
+ InternalPrintMessage (
+" I:%x R:%x U:%x W:%x P:%x PK:%x S:%x",
+(SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0,
+(SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_RSVD) != 0,
+(SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_US) != 0,
+(SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_WR) != 0,
+(SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_P)!= 0,
+(SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_PK) != 0,
+(SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_SGX) != 0
+);
+}
+InternalPrintMessage ("\n");
+ }
InternalPrint
[edk2] [PATCH 8/9] UefiCpuPkg/PiSmmCpuDxeSmm: Consume DumpCpuContext()
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 18 ++
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 4 ++--
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h | 6 +-
UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c| 18 ++
4 files changed, 15 insertions(+), 31 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
index 119810a..32ce595 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
@@ -1,7 +1,7 @@
/** @file
Page table manipulation functions for IA-32 processors
-Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
This program and the accompanying materials
@@ -88,8 +88,8 @@ SmiDefaultPFHandler (
VOID
EFIAPI
SmiPFHandler (
-IN EFI_EXCEPTION_TYPE InterruptType,
-IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINTN PFAddress;
@@ -108,6 +108,7 @@ SmiPFHandler (
//
if ((PFAddress >= mCpuHotPlugData.SmrrBase) &&
(PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) {
+DumpCpuContext (InterruptType, SystemContext);
CpuIndex = GetCpuIndex ();
GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex *
mSmmStackSize);
if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&
@@ -115,15 +116,6 @@ SmiPFHandler (
(PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) {
DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n"));
} else {
- DEBUG ((DEBUG_ERROR, "SMM exception data - 0x%x(",
SystemContext.SystemContextIa32->ExceptionData));
- DEBUG ((DEBUG_ERROR, "I:%x, R:%x, U:%x, W:%x, P:%x",
-(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0,
-(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_RSVD) !=
0,
-(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_US) != 0,
-(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_WR) != 0,
-(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_P) != 0
-));
- DEBUG ((DEBUG_ERROR, ")\n"));
if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) !=
0) {
DEBUG ((DEBUG_ERROR, "SMM exception at execution (0x%x)\n",
PFAddress));
DEBUG_CODE (
@@ -144,6 +136,7 @@ SmiPFHandler (
//
if ((PFAddress < mCpuHotPlugData.SmrrBase) ||
(PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
+DumpCpuContext (InterruptType, SystemContext);
if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0)
{
DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%x) out of SMM range after
SMM is locked!\n", PFAddress));
DEBUG_CODE (
@@ -166,6 +159,7 @@ SmiPFHandler (
SystemContext.SystemContextIa32->ExceptionData
);
} else {
+DumpCpuContext (InterruptType, SystemContext);
SmiDefaultPFHandler ();
}
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index 71af2f1..92b0fe6 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -690,8 +690,8 @@ SmmRelocateBases (
VOID
EFIAPI
SmiPFHandler (
-IN EFI_EXCEPTION_TYPE InterruptType,
-IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
);
/**
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
index 5aaf945..a216891 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
@@ -1,7 +1,7 @@
/** @file
SMM profile internal header file.
-Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -41,10 +41,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
EXPRESS OR IMPLIED.
// Please disable it.
//
-#define IA32_PF_EC_P(1u << 0)
-#define IA32_PF_EC_WR (1u << 1)
-#define IA32_PF_EC_US (1u << 2)
-#define IA32_PF_E
[edk2] [PATCH 2/9] MdeModulePkg/CpuExceptionHandlerLib: Add DumpCpuContext()
This API is used to display exception type and all processor context for debug
purpose.
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h| 15 ++-
.../CpuExceptionHandlerLibNull.c | 16 +++-
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
index b3016ee..6cd8230 100644
--- a/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
+++ b/MdeModulePkg/Include/Library/CpuExceptionHandlerLib.h
@@ -2,7 +2,7 @@
CPU Exception library provides the default CPU interrupt/exception handler.
It also provides capability to register user interrupt/exception handler.
- Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -93,4 +93,17 @@ RegisterCpuInterruptHandler (
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
);
+/**
+ Display processor context.
+
+ @param[in] ExceptionType Exception type.
+ @param[in] SystemContext Processor context to be display.
+**/
+VOID
+EFIAPI
+DumpCpuContext (
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ );
+
#endif
diff --git
a/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.c
b/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.c
index 68ee9a9..cbe4768 100644
---
a/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.c
+++
b/MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.c
@@ -1,7 +1,7 @@
/** @file
CPU Exception Handler library implementition with empty functions.
- Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -97,3 +97,17 @@ RegisterCpuInterruptHandler (
return EFI_UNSUPPORTED;
}
+/**
+ Display processor context.
+
+ @param[in] ExceptionType Exception type.
+ @param[in] SystemContext Processor context to be display.
+**/
+VOID
+EFIAPI
+DumpCpuContext (
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+}
--
2.9.3.windows.2
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[edk2] [PATCH 4/9] UefiCpuPkg/CpuExceptionHandlerLib: Add DumpModuleImageInfo()
Add internal DumpModuleImageInfo() to replace FindModuleImageBase(). It will
consume PeCoffGetEntrypointLib's PeCoffSerachImageBase() to get PE/COFF image
base.
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../CpuExceptionHandlerLib/CpuExceptionCommon.c| 75 ++
.../CpuExceptionHandlerLib/CpuExceptionCommon.h| 11 +---
.../Library/CpuExceptionHandlerLib/DxeException.c | 7 +-
.../Ia32/ArchExceptionHandler.c| 15 +
.../CpuExceptionHandlerLib/PeiCpuException.c | 6 +-
.../CpuExceptionHandlerLib/SecPeiCpuException.c| 4 --
.../Library/CpuExceptionHandlerLib/SmmException.c | 7 +-
.../X64/ArchExceptionHandler.c | 12 +---
8 files changed, 30 insertions(+), 107 deletions(-)
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
index 3d85b0c..6080d1e 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
@@ -113,75 +113,40 @@ InternalPrintMessage (
@return !0 Image base address.
@return 0 Image header cannot be found.
**/
-UINTN
-FindModuleImageBase (
- IN UINTN CurrentEip,
- OUT UINTN *EntryPoint
+VOID
+DumpModuleImageInfo (
+ IN UINTN CurrentEip
)
{
+ EFI_STATUS Status;
UINTNPe32Data;
- EFI_IMAGE_DOS_HEADER *DosHdr;
- EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;
VOID *PdbPointer;
+ VOID *EntryPoint;
- //
- // Find Image Base
- //
- Pe32Data = CurrentEip & ~(mImageAlignSize - 1);
- while (Pe32Data != 0) {
-DosHdr = (EFI_IMAGE_DOS_HEADER *) Pe32Data;
-if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {
- //
- // DOS image header is present, so read the PE header after the DOS
image header.
- //
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Pe32Data + (UINTN)
((DosHdr->e_lfanew) & 0x0));
- //
- // Make sure PE header address does not overflow and is less than the
initial address.
- //
- if (((UINTN)Hdr.Pe32 > Pe32Data) && ((UINTN)Hdr.Pe32 < CurrentEip)) {
-if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {
- //
- // It's PE image.
- //
- InternalPrintMessage (" Find PE image ");
- *EntryPoint = (UINTN)Pe32Data +
(UINTN)(Hdr.Pe32->OptionalHeader.AddressOfEntryPoint & 0x0);
- break;
-}
- }
-} else {
- //
- // DOS image header is not present, TE header is at the image base.
- //
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)Pe32Data;
- if ((Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) &&
- ((Hdr.Te->Machine == IMAGE_FILE_MACHINE_I386) || Hdr.Te->Machine ==
IMAGE_FILE_MACHINE_X64)) {
-//
-// It's TE image, it TE header and Machine type match
-//
-InternalPrintMessage (" Find TE image ");
-*EntryPoint = (UINTN)Pe32Data + (UINTN)(Hdr.Te->AddressOfEntryPoint &
0x0) + sizeof(EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize;
-break;
- }
-}
-
+ Pe32Data = PeCoffSerachImageBase (CurrentEip);
+ if (Pe32Data == 0) {
+InternalPrintMessage (" Can't find image information. \n");
+ } else {
//
-// Not found the image base, check the previous aligned address
+// Find Image Base entry point
//
-Pe32Data -= mImageAlignSize;
- }
-
- if (Pe32Data != 0) {
+Status = PeCoffLoaderGetEntryPoint ((VOID *) Pe32Data, );
+if (EFI_ERROR (Status)) {
+ EntryPoint = NULL;
+}
+InternalPrintMessage (" Find image ");
PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);
if (PdbPointer != NULL) {
InternalPrintMessage ("%a", PdbPointer);
} else {
InternalPrintMessage ("(No PDB) " );
}
- } else {
-InternalPrintMessage (" Can't find image information. \n");
+InternalPrintMessage (
+ " (ImageBase=%016lp, EntryPoint=%016p) \n",
+ (VOID *) Pe32Data,
+ EntryPoint
+ );
}
-
- return Pe32Data;
}
/**
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
index 9adb6a1..0047ad6 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
@@ -53,7 +53,6 @@ typedef struct {
} EXCEPTION_HAND
[edk2] [PATCH 5/9] UefiCpuPkg/CpuExceptionHandlerLib: Add DumpCpuContext() implementation
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../CpuExceptionHandlerLib/CpuExceptionCommon.h| 1 +
.../Ia32/ArchExceptionHandler.c| 24 +-
.../X64/ArchExceptionHandler.c | 17 ++-
3 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
index 0047ad6..5b3a9b9 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
@@ -24,6 +24,7 @@
#include
#include
#include
+#include
#define CPU_EXCEPTION_NUM 32
#define CPU_INTERRUPT_NUM 256
diff --git
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
index d3b26d3..59ed058 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
@@ -108,13 +108,14 @@ ArchRestoreExceptionContext (
}
/**
- Display CPU information.
+ Display processor context.
- @param ExceptionType Exception type.
- @param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
+ @param[in] ExceptionType Exception type.
+ @param[in] SystemContext Processor context to be display.
**/
VOID
-DumpImageAndCpuContent (
+EFIAPI
+DumpCpuContext (
IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
@@ -195,10 +196,23 @@ DumpImageAndCpuContent (
"FXSAVE_STATE - %08x\n",
>FxSaveState
);
+}
+/**
+ Display CPU information.
+
+ @param ExceptionType Exception type.
+ @param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
+**/
+VOID
+DumpImageAndCpuContent (
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ DumpCpuContext (ExceptionType, SystemContext);
//
// Find module image base and module entry point by EIP
//
DumpModuleImageInfo (SystemContext.SystemContextIa32->Eip);
-
}
diff --git
a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
index 9cd2cc2..5199559 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
@@ -119,7 +119,8 @@ ArchRestoreExceptionContext (
@param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
**/
VOID
-DumpImageAndCpuContent (
+EFIAPI
+DumpCpuContext (
IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
@@ -227,7 +228,21 @@ DumpImageAndCpuContent (
"FXSAVE_STATE - %016lx\n",
>FxSaveState
);
+}
+/**
+ Display CPU information.
+
+ @param ExceptionType Exception type.
+ @param SystemContext Pointer to EFI_SYSTEM_CONTEXT.
+**/
+VOID
+DumpImageAndCpuContent (
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ DumpCpuContext (ExceptionType, SystemContext);
//
// Find module image base and module entry point by RIP
//
--
2.9.3.windows.2
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[edk2] [PATCH 9/9] SourceLevelDebugPkg/DebugAgent.c: Consume PeCoffSerachImageBase()
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../DebugAgent/DebugAgentCommon/DebugAgent.c | 50 +++---
1 file changed, 6 insertions(+), 44 deletions(-)
diff --git
a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.c
b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.c
index edd0de1..6f3c419 100644
--- a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.c
+++ b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.c
@@ -4,7 +4,7 @@
read/write debug packet to communication with HOST based on transfer
protocol.
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -201,55 +201,17 @@ FindAndReportModuleImageInfo (
)
{
UINTNPe32Data;
- EFI_IMAGE_DOS_HEADER *DosHdr;
- EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;
PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;
//
// Find Image Base
//
- Pe32Data = ((UINTN)mErrorMsgVersionAlert) & ~(AlignSize - 1);
- while (Pe32Data != 0) {
-DosHdr = (EFI_IMAGE_DOS_HEADER *) Pe32Data;
-if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {
- //
- // DOS image header is present, so read the PE header after the DOS
image header.
- //
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Pe32Data + (UINTN)
((DosHdr->e_lfanew) & 0x0));
- //
- // Make sure PE header address does not overflow and is less than the
initial address.
- //
- if (((UINTN)Hdr.Pe32 > Pe32Data) && ((UINTN)Hdr.Pe32 <
(UINTN)mErrorMsgVersionAlert)) {
-if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {
- //
- // It's PE image.
- //
- break;
-}
- }
-} else {
- //
- // DOS image header is not present, TE header is at the image base.
- //
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)Pe32Data;
- if ((Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) &&
- ((Hdr.Te->Machine == IMAGE_FILE_MACHINE_I386) || Hdr.Te->Machine ==
IMAGE_FILE_MACHINE_X64)) {
-//
-// It's TE image, it TE header and Machine type match
-//
-break;
- }
-}
-
-//
-// Not found the image base, check the previous aligned address
-//
-Pe32Data -= AlignSize;
+ Pe32Data = PeCoffSerachImageBase ((UINTN) mErrorMsgVersionAlert);
+ if (Pe32Data != 0) {
+ImageContext.ImageAddress = Pe32Data;
+ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN)
ImageContext.ImageAddress);
+PeCoffLoaderRelocateImageExtraAction ();
}
-
- ImageContext.ImageAddress = Pe32Data;
- ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN)
ImageContext.ImageAddress);
- PeCoffLoaderRelocateImageExtraAction ();
}
/**
--
2.9.3.windows.2
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[edk2] [PATCH 7/9] UefiCpuPkg/PiSmmCpuDxeSmm: Consume PeCoffSerachImageBase()
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 37 +++---
1 file changed, 3 insertions(+), 34 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index d061482..7b23986 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -167,48 +167,17 @@ DumpModuleInfoByIp (
)
{
UINTNPe32Data;
- EFI_IMAGE_DOS_HEADER *DosHdr;
- EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;
VOID *PdbPointer;
- UINT64 DumpIpAddress;
//
// Find Image Base
//
- Pe32Data = CallerIpAddress & ~(SIZE_4KB - 1);
- while (Pe32Data != 0) {
-DosHdr = (EFI_IMAGE_DOS_HEADER *) Pe32Data;
-if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {
- //
- // DOS image header is present, so read the PE header after the DOS
image header.
- //
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Pe32Data + (UINTN)
((DosHdr->e_lfanew) & 0x0));
- //
- // Make sure PE header address does not overflow and is less than the
initial address.
- //
- if (((UINTN)Hdr.Pe32 > Pe32Data) && ((UINTN)Hdr.Pe32 < CallerIpAddress))
{
-if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {
- //
- // It's PE image.
- //
- break;
-}
- }
-}
-
-//
-// Not found the image base, check the previous aligned address
-//
-Pe32Data -= SIZE_4KB;
- }
-
- DumpIpAddress = CallerIpAddress;
- DEBUG ((EFI_D_ERROR, "It is invoked from the instruction before IP(0x%lx)",
DumpIpAddress));
-
+ Pe32Data = PeCoffSerachImageBase (CallerIpAddress);
if (Pe32Data != 0) {
+DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)",
(VOID *) CallerIpAddress));
PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);
if (PdbPointer != NULL) {
- DEBUG ((EFI_D_ERROR, " in module (%a)", PdbPointer));
+ DEBUG ((DEBUG_ERROR, " in module (%a)\n", PdbPointer));
}
}
}
--
2.9.3.windows.2
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[edk2] [PATCH 3/9] UefiCpuPkg/CpuExceptionHandlerLib: Rename internal DumpCpuContent()
Rename internal DumpCpuContent() to DumpImageAndCpuContent(). Cc: Jiewen Yao <jiewen@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Cc: Feng Tian <feng.t...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff@intel.com> --- UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h| 4 ++-- UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c | 4 ++-- UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c | 4 ++-- UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c| 4 ++-- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h index 4639ed2..9adb6a1 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h @@ -1,7 +1,7 @@ /** @file Common header file for CPU Exception Handler Library. - Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved. + Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -130,7 +130,7 @@ FindModuleImageBase ( @param SystemContext Pointer to EFI_SYSTEM_CONTEXT. **/ VOID -DumpCpuContent ( +DumpImageAndCpuContent ( IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext ); diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c index 7ab2438..aaf90f6 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c @@ -1,7 +1,7 @@ /** @file IA32 CPU Exception Handler functons. - Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved. + Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -114,7 +114,7 @@ ArchRestoreExceptionContext ( @param SystemContext Pointer to EFI_SYSTEM_CONTEXT. **/ VOID -DumpCpuContent ( +DumpImageAndCpuContent ( IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext ) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c index c0fc9a6..fb679b5 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c @@ -1,7 +1,7 @@ /** @file CPU Exception Library provides PEI/DXE/SMM CPU common exception handler. -Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved. +Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at @@ -101,7 +101,7 @@ CommonExceptionHandlerWorker ( // // Display ExceptionType, CPU information and Image information // -DumpCpuContent (ExceptionType, SystemContext); +DumpImageAndCpuContent (ExceptionType, SystemContext); // // Release Spinlock of output message // diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c index 7e94e38..7ac3fc2 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c @@ -1,7 +1,7 @@ /** @file CPU exception handler library implemenation for SEC/PEIM modules. -Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved. +Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at @@ -37,7 +37,7 @@ CommonExceptionHandler ( // // Display ExceptionType, CPU information and Image information // - DumpCpuContent (ExceptionType, SystemContext); + DumpImageAndCpuContent (ExceptionType, SystemContext); // // Enter a dead loop. diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c b/UefiCpuPkg/Library/Cp
[edk2] [PATCH 1/9] MdePkg/PeCoffGetEntryPointLib: Add PeCoffSerachImageBase()
This new API only works on DEBUG build. It will search the PE/COFF image base
forward the input address in this PE/COFF image and returns it.
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Liming Gao <liming@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
MdePkg/Include/Library/PeCoffGetEntryPointLib.h| 20 +-
.../PeCoffGetEntryPoint.c | 72 +-
2 files changed, 90 insertions(+), 2 deletions(-)
diff --git a/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
b/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
index e517ca2..647503b 100644
--- a/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
+++ b/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
@@ -1,7 +1,7 @@
/** @file
Provides a service to retrieve the PE/COFF entry point from a PE/COFF image.
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available
under
the terms and conditions of the BSD License that accompanies this
distribution.
The full text of the license may be found at
@@ -101,4 +101,22 @@ PeCoffGetSizeOfHeaders (
IN VOID *Pe32Data
);
+/**
+ Returns PE/COFF image base specified by the address in this PE/COFF image.
+
+ On DEBUG build, searches the PE/COFF image base forward the address in this
+ PE/COFF image and returns it.
+
+ @param AddressAddress located in one PE/COFF image.
+
+ @retval 0 RELEASE build or cannot find the PE/COFF image base.
+ @retval others PE/COFF image base found.
+
+**/
+UINTN
+EFIAPI
+PeCoffSerachImageBase (
+ IN UINTNAddress
+ );
+
#endif
diff --git a/MdePkg/Library/BasePeCoffGetEntryPointLib/PeCoffGetEntryPoint.c
b/MdePkg/Library/BasePeCoffGetEntryPointLib/PeCoffGetEntryPoint.c
index 0fb7e84..00f6d7d 100644
--- a/MdePkg/Library/BasePeCoffGetEntryPointLib/PeCoffGetEntryPoint.c
+++ b/MdePkg/Library/BasePeCoffGetEntryPointLib/PeCoffGetEntryPoint.c
@@ -2,7 +2,7 @@
Provides the services to get the entry point to a PE/COFF image that has
either been
loaded into memory or is executing at it's linked address.
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
@@ -22,6 +22,8 @@
#include
+#define PE_COFF_IMAGE_ALIGN_SIZE4
+
/**
Retrieves and returns a pointer to the entry point to a PE/COFF image that
has been loaded
into system memory with the PE/COFF Loader Library functions.
@@ -316,3 +318,71 @@ PeCoffGetSizeOfHeaders (
return (UINT32) SizeOfHeaders;
}
+/**
+ Returns PE/COFF image base is loaded in system memory where the input
address is in.
+
+ On DEBUG build, searches the PE/COFF image base forward the input address and
+ returns it.
+
+ @param AddressAddress located in one PE/COFF image.
+
+ @retval 0 RELEASE build or cannot find the PE/COFF image base.
+ @retval others PE/COFF image base found.
+
+**/
+UINTN
+EFIAPI
+PeCoffSerachImageBase (
+ IN UINTNAddress
+ )
+{
+ UINTNPe32Data;
+
+ Pe32Data = 0;
+
+ DEBUG_CODE (
+EFI_IMAGE_DOS_HEADER *DosHdr;
+EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;
+
+//
+// Find Image Base
+//
+Pe32Data = Address & ~(PE_COFF_IMAGE_ALIGN_SIZE - 1);
+while (Pe32Data != 0) {
+ DosHdr = (EFI_IMAGE_DOS_HEADER *) Pe32Data;
+ if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {
+//
+// DOS image header is present, so read the PE header after the DOS
image header.
+//
+Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Pe32Data + (UINTN)
((DosHdr->e_lfanew) & 0x0));
+//
+// Make sure PE header address does not overflow and is less than the
initial address.
+//
+if (((UINTN)Hdr.Pe32 > Pe32Data) && ((UINTN)Hdr.Pe32 < Address)) {
+ if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {
+break;
+ }
+}
+ } else {
+//
+// DOS image header is not present, TE header is at the image base.
+//
+Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)Pe32Data;
+if ((Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) &&
+((Hdr.Te->Machine == IMAGE_FILE_MACHINE_I386) || (Hdr.Te->Machine
== IMAGE_FILE_MACHINE_IA64) ||
+ (Hdr.Te->Machine == IMAGE_FILE_MACHINE_EBC) || (Hdr.Te->Machine
== IMAGE_FILE_MACHINE_X64) ||
+ (Hdr.Te->Machine == IM
[edk2] [PATCH v2 0/3] UefiCpuPkg/PiSmmCpuDxeSmm: Check all SMM ranges found
NX/SmmProfile feature required to protect all SMM ranges. This update is to check additonal saved SMM ranges besides the range specified by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz. v2: #1: Add #define SMRR_MAX_ADDRESS to clarify SMRR requirement. Cc: Jiewen Yao <jiewen@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Cc: Feng Tian <feng.t...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff....@intel.com> Jeff Fan (3): UefiCpuPkg/PiSmmCpuDxeSmm: Save SMM ranges info into global variables UefiCpuPkg/PiSmmCpuDxeSmm: Add IsInSmmRanges() to check SMM range UefiCpuPkg/PiSmmCpuDxeSmm: Update saved SMM ranges check in SmmProfile UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 44 + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 6 ++- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 78 +- 3 files changed, 96 insertions(+), 32 deletions(-) -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH v2 3/3] UefiCpuPkg/PiSmmCpuDxeSmm: Update saved SMM ranges check in SmmProfile
SmmProfile feature required to protect all SMM ranges by structure
mProtectionMemRangeTemplate. This update is to add additonal save SMM ranges
into mProtectionMemRangeTemplate besides the range specified by
mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz.
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 42 +-
1 file changed, 36 insertions(+), 6 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index 7125aec..2713b19 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -83,6 +83,12 @@ MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[] = {
{{0x, 0x},TRUE,TRUE},
//
+ // SMRAM ranges not covered by
mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz (to be fixed in runtime).
+ // It is always present and instruction fetches are allowed.
+ // {{0x, 0x},TRUE,FALSE},
+ //
+
+ //
// Future extended range could be added here.
//
@@ -360,7 +366,7 @@ InitProtectedMemRange (
{
UINTNIndex;
UINTNNumberOfDescriptors;
- UINTNNumberOfMmioDescriptors;
+ UINTNNumberOfAddedDescriptors;
UINTNNumberOfProtectRange;
UINTNNumberOfSpliteRange;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
@@ -373,7 +379,7 @@ InitProtectedMemRange (
UINT64 Low4KBPageSize;
NumberOfDescriptors = 0;
- NumberOfMmioDescriptors = 0;
+ NumberOfAddedDescriptors = mSmmCpuSmramRangeCount;
NumberOfSpliteRange = 0;
MemorySpaceMap = NULL;
@@ -386,12 +392,12 @@ InitProtectedMemRange (
);
for (Index = 0; Index < NumberOfDescriptors; Index++) {
if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo)
{
- NumberOfMmioDescriptors++;
+ NumberOfAddedDescriptors++;
}
}
- if (NumberOfMmioDescriptors != 0) {
-TotalSize = NumberOfMmioDescriptors * sizeof (MEMORY_PROTECTION_RANGE) +
sizeof (mProtectionMemRangeTemplate);
+ if (NumberOfAddedDescriptors != 0) {
+TotalSize = NumberOfAddedDescriptors * sizeof (MEMORY_PROTECTION_RANGE) +
sizeof (mProtectionMemRangeTemplate);
mProtectionMemRange = (MEMORY_PROTECTION_RANGE *) AllocateZeroPool
(TotalSize);
ASSERT (mProtectionMemRange != NULL);
mProtectionMemRangeCount = TotalSize / sizeof (MEMORY_PROTECTION_RANGE);
@@ -409,9 +415,27 @@ InitProtectedMemRange (
ASSERT (mSplitMemRange != NULL);
//
+// Create SMM ranges which are set to present and execution-enable.
+//
+NumberOfProtectRange = sizeof (mProtectionMemRangeTemplate) / sizeof
(MEMORY_PROTECTION_RANGE);
+for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
+ if (mSmmCpuSmramRanges[Index].CpuStart >=
mProtectionMemRange[0].Range.Base &&
+ mSmmCpuSmramRanges[Index].CpuStart +
mSmmCpuSmramRanges[Index].PhysicalSize < mProtectionMemRange[0].Range.Top) {
+//
+// If the address have been already covered by
mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz
+//
+break;
+ }
+ mProtectionMemRange[NumberOfProtectRange].Range.Base =
mSmmCpuSmramRanges[Index].CpuStart;
+ mProtectionMemRange[NumberOfProtectRange].Range.Top =
mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize;
+ mProtectionMemRange[NumberOfProtectRange].Present= TRUE;
+ mProtectionMemRange[NumberOfProtectRange].Nx = FALSE;
+ NumberOfProtectRange++;
+}
+
+//
// Create MMIO ranges which are set to present and execution-disable.
//
-NumberOfProtectRange= sizeof (mProtectionMemRangeTemplate) / sizeof
(MEMORY_PROTECTION_RANGE);
for (Index = 0; Index < NumberOfDescriptors; Index++) {
if (MemorySpaceMap[Index].GcdMemoryType !=
EfiGcdMemoryTypeMemoryMappedIo) {
continue;
@@ -422,6 +446,12 @@ InitProtectedMemRange (
mProtectionMemRange[NumberOfProtectRange].Nx = TRUE;
NumberOfProtectRange++;
}
+
+//
+// Check and updated actual protected memory ranges count
+//
+ASSERT (NumberOfProtectRange <= mProtectionMemRangeCount);
+mProtectionMemRangeCount = NumberOfProtectRange;
}
//
--
2.9.3.windows.2
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[edk2] [PATCH v2 1/3] UefiCpuPkg/PiSmmCpuDxeSmm: Save SMM ranges info into global variables
v2:
Add #define SMRR_MAX_ADDRESS to clarify SMRR requirement.
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 44 --
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 6 +++-
2 files changed, 29 insertions(+), 21 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index d061482..47cba10 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -108,6 +108,12 @@ UINT64 mAddressEncMask = 0;
//
SPIN_LOCK*mConfigSmmCodeAccessCheckLock = NULL;
+//
+// Saved SMM ranges information
+//
+EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;
+UINTNmSmmCpuSmramRangeCount;
+
/**
Initialize IDT to setup exception handlers for SMM.
@@ -971,8 +977,6 @@ FindSmramInfo (
UINTN Size;
EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
EFI_SMRAM_DESCRIPTOR *CurrentSmramRange;
- EFI_SMRAM_DESCRIPTOR *SmramRanges;
- UINTN SmramRangeCount;
UINTN Index;
UINT64MaxSize;
BOOLEAN Found;
@@ -990,31 +994,31 @@ FindSmramInfo (
Status = SmmAccess->GetCapabilities (SmmAccess, , NULL);
ASSERT (Status == EFI_BUFFER_TOO_SMALL);
- SmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);
- ASSERT (SmramRanges != NULL);
+ mSmmCpuSmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);
+ ASSERT (mSmmCpuSmramRanges != NULL);
- Status = SmmAccess->GetCapabilities (SmmAccess, , SmramRanges);
+ Status = SmmAccess->GetCapabilities (SmmAccess, , mSmmCpuSmramRanges);
ASSERT_EFI_ERROR (Status);
- SmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);
+ mSmmCpuSmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);
//
// Find the largest SMRAM range between 1MB and 4GB that is at least 256K -
4K in size
//
CurrentSmramRange = NULL;
- for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index <
SmramRangeCount; Index++) {
+ for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index <
mSmmCpuSmramRangeCount; Index++) {
//
// Skip any SMRAM region that is already allocated, needs testing, or
needs ECC initialization
//
-if ((SmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING |
EFI_NEEDS_ECC_INITIALIZATION)) != 0) {
+if ((mSmmCpuSmramRanges[Index].RegionState & (EFI_ALLOCATED |
EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {
continue;
}
-if (SmramRanges[Index].CpuStart >= BASE_1MB) {
- if ((SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize) <=
BASE_4GB) {
-if (SmramRanges[Index].PhysicalSize >= MaxSize) {
- MaxSize = SmramRanges[Index].PhysicalSize;
- CurrentSmramRange = [Index];
+if (mSmmCpuSmramRanges[Index].CpuStart >= BASE_1MB) {
+ if ((mSmmCpuSmramRanges[Index].CpuStart +
mSmmCpuSmramRanges[Index].PhysicalSize) <= SMRR_MAX_ADDRESS) {
+if (mSmmCpuSmramRanges[Index].PhysicalSize >= MaxSize) {
+ MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize;
+ CurrentSmramRange = [Index];
}
}
}
@@ -1027,19 +1031,19 @@ FindSmramInfo (
do {
Found = FALSE;
-for (Index = 0; Index < SmramRangeCount; Index++) {
- if (SmramRanges[Index].CpuStart < *SmrrBase && *SmrrBase ==
(SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize)) {
-*SmrrBase = (UINT32)SmramRanges[Index].CpuStart;
-*SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize);
+for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
+ if (mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase &&
+ *SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart +
mSmmCpuSmramRanges[Index].PhysicalSize)) {
+*SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart;
+*SmrrSize = (UINT32)(*SmrrSize +
mSmmCpuSmramRanges[Index].PhysicalSize);
Found = TRUE;
- } else if ((*SmrrBase + *SmrrSize) == SmramRanges[Index].CpuStart &&
SmramRanges[Index].PhysicalSize > 0) {
-*SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize);
+ } else if ((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart
&& mSmmCpuSmramRanges[Index].PhysicalSize > 0) {
+*SmrrSize = (UINT32)(*SmrrSize +
mSmmCpuSmramRanges[Index].PhysicalSize);
Found = TRUE;
}
}
} while (Found);
- FreePool (SmramRanges);
DEBUG ((EFI_D_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase,
[edk2] [PATCH 1/3] UefiCpuPkg/PiSmmCpuDxeSmm: Save SMM ranges info into global variables
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 44 --
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 4 ++-
2 files changed, 27 insertions(+), 21 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index d061482..bcdb498 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -108,6 +108,12 @@ UINT64 mAddressEncMask = 0;
//
SPIN_LOCK*mConfigSmmCodeAccessCheckLock = NULL;
+//
+// Saved SMM ranges information
+//
+EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;
+UINTNmSmmCpuSmramRangeCount;
+
/**
Initialize IDT to setup exception handlers for SMM.
@@ -971,8 +977,6 @@ FindSmramInfo (
UINTN Size;
EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
EFI_SMRAM_DESCRIPTOR *CurrentSmramRange;
- EFI_SMRAM_DESCRIPTOR *SmramRanges;
- UINTN SmramRangeCount;
UINTN Index;
UINT64MaxSize;
BOOLEAN Found;
@@ -990,31 +994,31 @@ FindSmramInfo (
Status = SmmAccess->GetCapabilities (SmmAccess, , NULL);
ASSERT (Status == EFI_BUFFER_TOO_SMALL);
- SmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);
- ASSERT (SmramRanges != NULL);
+ mSmmCpuSmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);
+ ASSERT (mSmmCpuSmramRanges != NULL);
- Status = SmmAccess->GetCapabilities (SmmAccess, , SmramRanges);
+ Status = SmmAccess->GetCapabilities (SmmAccess, , mSmmCpuSmramRanges);
ASSERT_EFI_ERROR (Status);
- SmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);
+ mSmmCpuSmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);
//
// Find the largest SMRAM range between 1MB and 4GB that is at least 256K -
4K in size
//
CurrentSmramRange = NULL;
- for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index <
SmramRangeCount; Index++) {
+ for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index <
mSmmCpuSmramRangeCount; Index++) {
//
// Skip any SMRAM region that is already allocated, needs testing, or
needs ECC initialization
//
-if ((SmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING |
EFI_NEEDS_ECC_INITIALIZATION)) != 0) {
+if ((mSmmCpuSmramRanges[Index].RegionState & (EFI_ALLOCATED |
EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {
continue;
}
-if (SmramRanges[Index].CpuStart >= BASE_1MB) {
- if ((SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize) <=
BASE_4GB) {
-if (SmramRanges[Index].PhysicalSize >= MaxSize) {
- MaxSize = SmramRanges[Index].PhysicalSize;
- CurrentSmramRange = [Index];
+if (mSmmCpuSmramRanges[Index].CpuStart >= BASE_1MB) {
+ if ((mSmmCpuSmramRanges[Index].CpuStart +
mSmmCpuSmramRanges[Index].PhysicalSize) <= BASE_4GB) {
+if (mSmmCpuSmramRanges[Index].PhysicalSize >= MaxSize) {
+ MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize;
+ CurrentSmramRange = [Index];
}
}
}
@@ -1027,19 +1031,19 @@ FindSmramInfo (
do {
Found = FALSE;
-for (Index = 0; Index < SmramRangeCount; Index++) {
- if (SmramRanges[Index].CpuStart < *SmrrBase && *SmrrBase ==
(SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize)) {
-*SmrrBase = (UINT32)SmramRanges[Index].CpuStart;
-*SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize);
+for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
+ if (mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase &&
+ *SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart +
mSmmCpuSmramRanges[Index].PhysicalSize)) {
+*SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart;
+*SmrrSize = (UINT32)(*SmrrSize +
mSmmCpuSmramRanges[Index].PhysicalSize);
Found = TRUE;
- } else if ((*SmrrBase + *SmrrSize) == SmramRanges[Index].CpuStart &&
SmramRanges[Index].PhysicalSize > 0) {
-*SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize);
+ } else if ((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart
&& mSmmCpuSmramRanges[Index].PhysicalSize > 0) {
+*SmrrSize = (UINT32)(*SmrrSize +
mSmmCpuSmramRanges[Index].PhysicalSize);
Found = TRUE;
}
}
} while (Found);
- FreePool (SmramRanges);
DEBUG ((EFI_D_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase,
*SmrrSize));
}
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
b/Ue
[edk2] [PATCH 3/3] UefiCpuPkg/PiSmmCpuDxeSmm: Update saved SMM ranges check in SmmProfile
SmmProfile feature required to protect all SMM ranges by structure
mProtectionMemRangeTemplate. This update is to add additonal save SMM ranges
into mProtectionMemRangeTemplate besides the range specified by
mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz.
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 42 +-
1 file changed, 36 insertions(+), 6 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index 7125aec..2713b19 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -83,6 +83,12 @@ MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[] = {
{{0x, 0x},TRUE,TRUE},
//
+ // SMRAM ranges not covered by
mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz (to be fixed in runtime).
+ // It is always present and instruction fetches are allowed.
+ // {{0x, 0x},TRUE,FALSE},
+ //
+
+ //
// Future extended range could be added here.
//
@@ -360,7 +366,7 @@ InitProtectedMemRange (
{
UINTNIndex;
UINTNNumberOfDescriptors;
- UINTNNumberOfMmioDescriptors;
+ UINTNNumberOfAddedDescriptors;
UINTNNumberOfProtectRange;
UINTNNumberOfSpliteRange;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
@@ -373,7 +379,7 @@ InitProtectedMemRange (
UINT64 Low4KBPageSize;
NumberOfDescriptors = 0;
- NumberOfMmioDescriptors = 0;
+ NumberOfAddedDescriptors = mSmmCpuSmramRangeCount;
NumberOfSpliteRange = 0;
MemorySpaceMap = NULL;
@@ -386,12 +392,12 @@ InitProtectedMemRange (
);
for (Index = 0; Index < NumberOfDescriptors; Index++) {
if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo)
{
- NumberOfMmioDescriptors++;
+ NumberOfAddedDescriptors++;
}
}
- if (NumberOfMmioDescriptors != 0) {
-TotalSize = NumberOfMmioDescriptors * sizeof (MEMORY_PROTECTION_RANGE) +
sizeof (mProtectionMemRangeTemplate);
+ if (NumberOfAddedDescriptors != 0) {
+TotalSize = NumberOfAddedDescriptors * sizeof (MEMORY_PROTECTION_RANGE) +
sizeof (mProtectionMemRangeTemplate);
mProtectionMemRange = (MEMORY_PROTECTION_RANGE *) AllocateZeroPool
(TotalSize);
ASSERT (mProtectionMemRange != NULL);
mProtectionMemRangeCount = TotalSize / sizeof (MEMORY_PROTECTION_RANGE);
@@ -409,9 +415,27 @@ InitProtectedMemRange (
ASSERT (mSplitMemRange != NULL);
//
+// Create SMM ranges which are set to present and execution-enable.
+//
+NumberOfProtectRange = sizeof (mProtectionMemRangeTemplate) / sizeof
(MEMORY_PROTECTION_RANGE);
+for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
+ if (mSmmCpuSmramRanges[Index].CpuStart >=
mProtectionMemRange[0].Range.Base &&
+ mSmmCpuSmramRanges[Index].CpuStart +
mSmmCpuSmramRanges[Index].PhysicalSize < mProtectionMemRange[0].Range.Top) {
+//
+// If the address have been already covered by
mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz
+//
+break;
+ }
+ mProtectionMemRange[NumberOfProtectRange].Range.Base =
mSmmCpuSmramRanges[Index].CpuStart;
+ mProtectionMemRange[NumberOfProtectRange].Range.Top =
mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize;
+ mProtectionMemRange[NumberOfProtectRange].Present= TRUE;
+ mProtectionMemRange[NumberOfProtectRange].Nx = FALSE;
+ NumberOfProtectRange++;
+}
+
+//
// Create MMIO ranges which are set to present and execution-disable.
//
-NumberOfProtectRange= sizeof (mProtectionMemRangeTemplate) / sizeof
(MEMORY_PROTECTION_RANGE);
for (Index = 0; Index < NumberOfDescriptors; Index++) {
if (MemorySpaceMap[Index].GcdMemoryType !=
EfiGcdMemoryTypeMemoryMappedIo) {
continue;
@@ -422,6 +446,12 @@ InitProtectedMemRange (
mProtectionMemRange[NumberOfProtectRange].Nx = TRUE;
NumberOfProtectRange++;
}
+
+//
+// Check and updated actual protected memory ranges count
+//
+ASSERT (NumberOfProtectRange <= mProtectionMemRangeCount);
+mProtectionMemRangeCount = NumberOfProtectRange;
}
//
--
2.9.3.windows.2
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[edk2] [PATCH 2/3] UefiCpuPkg/PiSmmCpuDxeSmm: Add IsInSmmRanges() to check SMM range
Internal function IsInSmmRanges() is added t check SMM range by saved SMM ranges
beside by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz.
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 36 +-
1 file changed, 31 insertions(+), 5 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index 1b84e2c..7125aec 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -1,7 +1,7 @@
/** @file
Enable SMM profile.
-Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
This program and the accompanying materials
@@ -247,6 +247,33 @@ DebugExceptionHandler (
}
/**
+ Check if the input address is in SMM ranges.
+
+ @param[in] Address The input address.
+
+ @retval TRUE The input address is in SMM.
+ @retval FALSEThe input address is not in SMM.
+**/
+BOOLEAN
+IsInSmmRanges (
+ IN EFI_PHYSICAL_ADDRESS Address
+ )
+{
+ UINTN Index;
+
+ if ((Address < mCpuHotPlugData.SmrrBase) || (Address >=
mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
+return TRUE;
+ }
+ for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
+if (Address >= mSmmCpuSmramRanges[Index].CpuStart &&
+Address < mSmmCpuSmramRanges[Index].CpuStart +
mSmmCpuSmramRanges[Index].PhysicalSize) {
+ return TRUE;
+}
+ }
+ return FALSE;
+}
+
+/**
Check if the memory address will be mapped by 4KB-page.
@param Address The address of Memory.
@@ -261,7 +288,6 @@ IsAddressValid (
{
UINTN Index;
- *Nx = FALSE;
if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
//
// Check configuration
@@ -276,9 +302,9 @@ IsAddressValid (
return FALSE;
} else {
-if ((Address < mCpuHotPlugData.SmrrBase) ||
-(Address >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
- *Nx = TRUE;
+*Nx = TRUE;
+if (IsInSmmRanges (Address)) {
+ *Nx = FALSE;
}
return TRUE;
}
--
2.9.3.windows.2
___
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[edk2] [PATCH 0/3] UefiCpuPkg/PiSmmCpuDxeSmm: Check all SMM ranges found
NX/SmmProfile feature required to protect all SMM ranges. This update is to check additonal saved SMM ranges besides the range specified by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz. Cc: Jiewen Yao <jiewen@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Cc: Feng Tian <feng.t...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff....@intel.com> Jeff Fan (3): UefiCpuPkg/PiSmmCpuDxeSmm: Save SMM ranges info into global variables UefiCpuPkg/PiSmmCpuDxeSmm: Add IsInSmmRanges() to check SMM range UefiCpuPkg/PiSmmCpuDxeSmm: Update saved SMM ranges check in SmmProfile UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 44 + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 4 +- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 78 +- 3 files changed, 94 insertions(+), 32 deletions(-) -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 2/3] UefiCpuPkg/PiSmmCpuDxeSmm: Add IsInSmmRanges() to check SMM range
Internal function IsInSmmRanges() is added t check SMM range by saved SMM ranges
beside by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz.
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 36 +-
1 file changed, 31 insertions(+), 5 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index 1b84e2c..7125aec 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -1,7 +1,7 @@
/** @file
Enable SMM profile.
-Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
This program and the accompanying materials
@@ -247,6 +247,33 @@ DebugExceptionHandler (
}
/**
+ Check if the input address is in SMM ranges.
+
+ @param[in] Address The input address.
+
+ @retval TRUE The input address is in SMM.
+ @retval FALSEThe input address is not in SMM.
+**/
+BOOLEAN
+IsInSmmRanges (
+ IN EFI_PHYSICAL_ADDRESS Address
+ )
+{
+ UINTN Index;
+
+ if ((Address < mCpuHotPlugData.SmrrBase) || (Address >=
mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
+return TRUE;
+ }
+ for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
+if (Address >= mSmmCpuSmramRanges[Index].CpuStart &&
+Address < mSmmCpuSmramRanges[Index].CpuStart +
mSmmCpuSmramRanges[Index].PhysicalSize) {
+ return TRUE;
+}
+ }
+ return FALSE;
+}
+
+/**
Check if the memory address will be mapped by 4KB-page.
@param Address The address of Memory.
@@ -261,7 +288,6 @@ IsAddressValid (
{
UINTN Index;
- *Nx = FALSE;
if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
//
// Check configuration
@@ -276,9 +302,9 @@ IsAddressValid (
return FALSE;
} else {
-if ((Address < mCpuHotPlugData.SmrrBase) ||
-(Address >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
- *Nx = TRUE;
+*Nx = TRUE;
+if (IsInSmmRanges (Address)) {
+ *Nx = FALSE;
}
return TRUE;
}
--
2.9.3.windows.2
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[edk2] [PATCH 1/3] UefiCpuPkg/PiSmmCpuDxeSmm: Save SMM ranges info into global variables
NX/SmmProfile feature required to protect all SMM ranges. This update is
to check all saved SMM ranges by SMM ACCESS protocol besides the range
specified by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz.
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 44 --
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 4 ++-
2 files changed, 27 insertions(+), 21 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index d061482..bcdb498 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -108,6 +108,12 @@ UINT64 mAddressEncMask = 0;
//
SPIN_LOCK*mConfigSmmCodeAccessCheckLock = NULL;
+//
+// Saved SMM ranges information
+//
+EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;
+UINTNmSmmCpuSmramRangeCount;
+
/**
Initialize IDT to setup exception handlers for SMM.
@@ -971,8 +977,6 @@ FindSmramInfo (
UINTN Size;
EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
EFI_SMRAM_DESCRIPTOR *CurrentSmramRange;
- EFI_SMRAM_DESCRIPTOR *SmramRanges;
- UINTN SmramRangeCount;
UINTN Index;
UINT64MaxSize;
BOOLEAN Found;
@@ -990,31 +994,31 @@ FindSmramInfo (
Status = SmmAccess->GetCapabilities (SmmAccess, , NULL);
ASSERT (Status == EFI_BUFFER_TOO_SMALL);
- SmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);
- ASSERT (SmramRanges != NULL);
+ mSmmCpuSmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);
+ ASSERT (mSmmCpuSmramRanges != NULL);
- Status = SmmAccess->GetCapabilities (SmmAccess, , SmramRanges);
+ Status = SmmAccess->GetCapabilities (SmmAccess, , mSmmCpuSmramRanges);
ASSERT_EFI_ERROR (Status);
- SmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);
+ mSmmCpuSmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);
//
// Find the largest SMRAM range between 1MB and 4GB that is at least 256K -
4K in size
//
CurrentSmramRange = NULL;
- for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index <
SmramRangeCount; Index++) {
+ for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index <
mSmmCpuSmramRangeCount; Index++) {
//
// Skip any SMRAM region that is already allocated, needs testing, or
needs ECC initialization
//
-if ((SmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING |
EFI_NEEDS_ECC_INITIALIZATION)) != 0) {
+if ((mSmmCpuSmramRanges[Index].RegionState & (EFI_ALLOCATED |
EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {
continue;
}
-if (SmramRanges[Index].CpuStart >= BASE_1MB) {
- if ((SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize) <=
BASE_4GB) {
-if (SmramRanges[Index].PhysicalSize >= MaxSize) {
- MaxSize = SmramRanges[Index].PhysicalSize;
- CurrentSmramRange = [Index];
+if (mSmmCpuSmramRanges[Index].CpuStart >= BASE_1MB) {
+ if ((mSmmCpuSmramRanges[Index].CpuStart +
mSmmCpuSmramRanges[Index].PhysicalSize) <= BASE_4GB) {
+if (mSmmCpuSmramRanges[Index].PhysicalSize >= MaxSize) {
+ MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize;
+ CurrentSmramRange = [Index];
}
}
}
@@ -1027,19 +1031,19 @@ FindSmramInfo (
do {
Found = FALSE;
-for (Index = 0; Index < SmramRangeCount; Index++) {
- if (SmramRanges[Index].CpuStart < *SmrrBase && *SmrrBase ==
(SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize)) {
-*SmrrBase = (UINT32)SmramRanges[Index].CpuStart;
-*SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize);
+for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
+ if (mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase &&
+ *SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart +
mSmmCpuSmramRanges[Index].PhysicalSize)) {
+*SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart;
+*SmrrSize = (UINT32)(*SmrrSize +
mSmmCpuSmramRanges[Index].PhysicalSize);
Found = TRUE;
- } else if ((*SmrrBase + *SmrrSize) == SmramRanges[Index].CpuStart &&
SmramRanges[Index].PhysicalSize > 0) {
-*SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize);
+ } else if ((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart
&& mSmmCpuSmramRanges[Index].PhysicalSize > 0) {
+*SmrrSize = (UINT32)(*SmrrSize +
mSmmCpuSmramRanges[Index].PhysicalSize);
Found = TRUE;
}
[edk2] [PATCH 3/3] UefiCpuPkg/PiSmmCpuDxeSmm: Update saved SMM ranges check in SmmProfile
SmmProfile feature required to protect all SMM ranges by structure
mProtectionMemRangeTemplate. This update is to add additonal save SMM ranges
into mProtectionMemRangeTemplate besides the range specified by
mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz.
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 42 +-
1 file changed, 36 insertions(+), 6 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index 7125aec..2713b19 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -83,6 +83,12 @@ MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[] = {
{{0x, 0x},TRUE,TRUE},
//
+ // SMRAM ranges not covered by
mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz (to be fixed in runtime).
+ // It is always present and instruction fetches are allowed.
+ // {{0x, 0x},TRUE,FALSE},
+ //
+
+ //
// Future extended range could be added here.
//
@@ -360,7 +366,7 @@ InitProtectedMemRange (
{
UINTNIndex;
UINTNNumberOfDescriptors;
- UINTNNumberOfMmioDescriptors;
+ UINTNNumberOfAddedDescriptors;
UINTNNumberOfProtectRange;
UINTNNumberOfSpliteRange;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
@@ -373,7 +379,7 @@ InitProtectedMemRange (
UINT64 Low4KBPageSize;
NumberOfDescriptors = 0;
- NumberOfMmioDescriptors = 0;
+ NumberOfAddedDescriptors = mSmmCpuSmramRangeCount;
NumberOfSpliteRange = 0;
MemorySpaceMap = NULL;
@@ -386,12 +392,12 @@ InitProtectedMemRange (
);
for (Index = 0; Index < NumberOfDescriptors; Index++) {
if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo)
{
- NumberOfMmioDescriptors++;
+ NumberOfAddedDescriptors++;
}
}
- if (NumberOfMmioDescriptors != 0) {
-TotalSize = NumberOfMmioDescriptors * sizeof (MEMORY_PROTECTION_RANGE) +
sizeof (mProtectionMemRangeTemplate);
+ if (NumberOfAddedDescriptors != 0) {
+TotalSize = NumberOfAddedDescriptors * sizeof (MEMORY_PROTECTION_RANGE) +
sizeof (mProtectionMemRangeTemplate);
mProtectionMemRange = (MEMORY_PROTECTION_RANGE *) AllocateZeroPool
(TotalSize);
ASSERT (mProtectionMemRange != NULL);
mProtectionMemRangeCount = TotalSize / sizeof (MEMORY_PROTECTION_RANGE);
@@ -409,9 +415,27 @@ InitProtectedMemRange (
ASSERT (mSplitMemRange != NULL);
//
+// Create SMM ranges which are set to present and execution-enable.
+//
+NumberOfProtectRange = sizeof (mProtectionMemRangeTemplate) / sizeof
(MEMORY_PROTECTION_RANGE);
+for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
+ if (mSmmCpuSmramRanges[Index].CpuStart >=
mProtectionMemRange[0].Range.Base &&
+ mSmmCpuSmramRanges[Index].CpuStart +
mSmmCpuSmramRanges[Index].PhysicalSize < mProtectionMemRange[0].Range.Top) {
+//
+// If the address have been already covered by
mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz
+//
+break;
+ }
+ mProtectionMemRange[NumberOfProtectRange].Range.Base =
mSmmCpuSmramRanges[Index].CpuStart;
+ mProtectionMemRange[NumberOfProtectRange].Range.Top =
mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize;
+ mProtectionMemRange[NumberOfProtectRange].Present= TRUE;
+ mProtectionMemRange[NumberOfProtectRange].Nx = FALSE;
+ NumberOfProtectRange++;
+}
+
+//
// Create MMIO ranges which are set to present and execution-disable.
//
-NumberOfProtectRange= sizeof (mProtectionMemRangeTemplate) / sizeof
(MEMORY_PROTECTION_RANGE);
for (Index = 0; Index < NumberOfDescriptors; Index++) {
if (MemorySpaceMap[Index].GcdMemoryType !=
EfiGcdMemoryTypeMemoryMappedIo) {
continue;
@@ -422,6 +446,12 @@ InitProtectedMemRange (
mProtectionMemRange[NumberOfProtectRange].Nx = TRUE;
NumberOfProtectRange++;
}
+
+//
+// Check and updated actual protected memory ranges count
+//
+ASSERT (NumberOfProtectRange <= mProtectionMemRangeCount);
+mProtectionMemRangeCount = NumberOfProtectRange;
}
//
--
2.9.3.windows.2
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[edk2] [PATCH 0/3] UefiCpuPkg/PiSmmCpuDxeSmm: Check all SMM ranges found
NX/SmmProfile feature required to protect all SMM ranges. This update is to check additonal saved SMM ranges besides the range specified by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz. Cc: Jiewen Yao <jiewen@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Cc: Feng Tian <feng.t...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff....@intel.com> Jeff Fan (3): UefiCpuPkg/PiSmmCpuDxeSmm: Save SMM ranges info into global variables UefiCpuPkg/PiSmmCpuDxeSmm: Add IsInSmmRanges() to check SMM range UefiCpuPkg/PiSmmCpuDxeSmm: Update saved SMM ranges check in SmmProfile UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 44 + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 4 +- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 78 +- 3 files changed, 94 insertions(+), 32 deletions(-) -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH v2] UefiCpuPkg/MpLib.c: Add checking CR0 PG bit
If CR0 PG bit is not set, it means paging is not enabled on BSP. Thus, Execute
Disable feature is not working actually. Thus, we cannot enable it on APs.
v2:
Correct the commit log.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/MpInitLib/MpLib.c | 38 +++-
1 file changed, 24 insertions(+), 14 deletions(-)
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 55fe812..bb93526 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -1,7 +1,7 @@
/** @file
CPU MP Initialize Library common functions.
- Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -18,8 +18,11 @@ EFI_GUID mCpuInitMpLibHobGuid = CPU_INIT_MP_LIB_HOB_GUID;
/**
The function will check if BSP Execute Disable is enabled.
- DxeIpl may have enabled Execute Disable for BSP,
- APs need to get the status and sync up the settings.
+
+ DxeIpl may have enabled Execute Disable for BSP, APs need to
+ get the status and sync up the settings.
+ If BSP's CR0.Paging is not set, BSP execute Disble feature is
+ not working actually.
@retval TRUE BSP Execute Disable is enabled.
@retval FALSE BSP Execute Disable is not enabled.
@@ -33,23 +36,30 @@ IsBspExecuteDisableEnabled (
CPUID_EXTENDED_CPU_SIG_EDX Edx;
MSR_IA32_EFER_REGISTER EferMsr;
BOOLEAN Enabled;
+ IA32_CR0Cr0;
Enabled = FALSE;
- AsmCpuid (CPUID_EXTENDED_FUNCTION, , NULL, NULL, NULL);
- if (Eax >= CPUID_EXTENDED_CPU_SIG) {
-AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, );
+ Cr0.UintN = AsmReadCr0 ();
+ if (Cr0.Bits.PG != 0) {
//
-// CPUID 0x8001
-// Bit 20: Execute Disable Bit available.
+// If CR0 Paging bit is set
//
-if (Edx.Bits.NX != 0) {
- EferMsr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
+AsmCpuid (CPUID_EXTENDED_FUNCTION, , NULL, NULL, NULL);
+if (Eax >= CPUID_EXTENDED_CPU_SIG) {
+ AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, );
//
- // MSR 0xC080
- // Bit 11: Execute Disable Bit enable.
+ // CPUID 0x8001
+ // Bit 20: Execute Disable Bit available.
//
- if (EferMsr.Bits.NXE != 0) {
-Enabled = TRUE;
+ if (Edx.Bits.NX != 0) {
+EferMsr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
+//
+// MSR 0xC080
+// Bit 11: Execute Disable Bit enable.
+//
+if (EferMsr.Bits.NXE != 0) {
+ Enabled = TRUE;
+}
}
}
}
--
2.9.3.windows.2
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[edk2] [PATCH] UefiCpuPkg/MpLib.c: Add checking CR0 PG bit
If CR0 PG bit is not set, it means paging is enabled on BSP. Thus, Execute
Disable feature is not working actually. We cannot enable it on APs.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/MpInitLib/MpLib.c | 38 +++-
1 file changed, 24 insertions(+), 14 deletions(-)
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index 55fe812..bb93526 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -1,7 +1,7 @@
/** @file
CPU MP Initialize Library common functions.
- Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -18,8 +18,11 @@ EFI_GUID mCpuInitMpLibHobGuid = CPU_INIT_MP_LIB_HOB_GUID;
/**
The function will check if BSP Execute Disable is enabled.
- DxeIpl may have enabled Execute Disable for BSP,
- APs need to get the status and sync up the settings.
+
+ DxeIpl may have enabled Execute Disable for BSP, APs need to
+ get the status and sync up the settings.
+ If BSP's CR0.Paging is not set, BSP execute Disble feature is
+ not working actually.
@retval TRUE BSP Execute Disable is enabled.
@retval FALSE BSP Execute Disable is not enabled.
@@ -33,23 +36,30 @@ IsBspExecuteDisableEnabled (
CPUID_EXTENDED_CPU_SIG_EDX Edx;
MSR_IA32_EFER_REGISTER EferMsr;
BOOLEAN Enabled;
+ IA32_CR0Cr0;
Enabled = FALSE;
- AsmCpuid (CPUID_EXTENDED_FUNCTION, , NULL, NULL, NULL);
- if (Eax >= CPUID_EXTENDED_CPU_SIG) {
-AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, );
+ Cr0.UintN = AsmReadCr0 ();
+ if (Cr0.Bits.PG != 0) {
//
-// CPUID 0x8001
-// Bit 20: Execute Disable Bit available.
+// If CR0 Paging bit is set
//
-if (Edx.Bits.NX != 0) {
- EferMsr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
+AsmCpuid (CPUID_EXTENDED_FUNCTION, , NULL, NULL, NULL);
+if (Eax >= CPUID_EXTENDED_CPU_SIG) {
+ AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, );
//
- // MSR 0xC080
- // Bit 11: Execute Disable Bit enable.
+ // CPUID 0x8001
+ // Bit 20: Execute Disable Bit available.
//
- if (EferMsr.Bits.NXE != 0) {
-Enabled = TRUE;
+ if (Edx.Bits.NX != 0) {
+EferMsr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
+//
+// MSR 0xC080
+// Bit 11: Execute Disable Bit enable.
+//
+if (EferMsr.Bits.NXE != 0) {
+ Enabled = TRUE;
+}
}
}
}
--
2.9.3.windows.2
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[edk2] [PATCH 1/5] UefiCpuPkg/RegisterCpuFeaturesLib: Fix the function header issues
Cc: Feng Tian <feng.t...@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff@intel.com> --- .../Include/Library/RegisterCpuFeaturesLib.h | 60 +++-- .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 2 +- .../DxeRegisterCpuFeaturesLib.c| 2 +- .../PeiRegisterCpuFeaturesLib.c| 2 +- .../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 2 +- .../RegisterCpuFeaturesLib.c | 62 +++--- 6 files changed, 67 insertions(+), 63 deletions(-) diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h index 3fb8209..81a1f4b 100644 --- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h @@ -257,35 +257,37 @@ RETURN_STATUS /** Registers a CPU Feature. - @param GetConfigDataFunc CPU feature get configuration data function. This - is an optional parameter that may be NULL. If NULL, - then the most recently registered function for the - CPU feature is used. If no functions are registered - for a CPU feature, then the CPU configuration data - for the registered feature is NULL. - @param SupportFuncCPU feature support function. This is an optional - parameter that may be NULL. If NULL, then the most - recently registered function for the CPU feature is - used. If no functions are registered for a CPU - feature, then the CPU feature is assumed to be - supported by all CPUs. - @param InitializeFunc CPU feature initialize function. This is an optional - parameter that may be NULL. If NULL, then the most - recently registered function for the CPU feature is - used. If no functions are registered for a CPU - feature, then the CPU feature initialization is - skipped. - @param ...Variable argument list of UINT32 CPU feature value. - Values with no modifiers are the features provided - by the registered functions. - Values with CPU_FEATURE_BEFORE modifier are features - that must be initialized after the features provided - by the registered functions are used. - Values with CPU_FEATURE_AFTER modifier are features - that must be initialized before the features provided - by the registered functions are used. - The last argument in this variable argument list must - always be CPU_FEATURE_END. + @param[in] FeatureNameA Null-terminated Ascii string indicates CPU feature + name. + @param[in] GetConfigDataFunc CPU feature get configuration data function. This + is an optional parameter that may be NULL. If NULL, + then the most recently registered function for the + CPU feature is used. If no functions are registered + for a CPU feature, then the CPU configuration data + for the registered feature is NULL. + @param[in] SupportFuncCPU feature support function. This is an optional + parameter that may be NULL. If NULL, then the most + recently registered function for the CPU feature is + used. If no functions are registered for a CPU + feature, then the CPU feature is assumed to be + supported by all CPUs. + @param[in] InitializeFunc CPU feature initialize function. This is an optional + parameter that may be NULL. If NULL, then the most + recently registered function for the CPU feature is + used. If no functions are registered for a CPU + feature, then the CPU feature initialization is + skipped. + @param[in] ...Variable argument list of UINT32 CPU feature value. + Values with no modifiers are the features provided +
[edk2] [PATCH 0/5] [UefiCpuPkg/CpuFeatures] Fix some comments and meta data issues.
Cc: Feng Tian <feng.t...@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Jeff Fan (5): UefiCpuPkg/RegisterCpuFeaturesLib: Fix the function header issues UefiCpuPkg/RegisterCpuFeaturesLib: Remove static type UefiCpuPkg/RegisterCpuFeaturesLib: Fix meta data comments UefiCpuPkg/CpuCommonFeaturesLib: Generate new INF GUID value UefiCpuPkg: Add new PCDs PROMPT/HELP string in UNI file UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.inf | 4 +- UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf | 2 +- .../Include/Library/RegisterCpuFeaturesLib.h | 60 +++-- .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 8 +-- .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 2 +- .../DxeRegisterCpuFeaturesLib.c| 12 ++--- .../PeiRegisterCpuFeaturesLib.c| 2 +- .../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 2 +- .../RegisterCpuFeaturesLib.c | 62 +++--- UefiCpuPkg/UefiCpuPkg.dec | 12 ++--- UefiCpuPkg/UefiCpuPkg.uni | 31 +++ 11 files changed, 116 insertions(+), 81 deletions(-) -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 2/5] UefiCpuPkg/RegisterCpuFeaturesLib: Remove static type
Using one specific name for global variable to save MP services protocol
pointer.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
index c49f556..74c658a 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
@@ -19,7 +19,7 @@
#include "RegisterCpuFeatures.h"
CPU_FEATURES_DATA mCpuFeaturesData = {0};
-static EFI_MP_SERVICES_PROTOCOL *mMpServices = NULL;
+EFI_MP_SERVICES_PROTOCOL *mCpuFeaturesMpServices = NULL;
/**
Worker function to get CPU_FEATURES_DATA pointer.
@@ -46,20 +46,20 @@ GetMpProtocol (
{
EFI_STATUS Status;
- if (mMpServices == NULL) {
+ if (mCpuFeaturesMpServices == NULL) {
//
// Get MP Services Protocol
//
Status = gBS->LocateProtocol (
,
NULL,
- (VOID **)
+ (VOID **)
);
ASSERT_EFI_ERROR (Status);
}
- ASSERT (mMpServices != NULL);
- return mMpServices;
+ ASSERT (mCpuFeaturesMpServices != NULL);
+ return mCpuFeaturesMpServices;
}
/**
--
2.9.3.windows.2
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[edk2] [PATCH 3/5] UefiCpuPkg/RegisterCpuFeaturesLib: Fix meta data comments
Cc: Feng Tian <feng.t...@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff@intel.com> --- UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.inf| 4 ++-- UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf| 2 +- UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.inf b/UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.inf index 5a3e4f0..dee44e6 100644 --- a/UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.inf +++ b/UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.inf @@ -38,10 +38,10 @@ CpuFeaturesDxe.c [Guids] - gEdkiiCpuFeaturesInitDoneGuid ## PRODUCES + gEdkiiCpuFeaturesInitDoneGuid ## PRODUCES ## UNDEFINED # protocol GUID installed [Protocols] - gEfiSmmConfigurationProtocolGuid## SOMETIME_CONSUMES + gEfiSmmConfigurationProtocolGuid## NOTIFY [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation ## CONSUMES diff --git a/UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf b/UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf index e306bb2..2fb84b1 100644 --- a/UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf +++ b/UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf @@ -37,7 +37,7 @@ CpuFeaturesPei.c [Guids] - gEdkiiCpuFeaturesInitDoneGuid ## PRODUCES + gEdkiiCpuFeaturesInitDoneGuid ## PRODUCES ## UNDEFINED # PPI GUID installed [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume ## CONSUMES diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf index 7287d4e..056b776 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf @@ -62,7 +62,7 @@ LocalApicLib [Pcd] - gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport# CONSUMES - gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle # SOMETIME_CONSUMES - gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset# SOMETIME_CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle ## SOMETIMES_CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset## SOMETIMES_CONSUMES -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 4/5] UefiCpuPkg/CpuCommonFeaturesLib: Generate new INF GUID value
Cc: Feng Tian <feng.t...@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff@intel.com> --- UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf index 056b776..4358196 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf @@ -19,7 +19,7 @@ INF_VERSION= 0x00010005 BASE_NAME = CpuCommonFeaturesLib MODULE_UNI_FILE= CpuCommonFeaturesLib.uni - FILE_GUID = 387A2490-81FC-4E7C-8E0A-3E58C30FCD0B + FILE_GUID = 6D69F79F-9535-4893-9DD7-93929898252C MODULE_TYPE= BASE VERSION_STRING = 1.0 LIBRARY_CLASS = NULL -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 5/5] UefiCpuPkg: Add new PCDs PROMPT/HELP string in UNI file
Correct PCD declaration comments and add new PCDs in UNI file.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/UefiCpuPkg.dec | 12 ++--
UefiCpuPkg/UefiCpuPkg.uni | 31 +++
2 files changed, 37 insertions(+), 6 deletions(-)
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 4a679bd..e87f103 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -192,16 +192,16 @@
# @Prompt MSEG size.
gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x20|UINT32|0x32132112
- ## Specifies the supported CPU features bit in array
- # @Prompt Supported CPU features
+ ## Specifies the supported CPU features bit in array.
+ # @Prompt Supported CPU features.
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x0016
- ## Specifies if CPU features will be initialized after SMM relocation
- # @Prompt if CPU features will be initialized after SMM relocation
+ ## Specifies if CPU features will be initialized after SMM relocation.
+ # @Prompt If CPU features will be initialized after SMM relocation.
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x001C
- ## Specifies if CPU features will be initialized during S3 resume
- # @Prompt if CPU features will be initialized during S3 resume
+ ## Specifies if CPU features will be initialized during S3 resume.
+ # @Prompt If CPU features will be initialized during S3 resume.
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x001D
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
diff --git a/UefiCpuPkg/UefiCpuPkg.uni b/UefiCpuPkg/UefiCpuPkg.uni
index f4dd339..cd0ecab 100644
--- a/UefiCpuPkg/UefiCpuPkg.uni
+++ b/UefiCpuPkg/UefiCpuPkg.uni
@@ -163,3 +163,34 @@
#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuMsegSize_HELP #language en-US
"Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB."
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuFeaturesSupport_PROMPT #language
en-US "Supported CPU features."
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuFeaturesSupport_HELP #language
en-US "Specifies the supported CPU features bit in array."
+
+#string
STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuFeaturesInitAfterSmmRelocation_PROMPT
#language en-US "If CPU features will be initialized after SMM relocation."
+
+#string
STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuFeaturesInitAfterSmmRelocation_HELP
#language en-US "Specifies if CPU features will be initialized after SMM
relocation."
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuFeaturesInitOnS3Resume_PROMPT
#language en-US "If CPU features will be initialized during S3 resume."
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuFeaturesInitOnS3Resume_HELP
#language en-US "Specifies if CPU features will be initialized during S3
resume."
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuFeaturesUserConfiguration_PROMPT
#language en-US "User settings for enabling/disabling processor features."
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuFeaturesUserConfiguration_HELP
#language en-US "Specifies user's desired settings for enabling/disabling
processor features."
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuClockModulationDutyCycle_PROMPT
#language en-US "The encoded values for target duty cycle modulation."
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuClockModulationDutyCycle_HELP
#language en-US "Specifies the On-demand clock modulation duty cycle when ACPI
feature is enabled."
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdIsPowerOnReset_PROMPT #language
en-US "Current boot is a power-on reset."
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdIsPowerOnReset_HELP #language en-US
"Indicates if the current boot is a power-on reset."
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuFeaturesCapability_PROMPT
#language en-US "Processor feature capabilities."
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuFeaturesCapability_HELP #language
en-US "Indicates processor feature capabilities, each bit corresponding to a
specific feature."
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuFeaturesSetting_PROMPT #language
en-US "Actual processor feature settings."
+
+#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuFeaturesSetting_HELP #language
en-US "Specifies actual settings for processor features, each bit corresponding
to a specific feature."
--
2.9.3.windows.2
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[edk2] [PATCH] UefiCpuPkg/RegisterCpuFeaturesLib: Add ASSERT on allocated memory
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index 34e6c6b..cd689af 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -65,6 +65,7 @@ GetSupportPcds (
BitMaskSize = PcdGetSize (PcdCpuFeaturesSupport);
SupportBitMask = AllocateZeroPool (BitMaskSize);
+ ASSERT (SupportBitMask != NULL);
SupportBitMask = (UINT8 *) PcdGetPtr (PcdCpuFeaturesSupport);
return SupportBitMask;
@@ -85,6 +86,7 @@ GetConfigurationPcds (
BitMaskSize = PcdGetSize (PcdCpuFeaturesUserConfiguration);
SupportBitMask = AllocateZeroPool (BitMaskSize);
+ ASSERT (SupportBitMask != NULL);
SupportBitMask = (UINT8 *) PcdGetPtr (PcdCpuFeaturesUserConfiguration);
return SupportBitMask;
@@ -165,6 +167,7 @@ CpuInitDataInitialize (
for (ProcessorNumber = 0; ProcessorNumber < NumberOfCpus; ProcessorNumber++)
{
InitOrder = >InitOrder[ProcessorNumber];
InitOrder->FeaturesSupportedMask = AllocateZeroPool
(CpuFeaturesData->BitMaskSize);
+ASSERT (InitOrder->FeaturesSupportedMask != NULL);
InitializeListHead (>OrderList);
Status = GetProcessorInformation (ProcessorNumber, );
ASSERT_EFI_ERROR (Status);
@@ -417,6 +420,7 @@ AnalysisProcessorFeatures (
CpuFeaturesData = GetCpuFeaturesData ();
CpuFeaturesData->CapabilityPcds = AllocatePool
(CpuFeaturesData->BitMaskSize);
+ ASSERT (CpuFeaturesData->CapabilityPcds != NULL);
SetMem (CpuFeaturesData->CapabilityPcds, CpuFeaturesData->BitMaskSize, 0xFF);
for (ProcessorNumber = 0; ProcessorNumber < NumberOfCpus; ProcessorNumber++)
{
CpuInitOrder = >InitOrder[ProcessorNumber];
@@ -430,6 +434,7 @@ AnalysisProcessorFeatures (
//
CpuFeaturesData->SettingPcds = AllocateCopyPool
(CpuFeaturesData->BitMaskSize, CpuFeaturesData->CapabilityPcds);
+ ASSERT (CpuFeaturesData->SettingPcds != NULL);
SupportedMaskAnd (CpuFeaturesData->SettingPcds,
CpuFeaturesData->ConfigurationPcds);
//
@@ -478,6 +483,7 @@ AnalysisProcessorFeatures (
CpuFeature = CPU_FEATURE_ENTRY_FROM_LINK (Entry);
if (IsBitMaskMatch (CpuFeature->FeatureMask,
CpuFeaturesData->CapabilityPcds)) {
CpuFeatureInOrder = AllocateCopyPool (sizeof (CPU_FEATURES_ENTRY),
CpuFeature);
+ASSERT (CpuFeatureInOrder != NULL);
InsertTailList (>OrderList, >Link);
}
Entry = Entry->ForwardLink;
--
2.9.3.windows.2
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[edk2] [PATCH 0/2] [UefiCpuPkg] Support 64bit MMIO address in CPU Register Table
The current CPU_REGISTER_TABLE_ENTRY structure only defined UINT32 Index to indicate MSR/MMIO address. It's ok for MSR because MSR address is UINT32 type actually. But for MMIO address, UINT32 limits MMIO address exceeds 4GB. https://bugzilla.tianocore.org/show_bug.cgi?id=347 Jeff Fan (2): UefiCpuPkg/RegisterCpuFeaturesLib: Define Index to UINT64 UefiCpuPkg/AcpiCpuData.h: Support >4GB MMIO address UefiCpuPkg/Include/AcpiCpuData.h | 12 +++- UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h | 4 ++-- .../Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 6 +++--- .../Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c | 9 + UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c| 2 +- 5 files changed, 18 insertions(+), 15 deletions(-) -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 2/2] UefiCpuPkg/AcpiCpuData.h: Support >4GB MMIO address
The current CPU_REGISTER_TABLE_ENTRY structure only defined UINT32 Index to
indicate MSR/MMIO address. It's ok for MSR because MSR address is UINT32 type
actually. But for MMIO address, UINT32 limits MMIO address exceeds 4GB.
This update on CPU_REGISTER_TABLE_ENTRY is to add additional UINT32 field
HighIndex to indicate the high 32bit MMIO address and original Index still
indicate the low 32bit MMIO address.
This update makes use of original padding space between ValidBitLength and
Value to add HighIndex.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Include/AcpiCpuData.h | 12 +++-
.../Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 6 +++---
.../Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c | 1 +
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c| 2 +-
4 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuData.h
index 130eb90..ec09207 100644
--- a/UefiCpuPkg/Include/AcpiCpuData.h
+++ b/UefiCpuPkg/Include/AcpiCpuData.h
@@ -29,11 +29,13 @@ typedef enum {
// Element of register table entry
//
typedef struct {
- REGISTER_TYPE RegisterType;
- UINT32 Index;
- UINT8 ValidBitStart;
- UINT8 ValidBitLength;
- UINT64 Value;
+ REGISTER_TYPE RegisterType; // offset 0 - 3
+ UINT32 Index; // offset 4 - 7
+ UINT8 ValidBitStart; // offset 8
+ UINT8 ValidBitLength;// offset 9
+ UINT16 Reserved; // offset 10 - 11
+ UINT32 HighIndex; // offset 12-15, only valid for
MemoryMapped
+ UINT64 Value; // offset 16-23
} CPU_REGISTER_TABLE_ENTRY;
//
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index d879591..34e6c6b 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -370,9 +370,9 @@ DumpRegisterTableOnProcessor (
case MemoryMapped:
DEBUG ((
DebugPrintErrorLevel,
-"Processor: %d: MMIO: %x, Bit Start: %d, Bit Length: %d, Value:
%lx\r\n",
+"Processor: %d: MMIO: %lx, Bit Start: %d, Bit Length: %d, Value:
%lx\r\n",
ProcessorNumber,
-RegisterTableEntry->Index,
+RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex,
32),
RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitLength,
RegisterTableEntry->Value
@@ -628,7 +628,7 @@ ProgramProcessorRegister (
case MemoryMapped:
AcquireSpinLock (>MemoryMappedLock);
MmioBitFieldWrite32 (
-RegisterTableEntry->Index,
+(UINTN)(RegisterTableEntry->Index | LShiftU64
(RegisterTableEntry->HighIndex, 32)),
RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength
- 1,
(UINT32)RegisterTableEntry->Value
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
index 32189cb..3fec2e6 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
@@ -551,6 +551,7 @@ CpuRegisterTableWriteWorker (
RegisterTableEntry = (CPU_REGISTER_TABLE_ENTRY *) (UINTN)
RegisterTable->RegisterTableEntry;
RegisterTableEntry[RegisterTable->TableLength].RegisterType = RegisterType;
RegisterTableEntry[RegisterTable->TableLength].Index = (UINT32)
Index;
+ RegisterTableEntry[RegisterTable->TableLength].HighIndex = (UINT32)
RShiftU64 (Index, 32);
RegisterTableEntry[RegisterTable->TableLength].ValidBitStart =
ValidBitStart;
RegisterTableEntry[RegisterTable->TableLength].ValidBitLength =
ValidBitLength;
RegisterTableEntry[RegisterTable->TableLength].Value = Value;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index c3280b8..9404501 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -315,7 +315,7 @@ SetProcessorRegister (
case MemoryMapped:
AcquireSpinLock (mMemoryMappedLock);
MmioBitFieldWrite32 (
-RegisterTableEntry->Index,
+(UINTN)(RegisterTableEntry->Index | LShiftU64
(RegisterTableEntry->HighIndex, 32)),
RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength
- 1,
(UINT32)RegisterTableEntry-
[edk2] [PATCH 1/2] UefiCpuPkg/RegisterCpuFeaturesLib: Define Index to UINT64
The input parameter Index of PreSmmCpuRegisterTableWrite() and CpuRegisterTableWrite() is defined as UINT32. Index is MSR/MMIO address that will be saved in CPU register table. UINT32 blocks the MMIO address > 4GB. This fix is to define Index to UINT64 instead of UINT32. Cc: Feng Tian <feng.t...@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff@intel.com> --- UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h | 4 ++-- .../Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c | 8 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h index 42eb3b2..3fb8209 100644 --- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h @@ -366,7 +366,7 @@ EFIAPI CpuRegisterTableWrite ( IN UINTN ProcessorNumber, IN REGISTER_TYPE RegisterType, - IN UINT32 Index, + IN UINT64 Index, IN UINT64 ValueMask, IN UINT64 Value ); @@ -390,7 +390,7 @@ EFIAPI PreSmmCpuRegisterTableWrite ( IN UINTN ProcessorNumber, IN REGISTER_TYPE RegisterType, - IN UINT32 Index, + IN UINT64 Index, IN UINT64 ValueMask, IN UINT64 Value ); diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c index 396618b..32189cb 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c @@ -506,7 +506,7 @@ CpuRegisterTableWriteWorker ( IN BOOLEAN PreSmmFlag, IN UINTN ProcessorNumber, IN REGISTER_TYPE RegisterType, - IN UINT32 Index, + IN UINT64 Index, IN UINT8 ValidBitStart, IN UINT8 ValidBitLength, IN UINT64 Value @@ -550,7 +550,7 @@ CpuRegisterTableWriteWorker ( // RegisterTableEntry = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry; RegisterTableEntry[RegisterTable->TableLength].RegisterType = RegisterType; - RegisterTableEntry[RegisterTable->TableLength].Index = Index; + RegisterTableEntry[RegisterTable->TableLength].Index = (UINT32) Index; RegisterTableEntry[RegisterTable->TableLength].ValidBitStart = ValidBitStart; RegisterTableEntry[RegisterTable->TableLength].ValidBitLength = ValidBitLength; RegisterTableEntry[RegisterTable->TableLength].Value = Value; @@ -577,7 +577,7 @@ EFIAPI CpuRegisterTableWrite ( IN UINTN ProcessorNumber, IN REGISTER_TYPE RegisterType, - IN UINT32 Index, + IN UINT64 Index, IN UINT64 ValueMask, IN UINT64 Value ) @@ -611,7 +611,7 @@ EFIAPI PreSmmCpuRegisterTableWrite ( IN UINTN ProcessorNumber, IN REGISTER_TYPE RegisterType, - IN UINT32 Index, + IN UINT64 Index, IN UINT64 ValueMask, IN UINT64 Value ) -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH] UefiCpuPkg/RegisterCpuFeaturesLib: Set CpuFeatureEntry initial value
CpuFeatureEntry will be set before using it. But VS2012 build reported the build
warning "potentially uninitialized local variable 'CpuFeatureEntry' used".
This fix is to set CpuFeatureEntry initial value and add ASSERT check later.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
index 7a1470b..396618b 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
@@ -272,6 +272,7 @@ RegisterCpuFeatureWorker (
ASSERT (CpuFeaturesData->BitMaskSize == BitMaskSize);
FeatureExist = FALSE;
+ CpuFeatureEntry = NULL;
Entry = GetFirstNode (>FeatureList);
while (!IsNull (>FeatureList, Entry)) {
CpuFeatureEntry = CPU_FEATURE_ENTRY_FROM_LINK (Entry);
@@ -293,6 +294,7 @@ RegisterCpuFeatureWorker (
} else {
DEBUG ((DEBUG_INFO, "[OVERRIDE] "));
DumpCpuFeature (CpuFeature);
+ASSERT (CpuFeatureEntry != NULL);
//
// Overwrite original parameters of CPU feature
//
--
2.9.3.windows.2
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[edk2] [PATCH] UefiCpuPkg/CpuCommonFeaturesLib: Fix case write issue
Cc: Feng Tian <feng.t...@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff@intel.com> --- UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h index 63fc03d..8118c1f 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h @@ -25,7 +25,7 @@ #include #include -#include +#include #include /** -- 2.9.3.windows.2 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH v5 00/11] Add CPU features driver
This serial of patches will add CPU featuers initialization on boot time. 1) One new Register CPU Features Library and instances are added to provide the capability to register CPU feature's detect/initialize services. 2) One new NULL class CPU Commong Features Library instance is added to provide detect/initialize servcies of CPU features defined in SDM. 3) New CPU features PEI/DXE drivers are added to initialize CPU features in PEI phase or DXE phase, by consuming Register CPU Features Library. https://bugzilla.tianocore.org/show_bug.cgi?id=421 The whole updated UefiCpuPkg v5 could be accessed at https://github.com/JeffFan/edk2/tree/CpuFeaturesV5/UefiCpuPkg for review. v2: #9: Format debug messages. #10: 1. Using MSR_IA32_EFER to enable/disable NX feature instead of using MSR_IA32_MISC_ENABLE. 2. Fix bug that SMX and VMX feature is swapped. v3: #9: Trim white space at end of line. #10: Add AesniGetConfigData() to get current register state. v4: #3, #8, #9: Fix GCC complied issue. v5: #3: Set DestinationRegisterTableList[Index].RegisterTableEntry before RegisterTableEntry is updated. #10: Move MSR reading from AesniGetConfigData() to AesniSupport(). Cc: Feng Tian <feng.t...@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff....@intel.com> Jeff Fan (11): UefiCpuPkg/AcpiCpuData: Update RegisterTableEntry type UefiCpuPkg/CpuS3DataDxe: Consume the existing PcdCpuS3DataAddress UefiCpuPkg/PiSmmCpuDxeSmm: Skip if AllocatedSize is 0 UefiCpuPkg/Msr: Add CPUID signature check MACROs UefiCpuPkg/UefiCpuPkg.dec: Add a set of CPU features PCDs UefiCpuPkg: Add GUID gEdkiiCpuFeaturesSetDoneGuid UefiCpuPkg: Add GUID gEdkiiCpuFeaturesInitDoneGuid UefiCpuPkg/Include/Library: Add Register CPU Features Library UefiCpuPkg: Add PEI/DXE Register CPU Features Library instances UefiCpuPkg: Add NULL CPU Common Features Library instance UefiCpuPkg: Add CPU Features PEI/DXE drivers UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c| 122 +++ UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.inf | 53 ++ UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.uni | 22 + UefiCpuPkg/CpuFeatures/CpuFeaturesDxeExtra.uni | 20 + UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c| 75 ++ UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf | 49 ++ UefiCpuPkg/CpuFeatures/CpuFeaturesPei.uni | 22 + UefiCpuPkg/CpuFeatures/CpuFeaturesPeiExtra.uni | 20 + UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c| 56 +- UefiCpuPkg/Include/AcpiCpuData.h | 6 +- UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h | 26 + UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h | 26 + .../Include/Library/RegisterCpuFeaturesLib.h | 516 UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 22 +- UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 21 +- UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 19 +- UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 20 +- UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 21 +- UefiCpuPkg/Include/Register/Msr/P6Msr.h| 23 +- UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 15 +- UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 20 +- UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 19 +- UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h| 22 +- UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 19 +- UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 19 +- UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 19 +- UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h| 18 +- UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 18 +- UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c| 127 +++ UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 79 ++ .../Library/CpuCommonFeaturesLib/ClockModulation.c | 106 +++ .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 867 + .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c| 227 ++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 68 ++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.uni | 25 + UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c | 81 ++ .../Library/CpuCommonFeaturesLib/ExecuteDisable.c | 91 +++ .../Library/CpuCommonFeaturesLib/FastStrings.c | 52 ++ .../Library/CpuCommonFeaturesLib/FeatureControl.c | 314 .../CpuCommonFeaturesLib/LimitCpuIdMaxval.c| 82 ++ .../Library/CpuCommonFeaturesLib/MachineCheck.c| 231 ++ .../Library/CpuCommonFeaturesLib/MonitorMwait.c|
[edk2] [PATCH v5 03/11] UefiCpuPkg/PiSmmCpuDxeSmm: Skip if AllocatedSize is 0
Needn't to copy register table if AllocatedSize is 0.
v4:
Fix potential uninitialized variable issue.
v5:
Set DestinationRegisterTableList[Index].RegisterTableEntry before
RegisterTableEntry is updated.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 30 +-
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 12efc1f..c3280b8 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -826,21 +826,25 @@ CopyRegisterTable (
CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus
* sizeof (CPU_REGISTER_TABLE));
for (Index = 0; Index < NumberOfCpus; Index++) {
-RegisterTableEntry = AllocatePool
(DestinationRegisterTableList[Index].AllocatedSize);
-ASSERT (RegisterTableEntry != NULL);
-CopyMem (RegisterTableEntry, (VOID
*)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry,
DestinationRegisterTableList[Index].AllocatedSize);
-//
-// Go though all MSRs in register table to initialize MSR spin lock
-//
-for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength;
Index1++, RegisterTableEntry++) {
- if ((RegisterTableEntry->RegisterType == Msr) &&
(RegisterTableEntry->ValidBitLength < 64)) {
-//
-// Initialize MSR spin lock only for those MSRs need bit field writing
-//
-InitMsrSpinLockByIndex (RegisterTableEntry->Index);
+if (DestinationRegisterTableList[Index].AllocatedSize != 0) {
+ RegisterTableEntry = AllocateCopyPool (
+DestinationRegisterTableList[Index].AllocatedSize,
+(VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry
+);
+ ASSERT (RegisterTableEntry != NULL);
+ DestinationRegisterTableList[Index].RegisterTableEntry =
(EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
+ //
+ // Go though all MSRs in register table to initialize MSR spin lock
+ //
+ for (Index1 = 0; Index1 <
DestinationRegisterTableList[Index].TableLength; Index1++,
RegisterTableEntry++) {
+if ((RegisterTableEntry->RegisterType == Msr) &&
(RegisterTableEntry->ValidBitLength < 64)) {
+ //
+ // Initialize MSR spin lock only for those MSRs need bit field
writing
+ //
+ InitMsrSpinLockByIndex (RegisterTableEntry->Index);
+}
}
}
-DestinationRegisterTableList[Index].RegisterTableEntry =
(EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
}
}
--
2.9.3.windows.2
___
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[edk2] [PATCH v5 10/11] UefiCpuPkg: Add NULL CPU Common Features Library instance
This NULL CPU common Features Library instance will register some CPU features
defined in Intel(R) 64 and IA-32 Architectures Software Developer's Manual,
Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR).
Add PCD PcdCpuClockModulationDutyCycle and PcdIsPowerOnReset consumed by NULL
CPU Common Features Library instance.
v2:
1. Using MSR_IA32_EFER to enable/disable NX feature instead of using
MSR_IA32_MISC_ENABLE.
2. Fix bug that SMX and VMX feature is swapped.
v3:
1. Add AesniGetConfigData() to get current register state.
v5:
1. Move MSR reading from AesniGetConfigData() to AesniSupport().
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c| 127 +++
UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 79 ++
.../Library/CpuCommonFeaturesLib/ClockModulation.c | 106 +++
.../CpuCommonFeaturesLib/CpuCommonFeatures.h | 867 +
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c| 227 ++
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 68 ++
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.uni | 25 +
UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c | 81 ++
.../Library/CpuCommonFeaturesLib/ExecuteDisable.c | 91 +++
.../Library/CpuCommonFeaturesLib/FastStrings.c | 52 ++
.../Library/CpuCommonFeaturesLib/FeatureControl.c | 314
.../CpuCommonFeaturesLib/LimitCpuIdMaxval.c| 82 ++
.../Library/CpuCommonFeaturesLib/MachineCheck.c| 231 ++
.../Library/CpuCommonFeaturesLib/MonitorMwait.c| 79 ++
.../Library/CpuCommonFeaturesLib/PendingBreak.c| 90 +++
UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 81 ++
UefiCpuPkg/UefiCpuPkg.dec | 11 +
17 files changed, 2611 insertions(+)
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
create mode 100644
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
create mode 100644
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
create mode 100644
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.uni
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
new file mode 100644
index 000..d889410
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
@@ -0,0 +1,127 @@
+/** @file
+ AESNI feature.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+AesniGetConfigData (
+ IN UINTN NumberOfProcessors
+ )
+{
+ UINT64*ConfigData;
+
+ ConfigData = AllocateZeroPool (sizeof (UINT64) * NumberOfProcessors);
+ ASSERT (ConfigData != NULL);
+ return ConfigData;
+}
+
+/**
+ Detects if AESNI feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the
REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+
[edk2] [PATCH v4 03/11] UefiCpuPkg/PiSmmCpuDxeSmm: Skip if AllocatedSize is 0
Needn't to copy register table if AllocatedSize is 0.
v4:
Fix potential uninitialized variable issue.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 27 +++
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 12efc1f..2588979 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -826,18 +826,21 @@ CopyRegisterTable (
CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus
* sizeof (CPU_REGISTER_TABLE));
for (Index = 0; Index < NumberOfCpus; Index++) {
-RegisterTableEntry = AllocatePool
(DestinationRegisterTableList[Index].AllocatedSize);
-ASSERT (RegisterTableEntry != NULL);
-CopyMem (RegisterTableEntry, (VOID
*)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry,
DestinationRegisterTableList[Index].AllocatedSize);
-//
-// Go though all MSRs in register table to initialize MSR spin lock
-//
-for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength;
Index1++, RegisterTableEntry++) {
- if ((RegisterTableEntry->RegisterType == Msr) &&
(RegisterTableEntry->ValidBitLength < 64)) {
-//
-// Initialize MSR spin lock only for those MSRs need bit field writing
-//
-InitMsrSpinLockByIndex (RegisterTableEntry->Index);
+RegisterTableEntry = NULL;
+if (DestinationRegisterTableList[Index].AllocatedSize != 0) {
+ RegisterTableEntry = AllocatePool
(DestinationRegisterTableList[Index].AllocatedSize);
+ ASSERT (RegisterTableEntry != NULL);
+ CopyMem (RegisterTableEntry, (VOID
*)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry,
DestinationRegisterTableList[Index].AllocatedSize);
+ //
+ // Go though all MSRs in register table to initialize MSR spin lock
+ //
+ for (Index1 = 0; Index1 <
DestinationRegisterTableList[Index].TableLength; Index1++,
RegisterTableEntry++) {
+if ((RegisterTableEntry->RegisterType == Msr) &&
(RegisterTableEntry->ValidBitLength < 64)) {
+ //
+ // Initialize MSR spin lock only for those MSRs need bit field
writing
+ //
+ InitMsrSpinLockByIndex (RegisterTableEntry->Index);
+}
}
}
DestinationRegisterTableList[Index].RegisterTableEntry =
(EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
--
2.9.3.windows.2
___
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[edk2] [PATCH v4 00/11] Add CPU features driver
This serial of patches will add CPU featuers initialization on boot time. 1) One new Register CPU Features Library and instances are added to provide the capability to register CPU feature's detect/initialize services. 2) One new NULL class CPU Commong Features Library instance is added to provide detect/initialize servcies of CPU features defined in SDM. 3) New CPU features PEI/DXE drivers are added to initialize CPU features in PEI phase or DXE phase, by consuming Register CPU Features Library. https://bugzilla.tianocore.org/show_bug.cgi?id=421 The whole updated UefiCpuPkg v4 could be accessed at https://github.com/JeffFan/edk2/tree/CpuFeaturesV4/UefiCpuPkg for review. v2: #9: Format debug messages. #10: 1. Using MSR_IA32_EFER to enable/disable NX feature instead of using MSR_IA32_MISC_ENABLE. 2. Fix bug that SMX and VMX feature is swapped. v3: #9: Trim white space at end of line. #10: Add AesniGetConfigData() to get current register state. v4: #3, #8, #9: Fix GCC complied issue. Cc: Feng Tian <feng.t...@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff....@intel.com> Jeff Fan (11): UefiCpuPkg/AcpiCpuData: Update RegisterTableEntry type UefiCpuPkg/CpuS3DataDxe: Consume the existing PcdCpuS3DataAddress UefiCpuPkg/PiSmmCpuDxeSmm: Skip if AllocatedSize is 0 UefiCpuPkg/Msr: Add CPUID signature check MACROs UefiCpuPkg/UefiCpuPkg.dec: Add a set of CPU features PCDs UefiCpuPkg: Add GUID gEdkiiCpuFeaturesSetDoneGuid UefiCpuPkg: Add GUID gEdkiiCpuFeaturesInitDoneGuid UefiCpuPkg/Include/Library: Add Register CPU Features Library UefiCpuPkg: Add PEI/DXE Register CPU Features Library instances UefiCpuPkg: Add NULL CPU Common Features Library instance UefiCpuPkg: Add CPU Features PEI/DXE drivers UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c| 122 +++ UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.inf | 53 ++ UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.uni | 22 + UefiCpuPkg/CpuFeatures/CpuFeaturesDxeExtra.uni | 20 + UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c| 75 ++ UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf | 49 ++ UefiCpuPkg/CpuFeatures/CpuFeaturesPei.uni | 22 + UefiCpuPkg/CpuFeatures/CpuFeaturesPeiExtra.uni | 20 + UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c| 56 +- UefiCpuPkg/Include/AcpiCpuData.h | 6 +- UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h | 26 + UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h | 26 + .../Include/Library/RegisterCpuFeaturesLib.h | 516 UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 22 +- UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 21 +- UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 19 +- UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 20 +- UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 21 +- UefiCpuPkg/Include/Register/Msr/P6Msr.h| 23 +- UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 15 +- UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 20 +- UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 19 +- UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h| 22 +- UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 19 +- UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 19 +- UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 19 +- UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h| 18 +- UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 18 +- UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c| 124 +++ UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 79 ++ .../Library/CpuCommonFeaturesLib/ClockModulation.c | 106 +++ .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 867 + .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c| 227 ++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 68 ++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.uni | 25 + UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c | 81 ++ .../Library/CpuCommonFeaturesLib/ExecuteDisable.c | 91 +++ .../Library/CpuCommonFeaturesLib/FastStrings.c | 52 ++ .../Library/CpuCommonFeaturesLib/FeatureControl.c | 314 .../CpuCommonFeaturesLib/LimitCpuIdMaxval.c| 82 ++ .../Library/CpuCommonFeaturesLib/MachineCheck.c| 231 ++ .../Library/CpuCommonFeaturesLib/MonitorMwait.c| 79 ++ .../Library/CpuCommonFeaturesLib/PendingBreak.c| 90 +++ UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 81 ++ .../RegisterCpuFeaturesLib/CpuFeatures
[edk2] [PATCH v4 08/11] UefiCpuPkg/Include/Library: Add Register CPU Features Library
Register CPU Features Library is used to register/manage/program CPU features.
NULL CPU features library instance could consume it register CPU features
functions.
CPU Feature module could consume this library to detect/analysis/program CPU
features on BSP/APs.
v4:
Fix GCC build issue.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../Include/Library/RegisterCpuFeaturesLib.h | 516 +
UefiCpuPkg/UefiCpuPkg.dec | 5 +
2 files changed, 521 insertions(+)
create mode 100644 UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
new file mode 100644
index 000..42eb3b2
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
@@ -0,0 +1,516 @@
+/** @file
+ Register CPU Features Library to register and manage CPU features.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __REGISTER_CPU_FEATURES_LIB_H__
+#define __REGISTER_CPU_FEATURES_LIB_H__
+
+#include
+#include
+#include
+
+///
+/// Defines used to identify a CPU feature. The lower 16-bits are used to
+/// identify a unique CPU feature and the value represents a bit number in
+/// a bit mask. The upper 16-bits are bit mask values that are used as
+/// modifiers of a CPU feature. When used in a list, the define value
+/// CPU_FEATURE_END is used to terminate a list of CPU feature values.
+/// @{
+#define CPU_FEATURE_AESNI 0
+#define CPU_FEATURE_TURBO_MODE 1
+#define CPU_FEATURE_MWAIT 2
+#define CPU_FEATURE_ACPI3
+#define CPU_FEATURE_EIST4
+#define CPU_FEATURE_XD 5
+#define CPU_FEATURE_FASTSTRINGS 6
+#define CPU_FEATURE_VMX 7
+#define CPU_FEATURE_SMX 8
+#define CPU_FEATURE_SENTER 9
+#define CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER 10
+#define CPU_FEATURE_LIMIT_CPUID_MAX_VAL 11
+#define CPU_FEATURE_MCE 12
+#define CPU_FEATURE_MCA 13
+#define CPU_FEATURE_MCG_CTL 14
+#define CPU_FEATURE_PENDING_BREAK 15
+#define CPU_FEATURE_C1E 16
+#define CPU_FEATURE_C1_AUTO_DEMOTION17
+#define CPU_FEATURE_C3_AUTO_DEMOTION18
+#define CPU_FEATURE_C1_AUTO_UNDEMOTION 19
+#define CPU_FEATURE_C3_AUTO_UNDEMOTION 20
+#define CPU_FEATURE_C_STATE 21
+#define CPU_FEATURE_TM 22
+#define CPU_FEATURE_TM2 23
+#define CPU_FEATURE_X2APIC 24
+#define CPU_FEATURE_RESERVED_25 25
+#define CPU_FEATURE_RESERVED_26 26
+#define CPU_FEATURE_RESERVED_27 27
+#define CPU_FEATURE_RESERVED_28 28
+#define CPU_FEATURE_RESERVED_29 29
+#define CPU_FEATURE_RESERVED_30 30
+#define CPU_FEATURE_RESERVED_31 31
+
+#define CPU_FEATURE_L2_PREFETCHER (32+0)
+#define CPU_FEATURE_L1_DATA_PREFETCHER (32+1)
+#define CPU_FEATURE_HARDWARE_PREFETCHER (32+2)
+#define CPU_FEATURE_ADJACENT_CACHE_LINE_PREFETCH(32+3)
+#define CPU_FEATURE_DCU_PREFETCHER (32+4)
+#define CPU_FEATURE_IP_PREFETCHER (32+5)
+#define CPU_FEATURE_MLC_STREAMER_PREFETCHER (32+6)
+#define CPU_FEATURE_MLC_SPATIAL_PREFETCHER (32+7)
+#define CPU_FEATURE_THREE_STRICK_COUNTER(32+8)
+#define CPU_FEATURE_APIC_TPR_UPDATE_MESSAGE (32+9)
+#define CPU_FEATURE_ENERGY_PERFORMANCE_BIAS (32+10)
+
+#define CPU_FEATURE_BEFORE_ALL BIT27
+#define CPU_FEATURE_AFTER_ALL BIT28
+#define CPU_FEATURE_BEFORE BIT29
+#define CPU_FEATURE_AFTER BIT30
+#define CPU_FEATURE_END MAX_UINT32
+/// @}
+
+///
+/// CPU Information passed into the SupportFunc and InitializeFunc of the
+/// RegisterCpuFeature() library function. This st
[edk2] [PATCH v4 09/11] UefiCpuPkg: Add PEI/DXE Register CPU Features Library instances
PEI Register CPU Features Library instance is used to register/manager/program
CPU features on PEI phase.
DXE Register CPU Features Library instance is used to register/manager/program
CPU features on DXE phase.
v2:
Format debug messages.
v3:
Trim white space at end of line.
v4:
Remove unused local variable.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 745
.../DxeRegisterCpuFeaturesLib.c| 266 +++
.../DxeRegisterCpuFeaturesLib.inf | 62 ++
.../PeiRegisterCpuFeaturesLib.c| 390 +++
.../PeiRegisterCpuFeaturesLib.inf | 64 ++
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 193 ++
.../RegisterCpuFeaturesDxe.uni | 22 +
.../RegisterCpuFeaturesLib.c | 770 +
UefiCpuPkg/UefiCpuPkg.dsc | 6 +-
9 files changed, 2517 insertions(+), 1 deletion(-)
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.inf
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.inf
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesDxe.uni
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
new file mode 100644
index 000..d879591
--- /dev/null
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -0,0 +1,745 @@
+/** @file
+ CPU Features Initialize functions.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "RegisterCpuFeatures.h"
+
+/**
+ Worker function to save PcdCpuFeaturesCapability.
+
+ @param[in] SupportedFeatureMask The pointer to CPU feature bits mask buffer
+*/
+VOID
+SetCapabilityPcd (
+ IN UINT8 *SupportedFeatureMask
+ )
+{
+ EFI_STATUS Status;
+ UINTN BitMaskSize;
+
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesCapability);
+ Status = PcdSetPtrS (PcdCpuFeaturesCapability, ,
SupportedFeatureMask);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Worker function to save PcdCpuFeaturesSetting.
+
+ @param[in] SupportedFeatureMask The pointer to CPU feature bits mask buffer
+**/
+VOID
+SetSettingPcd (
+ IN UINT8 *SupportedFeatureMask
+ )
+{
+ EFI_STATUS Status;
+ UINTN BitMaskSize;
+
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesSetting);
+ Status = PcdSetPtrS (PcdCpuFeaturesSetting, ,
SupportedFeatureMask);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Worker function to get PcdCpuFeaturesSupport.
+
+ @return The pointer to CPU feature bits mask buffer.
+**/
+UINT8 *
+GetSupportPcds (
+ VOID
+ )
+{
+ UINTN BitMaskSize;
+ UINT8 *SupportBitMask;
+
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesSupport);
+ SupportBitMask = AllocateZeroPool (BitMaskSize);
+ SupportBitMask = (UINT8 *) PcdGetPtr (PcdCpuFeaturesSupport);
+
+ return SupportBitMask;
+}
+
+/**
+ Worker function to get PcdCpuFeaturesUserConfiguration.
+
+ @return The pointer to CPU feature bits mask buffer.
+**/
+UINT8 *
+GetConfigurationPcds (
+ VOID
+ )
+{
+ UINTN BitMaskSize;
+ UINT8 *SupportBitMask;
+
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesUserConfiguration);
+ SupportBitMask = AllocateZeroPool (BitMaskSize);
+ SupportBitMask = (UINT8 *) PcdGetPtr (PcdCpuFeaturesUserConfiguration);
+
+ return SupportBitMask;
+}
+
+/**
+ Collects CPU type and feature information.
+
+ @param[in, out] CpuInfo The pointer to CPU feature information
+**/
+VOID
+FillProcessorInfo (
+ IN OUT REGISTER_CPU_FEATURE_INFORMATION*CpuInfo
+ )
+{
+ CPUID_VERSION_INFO_EAX Eax;
+ CPUID_VERSION_INFO_ECX Ecx;
+ CPUID_VERSION_INFO_EDX Edx;
+ UINT32
[edk2] [PATCH v3 09/11] UefiCpuPkg: Add PEI/DXE Register CPU Features Library instances
PEI Register CPU Features Library instance is used to register/manager/program
CPU features on PEI phase.
DXE Register CPU Features Library instance is used to register/manager/program
CPU features on DXE phase.
v2:
Format debug messages.
v3:
Trim white space at end of line.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 747
.../DxeRegisterCpuFeaturesLib.c| 266 +++
.../DxeRegisterCpuFeaturesLib.inf | 62 ++
.../PeiRegisterCpuFeaturesLib.c| 390 +++
.../PeiRegisterCpuFeaturesLib.inf | 64 ++
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 193 ++
.../RegisterCpuFeaturesDxe.uni | 22 +
.../RegisterCpuFeaturesLib.c | 770 +
UefiCpuPkg/UefiCpuPkg.dsc | 6 +-
9 files changed, 2519 insertions(+), 1 deletion(-)
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.inf
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.inf
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesDxe.uni
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
new file mode 100644
index 000..a8d628a
--- /dev/null
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -0,0 +1,747 @@
+/** @file
+ CPU Features Initialize functions.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "RegisterCpuFeatures.h"
+
+/**
+ Worker function to save PcdCpuFeaturesCapability.
+
+ @param[in] SupportedFeatureMask The pointer to CPU feature bits mask buffer
+*/
+VOID
+SetCapabilityPcd (
+ IN UINT8 *SupportedFeatureMask
+ )
+{
+ EFI_STATUS Status;
+ UINTN BitMaskSize;
+
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesCapability);
+ Status = PcdSetPtrS (PcdCpuFeaturesCapability, ,
SupportedFeatureMask);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Worker function to save PcdCpuFeaturesSetting.
+
+ @param[in] SupportedFeatureMask The pointer to CPU feature bits mask buffer
+**/
+VOID
+SetSettingPcd (
+ IN UINT8 *SupportedFeatureMask
+ )
+{
+ EFI_STATUS Status;
+ UINTN BitMaskSize;
+
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesSetting);
+ Status = PcdSetPtrS (PcdCpuFeaturesSetting, ,
SupportedFeatureMask);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Worker function to get PcdCpuFeaturesSupport.
+
+ @return The pointer to CPU feature bits mask buffer.
+**/
+UINT8 *
+GetSupportPcds (
+ VOID
+ )
+{
+ UINTN BitMaskSize;
+ UINT8 *SupportBitMask;
+
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesSupport);
+ SupportBitMask = AllocateZeroPool (BitMaskSize);
+ SupportBitMask = (UINT8 *) PcdGetPtr (PcdCpuFeaturesSupport);
+
+ return SupportBitMask;
+}
+
+/**
+ Worker function to get PcdCpuFeaturesUserConfiguration.
+
+ @return The pointer to CPU feature bits mask buffer.
+**/
+UINT8 *
+GetConfigurationPcds (
+ VOID
+ )
+{
+ UINTN BitMaskSize;
+ UINT8 *SupportBitMask;
+
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesUserConfiguration);
+ SupportBitMask = AllocateZeroPool (BitMaskSize);
+ SupportBitMask = (UINT8 *) PcdGetPtr (PcdCpuFeaturesUserConfiguration);
+
+ return SupportBitMask;
+}
+
+/**
+ Collects CPU type and feature information.
+
+ @param[in, out] CpuInfo The pointer to CPU feature information
+**/
+VOID
+FillProcessorInfo (
+ IN OUT REGISTER_CPU_FEATURE_INFORMATION*CpuInfo
+ )
+{
+ CPUID_VERSION_INFO_EAX Eax;
+ CPUID_VERSION_INFO_ECX Ecx;
+ CPUID_VERSION_INFO_EDX Edx;
+ UINT32 DisplayedFamily;
+ UINT32
[edk2] [PATCH v3 10/11] UefiCpuPkg: Add NULL CPU Common Features Library instance
This NULL CPU common Features Library instance will register some CPU features
defined in Intel(R) 64 and IA-32 Architectures Software Developer's Manual,
Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR).
Add PCD PcdCpuClockModulationDutyCycle and PcdIsPowerOnReset consumed by NULL
CPU Common Features Library instance.
v2:
1. Using MSR_IA32_EFER to enable/disable NX feature instead of using
MSR_IA32_MISC_ENABLE.
2. Fix bug that SMX and VMX feature is swapped.
v3:
1. Add AesniGetConfigData() to get current register state.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c| 124 +++
UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 79 ++
.../Library/CpuCommonFeaturesLib/ClockModulation.c | 106 +++
.../CpuCommonFeaturesLib/CpuCommonFeatures.h | 867 +
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c| 227 ++
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 68 ++
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.uni | 25 +
UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c | 81 ++
.../Library/CpuCommonFeaturesLib/ExecuteDisable.c | 91 +++
.../Library/CpuCommonFeaturesLib/FastStrings.c | 52 ++
.../Library/CpuCommonFeaturesLib/FeatureControl.c | 314
.../CpuCommonFeaturesLib/LimitCpuIdMaxval.c| 82 ++
.../Library/CpuCommonFeaturesLib/MachineCheck.c| 231 ++
.../Library/CpuCommonFeaturesLib/MonitorMwait.c| 79 ++
.../Library/CpuCommonFeaturesLib/PendingBreak.c| 90 +++
UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 81 ++
UefiCpuPkg/UefiCpuPkg.dec | 11 +
17 files changed, 2608 insertions(+)
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
create mode 100644
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
create mode 100644
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
create mode 100644
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.uni
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
new file mode 100644
index 000..b0f30df
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
@@ -0,0 +1,124 @@
+/** @file
+ AESNI feature.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Prepares for the data used by CPU feature detection and initialization.
+
+ @param[in] NumberOfProcessors The number of CPUs in the platform.
+
+ @return Pointer to a buffer of CPU related configuration data.
+
+ @note This service could be called by BSP only.
+**/
+VOID *
+EFIAPI
+AesniGetConfigData (
+ IN UINTN NumberOfProcessors
+ )
+{
+ UINT64*ConfigData;
+
+ ConfigData = AllocateZeroPool (sizeof (UINT64) * NumberOfProcessors);
+ ConfigData[NumberOfProcessors] = AsmReadMsr64
(MSR_SANDY_BRIDGE_FEATURE_CONFIG);
+ ASSERT (ConfigData != NULL);
+ return ConfigData;
+}
+
+/**
+ Detects if AESNI feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the
REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+
[edk2] [PATCH v3 00/11] Add CPU features driver
This serial of patches will add CPU featuers initialization on boot time. 1) One new Register CPU Features Library and instances are added to provide the capability to register CPU feature's detect/initialize services. 2) One new NULL class CPU Commong Features Library instance is added to provide detect/initialize servcies of CPU features defined in SDM. 3) New CPU features PEI/DXE drivers are added to initialize CPU features in PEI phase or DXE phase, by consuming Register CPU Features Library. https://bugzilla.tianocore.org/show_bug.cgi?id=421 The whole updated UefiCpuPkg v3 could be accessed at https://github.com/JeffFan/edk2/tree/CpuFeaturesV3/UefiCpuPkg for review. v2: #9: Format debug messages. #10: 1. Using MSR_IA32_EFER to enable/disable NX feature instead of using MSR_IA32_MISC_ENABLE. 2. Fix bug that SMX and VMX feature is swapped. v3: #9: Trim white space at end of line. #10: Add AesniGetConfigData() to get current register state. Cc: Feng Tian <feng.t...@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff....@intel.com> Jeff Fan (11): UefiCpuPkg/AcpiCpuData: Update RegisterTableEntry type UefiCpuPkg/CpuS3DataDxe: Consume the existing PcdCpuS3DataAddress UefiCpuPkg/PiSmmCpuDxeSmm: Skip if AllocatedSize is 0 UefiCpuPkg/Msr: Add CPUID signature check MACROs UefiCpuPkg/UefiCpuPkg.dec: Add a set of CPU features PCDs UefiCpuPkg: Add GUID gEdkiiCpuFeaturesSetDoneGuid UefiCpuPkg: Add GUID gEdkiiCpuFeaturesInitDoneGuid UefiCpuPkg/Include/Library: Add Register CPU Features Library UefiCpuPkg: Add PEI/DXE Register CPU Features Library instances UefiCpuPkg: Add NULL CPU Common Features Library instance UefiCpuPkg: Add CPU Features PEI/DXE drivers UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c| 122 +++ UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.inf | 53 ++ UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.uni | 22 + UefiCpuPkg/CpuFeatures/CpuFeaturesDxeExtra.uni | 20 + UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c| 75 ++ UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf | 49 ++ UefiCpuPkg/CpuFeatures/CpuFeaturesPei.uni | 22 + UefiCpuPkg/CpuFeatures/CpuFeaturesPeiExtra.uni | 20 + UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c| 56 +- UefiCpuPkg/Include/AcpiCpuData.h | 6 +- UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h | 26 + UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h | 26 + .../Include/Library/RegisterCpuFeaturesLib.h | 516 UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 22 +- UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 21 +- UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 19 +- UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 20 +- UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 21 +- UefiCpuPkg/Include/Register/Msr/P6Msr.h| 23 +- UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 15 +- UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 20 +- UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 19 +- UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h| 22 +- UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 19 +- UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 19 +- UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 19 +- UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h| 18 +- UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 18 +- UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c| 124 +++ UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 79 ++ .../Library/CpuCommonFeaturesLib/ClockModulation.c | 106 +++ .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 867 + .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c| 227 ++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 68 ++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.uni | 25 + UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c | 81 ++ .../Library/CpuCommonFeaturesLib/ExecuteDisable.c | 91 +++ .../Library/CpuCommonFeaturesLib/FastStrings.c | 52 ++ .../Library/CpuCommonFeaturesLib/FeatureControl.c | 314 .../CpuCommonFeaturesLib/LimitCpuIdMaxval.c| 82 ++ .../Library/CpuCommonFeaturesLib/MachineCheck.c| 231 ++ .../Library/CpuCommonFeaturesLib/MonitorMwait.c| 79 ++ .../Library/CpuCommonFeaturesLib/PendingBreak.c| 90 +++ UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 81 ++ .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 747 ++ .../DxeRegisterCpuFeaturesLib.c
[edk2] [PATCH v2 09/11] UefiCpuPkg: Add PEI/DXE Register CPU Features Library instances
PEI Register CPU Features Library instance is used to register/manager/program
CPU features on PEI phase.
DXE Register CPU Features Library instance is used to register/manager/program
CPU features on DXE phase.
v2:
Format debug messages.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 747
.../DxeRegisterCpuFeaturesLib.c| 266 +++
.../DxeRegisterCpuFeaturesLib.inf | 62 ++
.../PeiRegisterCpuFeaturesLib.c| 390 +++
.../PeiRegisterCpuFeaturesLib.inf | 64 ++
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 193 ++
.../RegisterCpuFeaturesDxe.uni | 22 +
.../RegisterCpuFeaturesLib.c | 770 +
UefiCpuPkg/UefiCpuPkg.dsc | 6 +-
9 files changed, 2519 insertions(+), 1 deletion(-)
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.inf
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.inf
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesDxe.uni
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
new file mode 100644
index 000..d201239
--- /dev/null
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -0,0 +1,747 @@
+/** @file
+ CPU Features Initialize functions.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "RegisterCpuFeatures.h"
+
+/**
+ Worker function to save PcdCpuFeaturesCapability.
+
+ @param[in] SupportedFeatureMask The pointer to CPU feature bits mask buffer
+*/
+VOID
+SetCapabilityPcd (
+ IN UINT8 *SupportedFeatureMask
+ )
+{
+ EFI_STATUS Status;
+ UINTN BitMaskSize;
+
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesCapability);
+ Status = PcdSetPtrS (PcdCpuFeaturesCapability, ,
SupportedFeatureMask);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Worker function to save PcdCpuFeaturesSetting.
+
+ @param[in] SupportedFeatureMask The pointer to CPU feature bits mask buffer
+**/
+VOID
+SetSettingPcd (
+ IN UINT8 *SupportedFeatureMask
+ )
+{
+ EFI_STATUS Status;
+ UINTN BitMaskSize;
+
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesSetting);
+ Status = PcdSetPtrS (PcdCpuFeaturesSetting, ,
SupportedFeatureMask);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Worker function to get PcdCpuFeaturesSupport.
+
+ @return The pointer to CPU feature bits mask buffer.
+**/
+UINT8 *
+GetSupportPcds (
+ VOID
+ )
+{
+ UINTN BitMaskSize;
+ UINT8 *SupportBitMask;
+
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesSupport);
+ SupportBitMask = AllocateZeroPool (BitMaskSize);
+ SupportBitMask = (UINT8 *) PcdGetPtr (PcdCpuFeaturesSupport);
+
+ return SupportBitMask;
+}
+
+/**
+ Worker function to get PcdCpuFeaturesUserConfiguration.
+
+ @return The pointer to CPU feature bits mask buffer.
+**/
+UINT8 *
+GetConfigurationPcds (
+ VOID
+ )
+{
+ UINTN BitMaskSize;
+ UINT8 *SupportBitMask;
+
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesUserConfiguration);
+ SupportBitMask = AllocateZeroPool (BitMaskSize);
+ SupportBitMask = (UINT8 *) PcdGetPtr (PcdCpuFeaturesUserConfiguration);
+
+ return SupportBitMask;
+}
+
+/**
+ Collects CPU type and feature information.
+
+ @param[in, out] CpuInfo The pointer to CPU feature information
+**/
+VOID
+FillProcessorInfo (
+ IN OUT REGISTER_CPU_FEATURE_INFORMATION*CpuInfo
+ )
+{
+ CPUID_VERSION_INFO_EAX Eax;
+ CPUID_VERSION_INFO_ECX Ecx;
+ CPUID_VERSION_INFO_EDX Edx;
+ UINT32 DisplayedFamily;
+ UINT32
[edk2] [PATCH v2 10/11] UefiCpuPkg: Add NULL CPU Common Features Library instance
This NULL CPU common Features Library instance will register some CPU features
defined in Intel(R) 64 and IA-32 Architectures Software Developer's Manual,
Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR).
Add PCD PcdCpuClockModulationDutyCycle and PcdIsPowerOnReset consumed by NULL
CPU Common Features Library instance.
v2:
1. Using MSR_IA32_EFER to enable/disable NX feature instead of using
MSR_IA32_MISC_ENABLE.
2. Fix bug that SMX and VMX feature is swapped.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c| 94 +++
UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 79 ++
.../Library/CpuCommonFeaturesLib/ClockModulation.c | 106 +++
.../CpuCommonFeaturesLib/CpuCommonFeatures.h | 852 +
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c| 227 ++
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 68 ++
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.uni | 25 +
UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c | 81 ++
.../Library/CpuCommonFeaturesLib/ExecuteDisable.c | 91 +++
.../Library/CpuCommonFeaturesLib/FastStrings.c | 52 ++
.../Library/CpuCommonFeaturesLib/FeatureControl.c | 314
.../CpuCommonFeaturesLib/LimitCpuIdMaxval.c| 82 ++
.../Library/CpuCommonFeaturesLib/MachineCheck.c| 231 ++
.../Library/CpuCommonFeaturesLib/MonitorMwait.c| 79 ++
.../Library/CpuCommonFeaturesLib/PendingBreak.c| 90 +++
UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 81 ++
UefiCpuPkg/UefiCpuPkg.dec | 11 +
17 files changed, 2563 insertions(+)
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
create mode 100644
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
create mode 100644
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
create mode 100644
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.uni
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
new file mode 100644
index 000..6aebf0d
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
@@ -0,0 +1,94 @@
+/** @file
+ AESNI feature.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Detects if AESNI feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the
REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE AESNI feature is supported.
+ @retval FALSEAESNI feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+AesniSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ if (IS_SANDY_BRIDGE_PROCESSOR (CpuInfo->DisplayFamily,
CpuInfo->DisplayModel) ||
+ IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)
||
+
[edk2] [PATCH v2 00/11] Add CPU features driver
This serial of patches will add CPU featuers initialization on boot time. 1) One new Register CPU Features Library and instances are added to provide the capability to register CPU feature's detect/initialize services. 2) One new NULL class CPU Commong Features Library instance is added to provide detect/initialize servcies of CPU features defined in SDM. 3) New CPU features PEI/DXE drivers are added to initialize CPU features in PEI phase or DXE phase, by consuming Register CPU Features Library. https://bugzilla.tianocore.org/show_bug.cgi?id=421 The whole updated UefiCpuPkg v2 could be accessed at https://github.com/JeffFan/edk2/tree/CpuFeaturesV2/UefiCpuPkg for review. v2: #9: Format debug messages. #10: 1. Using MSR_IA32_EFER to enable/disable NX feature instead of using MSR_IA32_MISC_ENABLE. 2. Fix bug that SMX and VMX feature is swapped. Cc: Feng Tian <feng.t...@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff....@intel.com> Jeff Fan (11): UefiCpuPkg/AcpiCpuData: Update RegisterTableEntry type UefiCpuPkg/CpuS3DataDxe: Consume the existing PcdCpuS3DataAddress UefiCpuPkg/PiSmmCpuDxeSmm: Skip if AllocatedSize is 0 UefiCpuPkg/Msr: Add CPUID signature check MACROs UefiCpuPkg/UefiCpuPkg.dec: Add a set of CPU features PCDs UefiCpuPkg: Add GUID gEdkiiCpuFeaturesSetDoneGuid UefiCpuPkg: Add GUID gEdkiiCpuFeaturesInitDoneGuid UefiCpuPkg/Include/Library: Add Register CPU Features Library UefiCpuPkg: Add PEI/DXE Register CPU Features Library instances UefiCpuPkg: Add NULL CPU Common Features Library instance UefiCpuPkg: Add CPU Features PEI/DXE drivers UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c| 122 +++ UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.inf | 53 ++ UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.uni | 22 + UefiCpuPkg/CpuFeatures/CpuFeaturesDxeExtra.uni | 20 + UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c| 75 ++ UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf | 49 ++ UefiCpuPkg/CpuFeatures/CpuFeaturesPei.uni | 22 + UefiCpuPkg/CpuFeatures/CpuFeaturesPeiExtra.uni | 20 + UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c| 56 +- UefiCpuPkg/Include/AcpiCpuData.h | 6 +- UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h | 26 + UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h | 26 + .../Include/Library/RegisterCpuFeaturesLib.h | 516 + UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 22 +- UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 21 +- UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 19 +- UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 20 +- UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 21 +- UefiCpuPkg/Include/Register/Msr/P6Msr.h| 23 +- UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 15 +- UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 20 +- UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 19 +- UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h| 22 +- UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 19 +- UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 19 +- UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 19 +- UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h| 18 +- UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 18 +- UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c| 94 +++ UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 79 ++ .../Library/CpuCommonFeaturesLib/ClockModulation.c | 106 +++ .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 852 + .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c| 227 ++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 68 ++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.uni | 25 + UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c | 81 ++ .../Library/CpuCommonFeaturesLib/ExecuteDisable.c | 91 +++ .../Library/CpuCommonFeaturesLib/FastStrings.c | 52 ++ .../Library/CpuCommonFeaturesLib/FeatureControl.c | 314 .../CpuCommonFeaturesLib/LimitCpuIdMaxval.c| 82 ++ .../Library/CpuCommonFeaturesLib/MachineCheck.c| 231 ++ .../Library/CpuCommonFeaturesLib/MonitorMwait.c| 79 ++ .../Library/CpuCommonFeaturesLib/PendingBreak.c| 90 +++ UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 81 ++ .../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 747 ++ .../DxeRegisterCpuFeaturesLib.c| 266 +++ .../DxeRegisterCpuFeaturesLib.inf | 62 ++ .../PeiRegist
[edk2] [PATCH] UefiCpuPkg/CpuDxe: Remove MSR_IA32_MISC_ENABLE check
The architectural MSR MSR_IA32_MISC_ENABLE is not supported by AMD processors.
Because reading CPUID.8001H:EDK[20] is enough to check if XD feature is
supported or not, we just remove checking MSR_IA32_MISC_ENABLE(0x1A0).
Cc: Anthony PERARD <anthony.per...@citrix.com>
Cc: Jiewen Yao <jiewen@intel.com>
Cc: Feng Tian <feng.t...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/CpuDxe/CpuPageTable.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTable.c
index 65f607a..ab664b4 100644
--- a/UefiCpuPkg/CpuDxe/CpuPageTable.c
+++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c
@@ -193,12 +193,9 @@ GetCurrentPagingContext (
AsmCpuid (0x8001, NULL, NULL, NULL, );
if ((RegEdx & BIT20) != 0) {
// XD supported
- if ((AsmReadMsr64 (0x01A0) & BIT34) == 0) {
-// XD enabled
-if ((AsmReadMsr64 (0xC080) & BIT11) != 0) {
- // XD activated
- PagingContext->ContextData.Ia32.Attributes |=
PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED;
-}
+ if ((AsmReadMsr64 (0xC080) & BIT11) != 0) {
+// XD activated
+PagingContext->ContextData.Ia32.Attributes |=
PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED;
}
}
if ((RegEdx & BIT26) != 0) {
--
2.9.3.windows.2
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[edk2] [PATCH] UefiCpuPkg/CpuDxe: Remove MSR_IA32_MISC_ENABLE check
The architectural MSR MSR_IA32_MISC_ENABLE is not supported by AMD processors.
Because reading CPUID.8001H:EDK[20] is enough to check if XD feature is
supported or not, we just remove checking MSR_IA32_MISC_ENABLE(0x1A0).
Cc: Anthony PERARD <anthony.per...@citrix.com>
Cc: Jiewen Yao <jiewen@citrix.com>
Cc: Feng Tian <feng.t...@citrix.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/CpuDxe/CpuPageTable.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTable.c
index 65f607a..ab664b4 100644
--- a/UefiCpuPkg/CpuDxe/CpuPageTable.c
+++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c
@@ -193,12 +193,9 @@ GetCurrentPagingContext (
AsmCpuid (0x8001, NULL, NULL, NULL, );
if ((RegEdx & BIT20) != 0) {
// XD supported
- if ((AsmReadMsr64 (0x01A0) & BIT34) == 0) {
-// XD enabled
-if ((AsmReadMsr64 (0xC080) & BIT11) != 0) {
- // XD activated
- PagingContext->ContextData.Ia32.Attributes |=
PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED;
-}
+ if ((AsmReadMsr64 (0xC080) & BIT11) != 0) {
+// XD activated
+PagingContext->ContextData.Ia32.Attributes |=
PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED;
}
}
if ((RegEdx & BIT26) != 0) {
--
2.9.3.windows.2
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[edk2] [PATCH 02/11] UefiCpuPkg/CpuS3DataDxe: Consume the existing PcdCpuS3DataAddress
If PCD PcdCpuS3DataAddress is set before, CpuS3DataDxe should get RegisterTable
and PreSmmRegisterTable from existing PCD pointed buffer and needn't to allocate
new buffer for RegisterTable and PreSmmRegisterTable.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c | 54 ++---
1 file changed, 33 insertions(+), 21 deletions(-)
diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
index 07c7102..dccb406 100644
--- a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
+++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
@@ -160,12 +160,18 @@ CpuS3DataInitialize (
VOID *Gdt;
VOID *Idt;
EFI_EVENT Event;
+ ACPI_CPU_DATA *OldAcpiCpuData;
if (!PcdGetBool (PcdAcpiS3Enable)) {
return EFI_UNSUPPORTED;
}
//
+ // Set PcdCpuS3DataAddress to the base address of the ACPI_CPU_DATA structure
+ //
+ OldAcpiCpuData = (ACPI_CPU_DATA *) (UINTN) PcdGet64 (PcdCpuS3DataAddress);
+
+ //
// Allocate ACPI NVS memory below 4G memory for use on ACPI S3 resume.
//
AcpiCpuDataEx = AllocateAcpiNvsMemoryBelow4G (sizeof (ACPI_CPU_DATA_EX));
@@ -229,32 +235,38 @@ CpuS3DataInitialize (
AcpiCpuDataEx->GdtrProfile.Base = (UINTN)Gdt;
AcpiCpuDataEx->IdtrProfile.Base = (UINTN)Idt;
- //
- // Allocate buffer for empty RegisterTable and PreSmmInitRegisterTable for
all CPUs
- //
- TableSize = 2 * NumberOfCpus * sizeof (CPU_REGISTER_TABLE);
- RegisterTable = (CPU_REGISTER_TABLE *)AllocateAcpiNvsMemoryBelow4G
(TableSize);
- ASSERT (RegisterTable != NULL);
- for (Index = 0; Index < NumberOfCpus; Index++) {
-Status = MpServices->GetProcessorInfo (
+ if (OldAcpiCpuData != NULL) {
+AcpiCpuData->RegisterTable = OldAcpiCpuData->RegisterTable;
+AcpiCpuData->PreSmmInitRegisterTable =
OldAcpiCpuData->PreSmmInitRegisterTable;
+ } else {
+//
+// Allocate buffer for empty RegisterTable and PreSmmInitRegisterTable for
all CPUs
+//
+TableSize = 2 * NumberOfCpus * sizeof (CPU_REGISTER_TABLE);
+RegisterTable = (CPU_REGISTER_TABLE *)AllocateAcpiNvsMemoryBelow4G
(TableSize);
+ASSERT (RegisterTable != NULL);
+
+for (Index = 0; Index < NumberOfCpus; Index++) {
+ Status = MpServices->GetProcessorInfo (
MpServices,
Index,
);
-ASSERT_EFI_ERROR (Status);
-
-RegisterTable[Index].InitialApicId =
(UINT32)ProcessorInfoBuffer.ProcessorId;
-RegisterTable[Index].TableLength= 0;
-RegisterTable[Index].AllocatedSize = 0;
-RegisterTable[Index].RegisterTableEntry = 0;
-
-RegisterTable[NumberOfCpus + Index].InitialApicId =
(UINT32)ProcessorInfoBuffer.ProcessorId;
-RegisterTable[NumberOfCpus + Index].TableLength= 0;
-RegisterTable[NumberOfCpus + Index].AllocatedSize = 0;
-RegisterTable[NumberOfCpus + Index].RegisterTableEntry = 0;
+ ASSERT_EFI_ERROR (Status);
+
+ RegisterTable[Index].InitialApicId =
(UINT32)ProcessorInfoBuffer.ProcessorId;
+ RegisterTable[Index].TableLength= 0;
+ RegisterTable[Index].AllocatedSize = 0;
+ RegisterTable[Index].RegisterTableEntry = 0;
+
+ RegisterTable[NumberOfCpus + Index].InitialApicId =
(UINT32)ProcessorInfoBuffer.ProcessorId;
+ RegisterTable[NumberOfCpus + Index].TableLength= 0;
+ RegisterTable[NumberOfCpus + Index].AllocatedSize = 0;
+ RegisterTable[NumberOfCpus + Index].RegisterTableEntry = 0;
+}
+AcpiCpuData->RegisterTable =
(EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTable;
+AcpiCpuData->PreSmmInitRegisterTable =
(EFI_PHYSICAL_ADDRESS)(UINTN)(RegisterTable + NumberOfCpus);
}
- AcpiCpuData->RegisterTable =
(EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTable;
- AcpiCpuData->PreSmmInitRegisterTable =
(EFI_PHYSICAL_ADDRESS)(UINTN)(RegisterTable + NumberOfCpus);
//
// Set PcdCpuS3DataAddress to the base address of the ACPI_CPU_DATA structure
--
2.9.3.windows.2
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[edk2] [PATCH 04/11] UefiCpuPkg/Msr: Add CPUID signature check MACROs
All model-specific MSRs are related to processor signatures that are defined in each section in Chapter 35 Model-Specific-Registers (MSR), Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016. Cc: Feng Tian <feng.t...@intel.com> Cc: Michael Kinney <michael.d.kin...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff@intel.com> --- UefiCpuPkg/Include/Register/Msr/AtomMsr.h| 22 +- UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 21 - UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 19 ++- UefiCpuPkg/Include/Register/Msr/CoreMsr.h| 18 +- UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h| 18 +- UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h| 18 +- UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 20 +++- UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 18 +- UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 21 - UefiCpuPkg/Include/Register/Msr/P6Msr.h | 23 ++- UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h| 15 ++- UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h| 18 +- UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 20 +++- UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 19 ++- UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 22 +- UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 19 ++- UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h| 19 ++- UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 19 ++- UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h | 18 +- UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 18 +- 20 files changed, 365 insertions(+), 20 deletions(-) diff --git a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h index c314195..b276469 100644 --- a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. - Copyright (c) 2016, Intel Corporation. All rights reserved. + Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -27,6 +27,26 @@ #include /** + Is Intel(R) Atom(TM) Processor Family? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + (\ +DisplayModel == 0x1C || \ +DisplayModel == 0x26 || \ +DisplayModel == 0x27 || \ +DisplayModel == 0x35 || \ +DisplayModel == 0x36\ +) \ + ) + +/** Shared. Model Specific Platform ID (R). @param ECX MSR_ATOM_PLATFORM_ID (0x0017) diff --git a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h index 1c3c2dc..90bd523 100644 --- a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR. - Copyright (c) 2016, Intel Corporation. All rights reserved. + Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved. This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -27,6 +27,25 @@ #include /** + Is Intel processors based on the Broadwell microarchitecture? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + (\ +DisplayModel == 0x3D || \ +DisplayModel == 0x47 || \ +DisplayModel == 0x4F || \ +DisplayModel == 0x56\ +) \ + ) + +/** Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.". diff --git a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h index 9f0e790..9ebca5e 100644 --- a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h +++ b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h @@ -6,7 +6,7 @@
[edk2] [PATCH 03/11] UefiCpuPkg/PiSmmCpuDxeSmm: Skip if AllocatedSize is 0
Needn't to copy register table if AllocatedSize is 0.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 12efc1f..f24d3d7 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -826,18 +826,20 @@ CopyRegisterTable (
CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus
* sizeof (CPU_REGISTER_TABLE));
for (Index = 0; Index < NumberOfCpus; Index++) {
-RegisterTableEntry = AllocatePool
(DestinationRegisterTableList[Index].AllocatedSize);
-ASSERT (RegisterTableEntry != NULL);
-CopyMem (RegisterTableEntry, (VOID
*)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry,
DestinationRegisterTableList[Index].AllocatedSize);
-//
-// Go though all MSRs in register table to initialize MSR spin lock
-//
-for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength;
Index1++, RegisterTableEntry++) {
- if ((RegisterTableEntry->RegisterType == Msr) &&
(RegisterTableEntry->ValidBitLength < 64)) {
-//
-// Initialize MSR spin lock only for those MSRs need bit field writing
-//
-InitMsrSpinLockByIndex (RegisterTableEntry->Index);
+if (DestinationRegisterTableList[Index].AllocatedSize != 0) {
+ RegisterTableEntry = AllocatePool
(DestinationRegisterTableList[Index].AllocatedSize);
+ ASSERT (RegisterTableEntry != NULL);
+ CopyMem (RegisterTableEntry, (VOID
*)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry,
DestinationRegisterTableList[Index].AllocatedSize);
+ //
+ // Go though all MSRs in register table to initialize MSR spin lock
+ //
+ for (Index1 = 0; Index1 <
DestinationRegisterTableList[Index].TableLength; Index1++,
RegisterTableEntry++) {
+if ((RegisterTableEntry->RegisterType == Msr) &&
(RegisterTableEntry->ValidBitLength < 64)) {
+ //
+ // Initialize MSR spin lock only for those MSRs need bit field
writing
+ //
+ InitMsrSpinLockByIndex (RegisterTableEntry->Index);
+}
}
}
DestinationRegisterTableList[Index].RegisterTableEntry =
(EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
--
2.9.3.windows.2
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[edk2] [PATCH 10/11] UefiCpuPkg: Add NULL CPU Common Features Library instance
This NULL CPU common Features Library instance will register some CPU features
defined in Intel(R) 64 and IA-32 Architectures Software Developer's Manual,
Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR).
Add PCD PcdCpuClockModulationDutyCycle and PcdIsPowerOnReset consumed by NULL
CPU Common Features Library instance.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c| 94 +++
UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 79 ++
.../Library/CpuCommonFeaturesLib/ClockModulation.c | 106 +++
.../CpuCommonFeaturesLib/CpuCommonFeatures.h | 852 +
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c| 227 ++
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 68 ++
.../CpuCommonFeaturesLib/CpuCommonFeaturesLib.uni | 25 +
UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c | 81 ++
.../Library/CpuCommonFeaturesLib/ExecuteDisable.c | 91 +++
.../Library/CpuCommonFeaturesLib/FastStrings.c | 52 ++
.../Library/CpuCommonFeaturesLib/FeatureControl.c | 315
.../CpuCommonFeaturesLib/LimitCpuIdMaxval.c| 82 ++
.../Library/CpuCommonFeaturesLib/MachineCheck.c| 231 ++
.../Library/CpuCommonFeaturesLib/MonitorMwait.c| 79 ++
.../Library/CpuCommonFeaturesLib/PendingBreak.c| 90 +++
UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 81 ++
UefiCpuPkg/UefiCpuPkg.dec | 11 +
17 files changed, 2564 insertions(+)
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
create mode 100644
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
create mode 100644
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
create mode 100644
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.uni
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c
create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
new file mode 100644
index 000..6aebf0d
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
@@ -0,0 +1,94 @@
+/** @file
+ AESNI feature.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuCommonFeatures.h"
+
+/**
+ Detects if AESNI feature supported on current processor.
+
+ @param[in] ProcessorNumber The index of the CPU executing this function.
+ @param[in] CpuInfo A pointer to the
REGISTER_CPU_FEATURE_INFORMATION
+ structure for the CPU executing this function.
+ @param[in] ConfigData A pointer to the configuration buffer returned
+ by CPU_FEATURE_GET_CONFIG_DATA. NULL if
+ CPU_FEATURE_GET_CONFIG_DATA was not provided in
+ RegisterCpuFeature().
+
+ @retval TRUE AESNI feature is supported.
+ @retval FALSEAESNI feature is not supported.
+
+ @note This service could be called by BSP/APs.
+**/
+BOOLEAN
+EFIAPI
+AesniSupport (
+ IN UINTN ProcessorNumber,
+ IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
+ IN VOID *ConfigData OPTIONAL
+ )
+{
+ if (IS_SANDY_BRIDGE_PROCESSOR (CpuInfo->DisplayFamily,
CpuInfo->DisplayModel) ||
+ IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)
||
+ IS_XEON_5600_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
+ IS_XEON_PHI_PROCESSOR (CpuInfo->Di
[edk2] [PATCH 07/11] UefiCpuPkg: Add GUID gEdkiiCpuFeaturesInitDoneGuid
GUID gEdkiiCpuFeaturesInitDoneGuid is used to indicate if CPU features have been
initialized.
On PEI phase, one gEdkiiCpuFeaturesInitDoneGuid PPI will be installed after CPU
features initialized.
On DXE phase, one gEdkiiCpuFeaturesInitDoneGuid Protocol will be installed after
CPU features initialized.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h | 26 ++
UefiCpuPkg/UefiCpuPkg.dec | 3 +++
2 files changed, 29 insertions(+)
create mode 100644 UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h
diff --git a/UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h
b/UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h
new file mode 100644
index 000..ef17da5
--- /dev/null
+++ b/UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h
@@ -0,0 +1,26 @@
+/** @file
+ CPU Features Init Done PPI/Protocol should be installed after CPU features
+ are initialized.
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_FEATURES_INIT_DONE_H_
+#define _CPU_FEATURES_INIT_DONE_H_
+
+#define EDKII_CPU_FEATURES_INIT_DONE_GUID \
+ { \
+{ 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28,
0xe5 } \
+ }
+
+extern EFI_GUID gEdkiiCpuFeaturesInitDoneGuid;
+
+#endif
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 1443e82..f7abe1c 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -68,6 +68,9 @@
## Include/Guid/CpuFeaturesSetDone.h
gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3,
0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}
+ ## Include/Guid/CpuFeaturesInitDone.h
+ gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e,
0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}
+
[Protocols]
## Include/Protocol/SmmCpuService.h
gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7,
0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}
--
2.9.3.windows.2
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[edk2] [PATCH 11/11] UefiCpuPkg: Add CPU Features PEI/DXE drivers
They will consume Register CPU Features library to detect and initialize CPU
features.
CpuFeaturesPei driver is used to initialize CPU features in PEI phase.
CpuFeaturesDxe driver is used to initialize CPU features in DXE phase.
Add PcdCpuFeaturesInitAfterSmmRelocation and PcdCpuFeaturesInitOnS3Resume
that consumed by CpuFeaturesPei and CpuFeaturesDxe.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c| 122 +
UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.inf | 53 +++
UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.uni | 22 +
UefiCpuPkg/CpuFeatures/CpuFeaturesDxeExtra.uni | 20
UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c| 75 +++
UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf | 49 ++
UefiCpuPkg/CpuFeatures/CpuFeaturesPei.uni | 22 +
UefiCpuPkg/CpuFeatures/CpuFeaturesPeiExtra.uni | 20
UefiCpuPkg/UefiCpuPkg.dec | 8 ++
UefiCpuPkg/UefiCpuPkg.dsc | 8 ++
10 files changed, 399 insertions(+)
create mode 100644 UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c
create mode 100644 UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.inf
create mode 100644 UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.uni
create mode 100644 UefiCpuPkg/CpuFeatures/CpuFeaturesDxeExtra.uni
create mode 100644 UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c
create mode 100644 UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf
create mode 100644 UefiCpuPkg/CpuFeatures/CpuFeaturesPei.uni
create mode 100644 UefiCpuPkg/CpuFeatures/CpuFeaturesPeiExtra.uni
diff --git a/UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c
b/UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c
new file mode 100644
index 000..f4f70cf
--- /dev/null
+++ b/UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c
@@ -0,0 +1,122 @@
+/** @file
+ CPU Features DXE driver to initialize CPU features.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+
+/**
+ Worker function to perform CPU feature initialization.
+
+**/
+VOID
+CpuFeaturesInitializeWorker (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ CpuFeaturesDetect ();
+
+ CpuFeaturesInitialize ();
+
+ //
+ // Install CPU Features Init Done Protocol
+ //
+ Handle = NULL;
+ Status = gBS->InstallProtocolInterface (
+ ,
+ ,
+ EFI_NATIVE_INTERFACE,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Event notification that initialize CPU features when
gEfiSmmConfigurationProtocol installs.
+
+ @param[in] Event The Event that is being processed, not
used.
+ @param[in] Context Event Context, not used.
+**/
+VOID
+EFIAPI
+SmmConfigurationEventNotify (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMM_CONFIGURATION_PROTOCOL *SmmConfiguration;
+
+ //
+ // Make sure this notification is for this handler
+ //
+ Status = gBS->LocateProtocol (, NULL, (VOID
**));
+ if (EFI_ERROR (Status)) {
+return;
+ }
+
+ CpuFeaturesInitializeWorker ();
+}
+
+/**
+ CPU Features driver entry point function.
+
+ If PcdCpuFeaturesInitAfterSmmRelocation is TRUE, it will register one
+ SMM Configuration Protocol notify function to perform CPU features
+ initialization. Otherwise, it will perform CPU features initialization
+ directly.
+
+ @param ImageHandle Image handle this driver.
+ @param SystemTable Pointer to the System Table.
+
+ @retval EFI_SUCCESS CPU Features is initialized successfully.
+**/
+EFI_STATUS
+EFIAPI
+CpuFeaturesDxeInitialize (
+ IN EFI_HANDLEImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ VOID*Registration;
+
+ if (PcdGetBool (PcdCpuFeaturesInitAfterSmmRelocation)) {
+//
+// Install notification callback on SMM Configuration Protocol
+//
+EfiCreateProtocolNotifyEvent (
+ ,
+ TPL_CALLBACK,
+ SmmConfigurationEventNotify,
+ NULL,
+
+ );
+ } else {
+CpuFeaturesInitializeWorker ();
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.inf
b/UefiCpuPkg/CpuFeature
[edk2] [PATCH 08/11] UefiCpuPkg/Include/Library: Add Register CPU Features Library
Register CPU Features Library is used to register/manage/program CPU features.
NULL CPU features library instance could consume it register CPU features
functions.
CPU Feature module could consume this library to detect/analysis/program CPU
features on BSP/APs.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../Include/Library/RegisterCpuFeaturesLib.h | 516 +
UefiCpuPkg/UefiCpuPkg.dec | 5 +
2 files changed, 521 insertions(+)
create mode 100644 UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
new file mode 100644
index 000..5b974e7
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
@@ -0,0 +1,516 @@
+/** @file
+ Register CPU Features Library to register and manage CPU features.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __REGISTER_CPU_FEATURES_LIB_H__
+#define __REGISTER_CPU_FEATURES_LIB_H__
+
+#include
+#include
+#include
+
+///
+/// Defines used to identify a CPU feature. The lower 16-bits are used to
+/// identify a unique CPU feature and the value represents a bit number in
+/// a bit mask. The upper 16-bits are bit mask values that are used as
+/// modifiers of a CPU feature. When used in a list, the define value
+/// CPU_FEATURE_END is used to terminate a list of CPU feature values.
+/// @{
+#define CPU_FEATURE_AESNI 0
+#define CPU_FEATURE_TURBO_MODE 1
+#define CPU_FEATURE_MWAIT 2
+#define CPU_FEATURE_ACPI3
+#define CPU_FEATURE_EIST4
+#define CPU_FEATURE_XD 5
+#define CPU_FEATURE_FASTSTRINGS 6
+#define CPU_FEATURE_VMX 7
+#define CPU_FEATURE_SMX 8
+#define CPU_FEATURE_SENTER 9
+#define CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER 10
+#define CPU_FEATURE_LIMIT_CPUID_MAX_VAL 11
+#define CPU_FEATURE_MCE 12
+#define CPU_FEATURE_MCA 13
+#define CPU_FEATURE_MCG_CTL 14
+#define CPU_FEATURE_PENDING_BREAK 15
+#define CPU_FEATURE_C1E 16
+#define CPU_FEATURE_C1_AUTO_DEMOTION17
+#define CPU_FEATURE_C3_AUTO_DEMOTION18
+#define CPU_FEATURE_C1_AUTO_UNDEMOTION 19
+#define CPU_FEATURE_C3_AUTO_UNDEMOTION 20
+#define CPU_FEATURE_C_STATE 21
+#define CPU_FEATURE_TM 22
+#define CPU_FEATURE_TM2 23
+#define CPU_FEATURE_X2APIC 24
+#define CPU_FEATURE_RESERVED_25 25
+#define CPU_FEATURE_RESERVED_26 26
+#define CPU_FEATURE_RESERVED_27 27
+#define CPU_FEATURE_RESERVED_28 28
+#define CPU_FEATURE_RESERVED_29 29
+#define CPU_FEATURE_RESERVED_30 30
+#define CPU_FEATURE_RESERVED_31 31
+
+#define CPU_FEATURE_L2_PREFETCHER (32+0)
+#define CPU_FEATURE_L1_DATA_PREFETCHER (32+1)
+#define CPU_FEATURE_HARDWARE_PREFETCHER (32+2)
+#define CPU_FEATURE_ADJACENT_CACHE_LINE_PREFETCH(32+3)
+#define CPU_FEATURE_DCU_PREFETCHER (32+4)
+#define CPU_FEATURE_IP_PREFETCHER (32+5)
+#define CPU_FEATURE_MLC_STREAMER_PREFETCHER (32+6)
+#define CPU_FEATURE_MLC_SPATIAL_PREFETCHER (32+7)
+#define CPU_FEATURE_THREE_STRICK_COUNTER(32+8)
+#define CPU_FEATURE_APIC_TPR_UPDATE_MESSAGE (32+9)
+#define CPU_FEATURE_ENERGY_PERFORMANCE_BIAS (32+10)
+
+#define CPU_FEATURE_BEFORE_ALL BIT27
+#define CPU_FEATURE_AFTER_ALL BIT28
+#define CPU_FEATURE_BEFORE BIT29
+#define CPU_FEATURE_AFTER BIT30
+#define CPU_FEATURE_END MAX_UINT32
+/// @}
+
+///
+/// CPU Information passed into the SupportFunc and InitializeFunc of the
+/// RegisterCpuFeature() library function. This structure contains information
+/// that
[edk2] [PATCH 09/11] UefiCpuPkg: Add PEI/DXE Register CPU Features Library instances
PEI Register CPU Features Library instance is used to register/manager/program
CPU features on PEI phase.
DXE Register CPU Features Library instance is used to register/manager/program
CPU features on DXE phase.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
.../RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 700 +++
.../DxeRegisterCpuFeaturesLib.c| 266 +++
.../DxeRegisterCpuFeaturesLib.inf | 62 ++
.../PeiRegisterCpuFeaturesLib.c| 390 +++
.../PeiRegisterCpuFeaturesLib.inf | 64 ++
.../RegisterCpuFeaturesLib/RegisterCpuFeatures.h | 193 ++
.../RegisterCpuFeaturesDxe.uni | 22 +
.../RegisterCpuFeaturesLib.c | 770 +
UefiCpuPkg/UefiCpuPkg.dsc | 6 +-
9 files changed, 2472 insertions(+), 1 deletion(-)
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.inf
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.inf
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesDxe.uni
create mode 100644
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
new file mode 100644
index 000..30dc0b8
--- /dev/null
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -0,0 +1,700 @@
+/** @file
+ CPU Features Initialize functions.
+
+ Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "RegisterCpuFeatures.h"
+
+/**
+ Worker function to save PcdCpuFeaturesCapability.
+
+ @param[in] SupportedFeatureMask The pointer to CPU feature bits mask buffer
+*/
+VOID
+SetCapabilityPcd (
+ IN UINT8 *SupportedFeatureMask
+ )
+{
+ EFI_STATUS Status;
+ UINTN BitMaskSize;
+
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesCapability);
+ Status = PcdSetPtrS (PcdCpuFeaturesCapability, ,
SupportedFeatureMask);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Worker function to save PcdCpuFeaturesSetting.
+
+ @param[in] SupportedFeatureMask The pointer to CPU feature bits mask buffer
+**/
+VOID
+SetSettingPcd (
+ IN UINT8 *SupportedFeatureMask
+ )
+{
+ EFI_STATUS Status;
+ UINTN BitMaskSize;
+
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesSetting);
+ Status = PcdSetPtrS (PcdCpuFeaturesSetting, ,
SupportedFeatureMask);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+ Worker function to get PcdCpuFeaturesSupport.
+
+ @return The pointer to CPU feature bits mask buffer.
+**/
+UINT8 *
+GetSupportPcds (
+ VOID
+ )
+{
+ UINTN BitMaskSize;
+ UINT8 *SupportBitMask;
+
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesSupport);
+ SupportBitMask = AllocateZeroPool (BitMaskSize);
+ SupportBitMask = (UINT8 *) PcdGetPtr (PcdCpuFeaturesSupport);
+
+ return SupportBitMask;
+}
+
+/**
+ Worker function to get PcdCpuFeaturesUserConfiguration.
+
+ @return The pointer to CPU feature bits mask buffer.
+**/
+UINT8 *
+GetConfigurationPcds (
+ VOID
+ )
+{
+ UINTN BitMaskSize;
+ UINT8 *SupportBitMask;
+
+ BitMaskSize = PcdGetSize (PcdCpuFeaturesUserConfiguration);
+ SupportBitMask = AllocateZeroPool (BitMaskSize);
+ SupportBitMask = (UINT8 *) PcdGetPtr (PcdCpuFeaturesUserConfiguration);
+
+ return SupportBitMask;
+}
+
+/**
+ Collects CPU type and feature information.
+
+ @param[in, out] CpuInfo The pointer to CPU feature information
+**/
+VOID
+FillProcessorInfo (
+ IN OUT REGISTER_CPU_FEATURE_INFORMATION*CpuInfo
+ )
+{
+ CPUID_VERSION_INFO_EAX Eax;
+ CPUID_VERSION_INFO_ECX Ecx;
+ CPUID_VERSION_INFO_EDX Edx;
+ UINT32 DisplayedFamily;
+ UINT32 DisplayedModel;
+
+
[edk2] [PATCH 06/11] UefiCpuPkg: Add GUID gEdkiiCpuFeaturesSetDoneGuid
GUID gEdkiiCpuFeaturesSetDoneGuid is used to indicate if CPU feature related
setting are set finished. For example, PCD PcdCpuFeaturesUserConfiguration.
On PEI phase, one gEdkiiCpuFeaturesSetDoneGuid PPI will be installed after
platform set CPU feature setting.
On DXE phase, one gEdkiiCpuFeaturesSetDoneGuid Protocol will be installed after
platform set CPU feature setting.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h | 26 ++
UefiCpuPkg/UefiCpuPkg.dec| 3 +++
2 files changed, 29 insertions(+)
create mode 100644 UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h
diff --git a/UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h
b/UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h
new file mode 100644
index 000..8b1592e
--- /dev/null
+++ b/UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h
@@ -0,0 +1,26 @@
+/** @file
+ CPU Features Set Done PPI/Protocol should be installed after CPU features
+ configuration are set.
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_FEATURES_INIT_DONE_H_
+#define _CPU_FEATURES_INIT_DONE_H_
+
+#define EDKII_CPU_FEATURES_SET_DONE_GUID \
+ { \
+{ 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e,
0x37 } \
+ }
+
+extern EFI_GUID gEdkiiCpuFeaturesSetDoneGuid;
+
+#endif
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index c4b43e2..1443e82 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -65,6 +65,9 @@
## Include/Guid/MicrocodeFmp.h
gMicrocodeFmpImageTypeIdGuid = { 0x96d4fdcd, 0x1502, 0x424d, { 0x9d,
0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } }
+ ## Include/Guid/CpuFeaturesSetDone.h
+ gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3,
0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}
+
[Protocols]
## Include/Protocol/SmmCpuService.h
gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7,
0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}
--
2.9.3.windows.2
___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 01/11] UefiCpuPkg/AcpiCpuData: Update RegisterTableEntry type
Current RegisterTableEntry filed in CPU_REGISTER_TABLE is one pointer to
CPU_REGISTER_TABLE_ENTRY. If CPU register table wants to be passed from 32bit
PEI to x64 DXE/SMM, x64 DXE/SMM cannot get the correct RegisterTableEntry.
This update is to update RegisterTableEntry type to EFI_PHYSICAL_ADDRESS and
make RegisterTableEntry is fixed length.
Cc: Feng Tian <feng.t...@intel.com>
Cc: Michael Kinney <michael.d.kin...@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff@intel.com>
---
UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c | 6 +++---
UefiCpuPkg/Include/AcpiCpuData.h| 6 +++---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 10 +-
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
index 3489b95..07c7102 100644
--- a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
+++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
@@ -9,7 +9,7 @@ number of CPUs reported by the MP Services Protocol, so this
module does not
support hot plug CPUs. This module can be copied into a CPU specific package
and customized if these additional features are required.
-Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2015, Red Hat, Inc.
This program and the accompanying materials
@@ -246,12 +246,12 @@ CpuS3DataInitialize (
RegisterTable[Index].InitialApicId =
(UINT32)ProcessorInfoBuffer.ProcessorId;
RegisterTable[Index].TableLength= 0;
RegisterTable[Index].AllocatedSize = 0;
-RegisterTable[Index].RegisterTableEntry = NULL;
+RegisterTable[Index].RegisterTableEntry = 0;
RegisterTable[NumberOfCpus + Index].InitialApicId =
(UINT32)ProcessorInfoBuffer.ProcessorId;
RegisterTable[NumberOfCpus + Index].TableLength= 0;
RegisterTable[NumberOfCpus + Index].AllocatedSize = 0;
-RegisterTable[NumberOfCpus + Index].RegisterTableEntry = NULL;
+RegisterTable[NumberOfCpus + Index].RegisterTableEntry = 0;
}
AcpiCpuData->RegisterTable =
(EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTable;
AcpiCpuData->PreSmmInitRegisterTable =
(EFI_PHYSICAL_ADDRESS)(UINTN)(RegisterTable + NumberOfCpus);
diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuData.h
index 12e9692..130eb90 100644
--- a/UefiCpuPkg/Include/AcpiCpuData.h
+++ b/UefiCpuPkg/Include/AcpiCpuData.h
@@ -1,7 +1,7 @@
/** @file
Definitions for CPU S3 data.
-Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -55,10 +55,10 @@ typedef struct {
//
UINT32InitialApicId;
//
- // Buffer of CPU_REGISTER_TABLE_ENTRY structures. This buffer must be
+ // Physical address of CPU_REGISTER_TABLE_ENTRY structures. This buffer
must be
// allocated below 4GB from memory of type EfiACPIMemoryNVS.
//
- CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
+ EFI_PHYSICAL_ADDRESS RegisterTableEntry;
} CPU_REGISTER_TABLE;
//
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 532b7c4..12efc1f 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -1,7 +1,7 @@
/** @file
Code for Processor S3 restoration
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -826,13 +826,12 @@ CopyRegisterTable (
CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus
* sizeof (CPU_REGISTER_TABLE));
for (Index = 0; Index < NumberOfCpus; Index++) {
-DestinationRegisterTableList[Index].RegisterTableEntry = AllocatePool
(DestinationRegisterTableList[Index].AllocatedSize);
-ASSERT (DestinationRegisterTableList[Index].RegisterTableEntry != NULL);
-CopyMem (DestinationRegisterTableList[Index].RegisterTableEntry,
SourceRegisterTableList[Index].RegisterTableEntry,
DestinationRegisterTableList[Index].AllocatedSize);
+RegisterTableEntry = AllocatePool
(DestinationRegisterTableList[Index].AllocatedSize);
+ASSERT (RegisterTableEntry != NULL);
+CopyMem (RegisterTableEntry, (VOID
*)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry,
DestinationRegisterTableList[Index].AllocatedSize);
//
// Go though all MSRs in register table to initialize MSR spin lock
//
-RegisterTableEntry =
Destina
