[edk2] [PATCH] CorebootPayloadPkg: Add OHCI driver
Add the USB OHCI driver from revision 24ca2f35 of QuarkSocPkg. Change-Id: Ie7aa0bc47d4ff06adc57976a5efb0e40ce4e1673 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- CorebootPayloadPkg/CorebootPayloadPkg.fdf| 5 + CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 5 + CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 5 + 3 files changed, 15 insertions(+) diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf index 4102e60..0e8ec43 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf +++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf @@ -159,6 +159,11 @@ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf # +# OHCI Support +# +INF QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciDxe.inf + +# # Shell # !if $(SHELL_TYPE) == BUILD_SHELL diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc index 9f155f3..dc86eb1 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc @@ -431,6 +431,11 @@ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf # + # OHCI support + # + QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciDxe.inf + + # # ISA Support # CorebootModulePkg/SerialDxe/SerialDxe.inf diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc index 7b065a6..dabd2dd 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc @@ -435,6 +435,11 @@ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf # + # OHCI support + # + QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciDxe.inf + + # # ISA Support # CorebootModulePkg/SerialDxe/SerialDxe.inf -- 1.9.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 3/3] QuarkSocPkg/SDControllerDxe: Add EFIAPI to SetHighSpeedMode
Add the missing EFIAPI to fix the inconsistent routine declaration and implementation of a protocol service. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.c | 1 + 1 file changed, 1 insertion(+) diff --git a/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.c b/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.c index 18e85c8..2b5dbe6 100644 --- a/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.c +++ b/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.c @@ -244,6 +244,7 @@ GetErrorReason ( @return EFI_SUCCESS **/ EFI_STATUS +EFIAPI SetHighSpeedMode ( IN EFI_SD_HOST_IO_PROTOCOL*This, IN BOOLEANEnable -- 1.9.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 2/3] QuarkPlatformPkg: Fix variable set but not used build errors
Fix variable set but not used errors detected by GCC 4.8.
Change-Id: I83634f88cfa89ea8afdfebbd0c7487f04e440693
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.c | 14 +-
.../Library/PlatformHelperLib/PlatformHelperPei.c | 2 --
QuarkPlatformPkg/Platform/SpiFvbServices/FwBlockService.c | 5 -
3 files changed, 1 insertion(+), 20 deletions(-)
diff --git a/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.c
b/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.c
index 8f5e6a3..a73b4c9 100644
--- a/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.c
+++ b/QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.c
@@ -79,7 +79,6 @@ PpmPatchFadtTable (
EFI_ACPI_TABLE_VERSIONVersion;
UINTN Index;
UINTN Handle;
- EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtPointer;
//
// Scan all the acpi tables to find FADT 2.0
@@ -106,9 +105,7 @@ PpmPatchFadtTable (
ASSERT (Table != NULL);
CopyMem (Table, CurrentTable, CurrentTable->Length);
- FadtPointer = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE*) Table;
-
-//
+ //
// Update the ACPI table and recalculate checksum
//
Status = mAcpiTable->UninstallAcpiTable (mAcpiTable, Handle);
@@ -322,7 +319,6 @@ PpmLoadAndPatchPMTables (
UINTN TableHandle;
UINT32FvStatus;
UINTN Size;
- EFI_ACPI_TABLE_VERSION Version;
Status = LocateSupportProtocol (,
(VOID**), 1);
if (EFI_ERROR (Status)) {
@@ -348,14 +344,6 @@ PpmLoadAndPatchPMTables (
);
if (!EFI_ERROR(Status)) {
-Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 |
EFI_ACPI_TABLE_VERSION_3_0;
-
- if(((EFI_ACPI_DESCRIPTION_HEADER*) CurrentTable)->OemTableId ==
SIGNATURE_64 ('C', 'p', 'u', '0', 'I', 's', 't', 0)) {
- Version = EFI_ACPI_TABLE_VERSION_NONE;
- } else if(((EFI_ACPI_DESCRIPTION_HEADER*) CurrentTable)->OemTableId ==
SIGNATURE_64 ('C', 'p', 'u', '1', 'I', 's', 't', 0)) {
- Version = EFI_ACPI_TABLE_VERSION_NONE;
- }
-
SsdtTableUpdate ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable);
//
diff --git a/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperPei.c
b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperPei.c
index 50a0e42..9976862 100644
--- a/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperPei.c
+++ b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperPei.c
@@ -63,7 +63,6 @@ PlatformFindFvFileRawDataSection (
EFI_SECTION_TYPE SearchType;
EFI_FV_INFO VolumeInfo;
EFI_FV_FILE_INFO FileInfo;
- CONST EFI_PEI_SERVICES**PeiServices;
if (FileNameGuid == NULL || SectionData == NULL || SectionDataSize == NULL) {
return EFI_INVALID_PARAMETER;
@@ -71,7 +70,6 @@ PlatformFindFvFileRawDataSection (
*SectionData = NULL;
*SectionDataSize = 0;
- PeiServices = GetPeiServicesTablePointer ();
SearchType = EFI_SECTION_RAW;
for (Instance = 0; !EFI_ERROR((PeiServicesFfsFindNextVolume (Instance,
))); Instance++) {
if (FvNameGuid != NULL) {
diff --git a/QuarkPlatformPkg/Platform/SpiFvbServices/FwBlockService.c
b/QuarkPlatformPkg/Platform/SpiFvbServices/FwBlockService.c
index 6cfe710..2185014 100644
--- a/QuarkPlatformPkg/Platform/SpiFvbServices/FwBlockService.c
+++ b/QuarkPlatformPkg/Platform/SpiFvbServices/FwBlockService.c
@@ -590,9 +590,6 @@ Returns:
--*/
{
EFI_STATUS Status;
- UINTN NumBytes;
-
- NumBytes = LbaLength;
WriteAddress -= (PcdGet32 (PcdFlashAreaBaseAddress));
if (mInSmmMode == 0 ) { // !(EfiInManagementInterrupt ())) {
@@ -1638,7 +1635,6 @@ Returns:
VOID*FirmwareVolumeHobList;
UINT32 BufferSize;
EFI_FV_BLOCK_MAP_ENTRY *PtrBlockMapEntry;
- UINTN LbaAddress;
BOOLEAN WriteEnabled;
BOOLEAN WriteLocked;
EFI_HANDLE FwbHandle;
@@ -1882,7 +1878,6 @@ Returns:
FwhInstance->WriteEnabled = WriteEnabled;
EfiInitializeLock (&(FwhInstance->FvbDevLock), TPL_HIGH_LEVEL);
-LbaAddress = (UINTN) FwhInstance->FvWriteBase[0];
NumOfBlocks = 0;
WriteLocked = FALSE;
--
1.9.1
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[edk2] [PATCH 3/3] QuarkSocPkg/SDControllerDxe: Add EFIAPI to SetHighSpeedMode
Fix 64-bit build error detected with GCC4.8 due to inconsistent routine declaration and implementation. Add EFIAPI to fix the build error. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.c | 1 + 1 file changed, 1 insertion(+) diff --git a/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.c b/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.c index 18e85c8..2b5dbe6 100644 --- a/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.c +++ b/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.c @@ -244,6 +244,7 @@ GetErrorReason ( @return EFI_SUCCESS **/ EFI_STATUS +EFIAPI SetHighSpeedMode ( IN EFI_SD_HOST_IO_PROTOCOL*This, IN BOOLEANEnable -- 1.9.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 1/3] QuarkPlatformPkg: Fix build errors
Fix build errors detected with GCC 4.8.4: local variable set but not
used!
Change-Id: I5e3cfb46b367a72bd333fd762c22968fbac4e6f9
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.c | 2 --
QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c | 4
.../Dxe/SmbiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c| 4 +---
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemStringFunction.c | 3 ---
.../Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionStringFunction.c | 3 ---
QuarkPlatformPkg/Platform/Pei/PlatformInit/Generic/Recovery.c | 6 --
QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c | 5 +
7 files changed, 2 insertions(+), 25 deletions(-)
diff --git a/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.c
b/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.c
index b0f0b44..653df45 100644
--- a/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.c
+++ b/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.c
@@ -261,9 +261,7 @@ SdtGetNameStringSize (
{
UINTN SegCount;
UINTN Length;
- UINT8 *Name;
- Name = Buffer;
Length = 0;
//
diff --git a/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c
b/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c
index aa18cae..f085753 100644
--- a/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c
+++ b/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c
@@ -255,7 +255,6 @@ ApicTableUpdate (
UINT8 CurrProcessor;
UINTN NumberOfCPUs;
UINTN NumberOfEnabledCPUs;
- UINTN BufferSize;
EFI_PROCESSOR_INFORMATION MpContext;
ACPI_APIC_STRUCTURE_PTR*ApicPtr;
@@ -298,7 +297,6 @@ ApicTableUpdate (
switch (ApicPtr->AcpiApicCommon.Type) {
case EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC:
-BufferSize = sizeof (EFI_PROCESSOR_INFORMATION);
ApicPtr->AcpiLocalApic.Flags = 0;
ApicPtr->AcpiLocalApic.ApicId = 0;
Status = MpService->GetProcessorInfo (
@@ -562,7 +560,6 @@ AcpiPlatformEntryPoint (
UINT32FvStatus;
UINTN Size;
EFI_ACPI_TABLE_VERSIONVersion;
- QNC_DEVICE_ENABLESQNCDeviceEnables;
EFI_HANDLEHandle;
UINTN Index;
PCI_DEVICE_INFO *PciDeviceInfo;
@@ -577,7 +574,6 @@ AcpiPlatformEntryPoint (
TableHandle = 0;
CurrentTable = NULL;
mConfigData = NULL;
- QNCDeviceEnables.Uint32 = PcdGet32 (PcdDeviceEnables);
//
// Initialize the EFI Driver Library
diff --git
a/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c
b/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c
index d17f5ea..48c2d53 100644
---
a/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c
+++
b/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c
@@ -190,7 +190,6 @@ MISC_SMBIOS_TABLE_FUNCTION(NumberOfInstallableLanguages)
CHAR8
CurrentLang[SMBIOS_STRING_MAX_LENGTH + 1];
CHAR8 *OptionalStrStart;
UINT16Offset;
- BOOLEAN LangMatch;
EFI_STATUSStatus;
EFI_SMBIOS_HANDLE SmbiosHandle;
SMBIOS_TABLE_TYPE13 *SmbiosRecord;
@@ -210,9 +209,8 @@ MISC_SMBIOS_TABLE_FUNCTION(NumberOfInstallableLanguages)
//
// Try to check if current langcode matches with the langcodes in installed
languages
//
- LangMatch = FALSE;
ZeroMem(CurrentLang, SMBIOS_STRING_MAX_LENGTH + 1);
- LangMatch = CurrentLanguageMatch (mHiiHandle, , CurrentLang);
+ CurrentLanguageMatch (mHiiHandle, , CurrentLang);
LangStrLen = AsciiStrLen(CurrentLang);
//
diff --git
a/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemStringFunction.c
b/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemStringFunction.c
index e352000..af6df02 100644
--- a/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemStringFunction.c
+++ b/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemStringFunction.c
@@ -38,9 +38,6 @@ MISC_SMBIOS_TABLE_FUNCTION(MiscOemString)
STRING_REF TokenToGet;
EFI_SMBIOS_HANDLESmbiosHandle;
SMBIOS_TABLE_TYPE11 *SmbiosRecord;
- EFI_MISC_OEM_STRING *ForType11InputData;
-
- ForType11InputData = (EFI_MISC_OEM_STRING *)RecordData;
//
// First check for invalid parameters.
diff --git
a/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionStringFunction.c
b/QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionStringFunction.c
index 44cc6
[edk2] [PATCH 7/7] CorebootPayloadPkg: Add BdsDxe support
Add define to select the MdeModulePkg/Universal/BdsDxe instead of IntelFrameworkModulePkg/Universal/BdsDxe. Change-Id: I0930b375e46fd72a199567efc422df5bb535798c Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- CorebootPayloadPkg/CorebootPayloadPkg.fdf | 14 +- CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 22 +- CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 22 +- .../PlatformBootManagerLib/PlatformBootManager.c | 339 + .../PlatformBootManagerLib/PlatformBootManager.h | 50 +++ .../PlatformBootManagerLib.inf | 73 + .../Library/PlatformBootManagerLib/PlatformData.c | 281 + 7 files changed, 794 insertions(+), 7 deletions(-) create mode 100644 CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c create mode 100644 CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.h create mode 100644 CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf create mode 100644 CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformData.c diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf index 432155f..df771ef 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf +++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf @@ -86,7 +86,11 @@ INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf INF UefiCpuPkg/CpuDxe/CpuDxe.inf +!if $(BDS_TYPE) == IntelFrameworkModulePkg INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf +!else +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf +!endif INF PcAtChipsetPkg/8254TimerDxe/8254Timer.inf INF MdeModulePkg/Universal/Metronome/Metronome.inf INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf @@ -112,12 +116,16 @@ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf # INF CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf INF CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf -INF CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.inf # -# ISA Support +# Serial Support # -INF CorebootModulePkg/SerialDxe/SerialDxe.inf +!if $(BDS_TYPE) == IntelFrameworkModulePkg + + INF CorebootModulePkg/SerialDxe/SerialDxe.inf +!else + INF CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.inf +!endif # # Console Support diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc index a9e78a5..57c2dce 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc @@ -34,6 +34,11 @@ DEFINE SOURCE_DEBUG_ENABLE = FALSE # + # BDS Options: [IntelFrameworkModulePkg, MdeModulePkg] + # + DEFINE BDS_TYPE= IntelFrameworkModulePkg + + # # CPU options # DEFINE MAX_LOGICAL_PROCESSORS = 64 @@ -162,7 +167,13 @@ ResetSystemLib|CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf SerialPortLib|CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf PlatformHookLib|CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf +!if $(BDS_TYPE) == IntelFrameworkModulePkg PlatformBdsLib|CorebootPayloadPkg/Library/PlatformBdsLib/PlatformBdsLib.inf +!else + PlatformBootManagerLib|CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf +!endif # # Misc @@ -353,7 +364,11 @@ # MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf UefiCpuPkg/CpuDxe/CpuDxe.inf +!if $(BDS_TYPE) == IntelFrameworkModulePkg IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf +!else + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf +!endif PcAtChipsetPkg/8254TimerDxe/8254Timer.inf MdeModulePkg/Universal/Metronome/Metronome.inf MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf @@ -398,7 +413,6 @@ # CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf - CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.inf # # SCSI/ATA/IDE/DISK Support @@ -436,9 +450,13 @@ CorebootModulePkg/OhciDxe/OhciDxe.inf # - # ISA Support + # Serial Support # +!if $(BDS_TYPE) == IntelFrameworkModulePkg CorebootModulePkg/SerialDxe/SerialDxe.inf +!else + CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.inf +!endif # # Console Support diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc index 5dd17cb..d377535 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc @@ -34,6 +34,11 @@ DEFINE SOURCE_DEBUG_ENABLE =
[edk2] [PATCH 2/7] CorebootPayloadPkg: Assume no PCI serial devices
Set the vendor to 0x which indicates the end of the list.
Change-Id: If6475e04d3675f0a932571a85d1dd3f301416b6a
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 4 ++--
CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index 907e952..cc88502 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -67,10 +67,10 @@
#UINT8 Reserved[2];
# } PCI_SERIAL_PARAMETER;
#
- # Vendor Device Prog Interface 1, BAR #0, Offset 0, Stride = 1,
Clock 1843200 (0x1c2000)
+ # Vendor Device Prog Interface 1, BAR #0, Offset 0, Stride = 1,
Clock 1843200 (0x1c2000)
#
# [Vendor] [Device]
[ClockRate---] [Offset---] [Bar] [Stride] [RxFifo]
[TxFifo] [Rsvd] [Vendor]
- DEFINE PCI_SERIAL_PARAMETERS= {0x00,0x00, 0x00,0x00,
0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00,0x01, 0x0,0x0,
0x0,0x0, 0x0,0x0, 0xff,0xff}
+ DEFINE PCI_SERIAL_PARAMETERS= {0xff,0xff, 0x00,0x00,
0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00,0x01, 0x0,0x0,
0x0,0x0, 0x0,0x0, 0xff,0xff}
#
# Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI]
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index 90a484d..77a33a9 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -67,10 +67,10 @@
#UINT8 Reserved[2];
# } PCI_SERIAL_PARAMETER;
#
- # Vendor Device Prog Interface 1, BAR #0, Offset 0, Stride = 1,
Clock 1843200 (0x1c2000)
+ # Vendor Device Prog Interface 1, BAR #0, Offset 0, Stride = 1,
Clock 1843200 (0x1c2000)
#
# [Vendor] [Device]
[ClockRate---] [Offset---] [Bar] [Stride] [RxFifo]
[TxFifo] [Rsvd] [Vendor]
- DEFINE PCI_SERIAL_PARAMETERS= {0x00,0x00, 0x00,0x00,
0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00,0x01, 0x0,0x0,
0x0,0x0, 0x0,0x0, 0xff,0xff}
+ DEFINE PCI_SERIAL_PARAMETERS= {0xff,0xff, 0x00,0x00,
0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00,0x01, 0x0,0x0,
0x0,0x0, 0x0,0x0, 0xff,0xff}
#
# Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI]
--
1.9.1
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[edk2] [PATCH 3/7] CorebootPayloadPkg: Use correct BaseSerialPortLib16550
Use the BaseSerialPortLib16550 which sets RTS and DTR during initialization. This fixes the mis-matched flow control issue when the flow control signals are connected between the host and target and the host has flow control enabled. Change-Id: I3505e129b2de3c5c17fff23c62553f15cd892dca Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 2 +- CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc index cc88502..9be96e3 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc @@ -160,7 +160,7 @@ # TimerLib|CorebootPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf ResetSystemLib|CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf - SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf + SerialPortLib|CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf PlatformHookLib|CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf PlatformBdsLib|CorebootPayloadPkg/Library/PlatformBdsLib/PlatformBdsLib.inf diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc index 77a33a9..561c0c9 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc @@ -162,7 +162,7 @@ # TimerLib|CorebootPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.inf ResetSystemLib|CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.inf - SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf + SerialPortLib|CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf PlatformHookLib|CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf PlatformBdsLib|CorebootPayloadPkg/Library/PlatformBdsLib/PlatformBdsLib.inf -- 1.9.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 4/7] CorebootPayloadPkg: Set the proper Shell file GUID
Set the proper Shell file GUID so that the BDS transfers control to the
Shell.
Change-Id: I816636a340bbe2f76ac1973b9cb685084c4f88a0
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 11 +++
CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 11 +++
2 files changed, 22 insertions(+)
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index 9be96e3..72b69f2 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -288,6 +288,17 @@
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS)
+ #
+ # Set the proper Shell file GUID
+ #
+ !if $(SHELL_TYPE) == FULL_BIN
+ # c57ad6b7-0515-40a8-9d21-551652854e37
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0xB7, 0xD6, 0x7A,
0xC5, 0x15, 0x05, 0xA8, 0x40, 0x9D, 0x21, 0x55, 0x16, 0x52, 0x85, 0x4E, 0x37 }
+ !else
+ # 7C04A583-9E3E-4f1c-AD65-E05268D0B4D1
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04,
0x7C, 0x3E, 0x9E, 0x1c, 0x4f, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+ !endif
+
#
# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index 561c0c9..21e2548 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -292,6 +292,17 @@
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS)
+ #
+ # Set the proper Shell file GUID
+ #
+ !if $(SHELL_TYPE) == FULL_BIN
+ # c57ad6b7-0515-40a8-9d21-551652854e37
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0xB7, 0xD6, 0x7A,
0xC5, 0x15, 0x05, 0xA8, 0x40, 0x9D, 0x21, 0x55, 0x16, 0x52, 0x85, 0x4E, 0x37 }
+ !else
+ # 7C04A583-9E3E-4f1c-AD65-E05268D0B4D1
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04,
0x7C, 0x3E, 0x9E, 0x1c, 0x4f, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+ !endif
+
#
# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform
--
1.9.1
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[edk2] [PATCH 5/7] CorebootPayloadPkg: Add SD/eMMC support
Add SD and eMMC DXE driver support to CorebootPayloadPkg. Change-Id: Ibfd3a2cc32a653ce51e38d9157ea3c6da25a5474 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- CorebootPayloadPkg/CorebootPayloadPkg.fdf| 7 +++ CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 7 +++ CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 7 +++ 3 files changed, 21 insertions(+) diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf index 7b52f40..cb18828 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf +++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf @@ -142,6 +142,13 @@ INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf INF FatPkg/EnhancedFatDxe/Fat.inf # +# SD/eMMC Support +# +INF MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf +INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf +INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf + +# # Usb Support # INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc index 72b69f2..73af2dd 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc @@ -414,6 +414,13 @@ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf # + # SD/eMMC Support + # + MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf + MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf + MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf + + # # Usb Support # MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc index 21e2548..95ec8ce 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc @@ -418,6 +418,13 @@ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf # + # SD/eMMC Support + # + MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf + MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf + MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf + + # # Usb Support # MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf -- 1.9.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH] IntelFrameworkModulePkg/BootMaint: Fix ASSERT condition
GroupMultipleLegacyBootOption4SameType ASSERTs with EFI_NOT_FOUND when
the BootOrder variable is not found. This occurs because BootOrderSize
is zero and BootOrder is NULL. This patch eliminates the two ASSERTs
which occur.
Change-Id: I6b4f713575011da7c7442fe25ebdbd8379b0303b
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
.../Universal/BdsDxe/BootMaint/BBSsupport.c| 41 --
1 file changed, 22 insertions(+), 19 deletions(-)
diff --git a/IntelFrameworkModulePkg/Universal/BdsDxe/BootMaint/BBSsupport.c
b/IntelFrameworkModulePkg/Universal/BdsDxe/BootMaint/BBSsupport.c
index 6a0b525..379a951 100644
--- a/IntelFrameworkModulePkg/Universal/BdsDxe/BootMaint/BBSsupport.c
+++ b/IntelFrameworkModulePkg/Universal/BdsDxe/BootMaint/BBSsupport.c
@@ -53,9 +53,9 @@ OrderLegacyBootOption4SameType (
UINTNBootOrderSize;
UINTNIndex;
UINTNStartPosition;
-
+
BDS_COMMON_OPTION*BootOption;
-
+
CHAR16 OptionName[sizeof ("Boot")];
UINT16 *BbsIndexArray;
UINT16 *DeviceTypeArray;
@@ -82,12 +82,12 @@ OrderLegacyBootOption4SameType (
ASSERT (*DisBootOption != NULL);
for (Index = 0; Index < BootOrderSize / sizeof (UINT16); Index++) {
-
+
UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x",
BootOrder[Index]);
InitializeListHead ();
BootOption = BdsLibVariableToOption (, OptionName);
ASSERT (BootOption != NULL);
-
+
if ((DevicePathType (BootOption->DevicePath) == BBS_DEVICE_PATH) &&
(DevicePathSubType (BootOption->DevicePath) == BBS_BBS_DP)) {
//
@@ -119,7 +119,7 @@ OrderLegacyBootOption4SameType (
if (BbsIndexArray[Index] == (DevOrder[DevOrderCount] & 0xFF)) {
StartPosition = MIN (StartPosition, Index);
NewBootOption[DevOrderCount] = BootOrder[Index];
-
+
if ((DevOrder[DevOrderCount] & 0xFF00) == 0xFF00) {
(*DisBootOption)[*DisBootOptionCount] = BootOrder[Index];
(*DisBootOptionCount)++;
@@ -157,7 +157,7 @@ OrderLegacyBootOption4SameType (
/**
Group the legacy boot options in the BootOption.
- The routine assumes the boot options in the beginning that covers all the
device
+ The routine assumes the boot options in the beginning that covers all the
device
types are ordered properly and re-position the following boot options just
after
the corresponding boot options with the same device type.
For example:
@@ -194,7 +194,6 @@ GroupMultipleLegacyBootOption4SameType (
,
);
-
for (Index = 0; Index < BootOrderSize / sizeof (UINT16); Index++) {
UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x",
BootOrder[Index]);
InitializeListHead ();
@@ -238,17 +237,21 @@ GroupMultipleLegacyBootOption4SameType (
FreePool (BootOption);
}
- Status = gRT->SetVariable (
- L"BootOrder",
- ,
- EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
- BootOrderSize,
- BootOrder
- );
- //
- // Changing content without increasing its size with current variable
implementation shouldn't fail.
- //
- ASSERT_EFI_ERROR (Status);
- FreePool (BootOrder);
+ if (BootOrder != NULL) {
+if (BootOrderSize != 0) {
+ Status = gRT->SetVariable (
+ L"BootOrder",
+ ,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+ BootOrderSize,
+ BootOrder
+ );
+ //
+ // Changing content without increasing its size with current variable
implementation shouldn't fail.
+ //
+ ASSERT_EFI_ERROR (Status);
+}
+FreePool (BootOrder);
+ }
}
--
1.9.1
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[edk2] [PATCH 1/7] CorebootPayloadPkg: Use DOS line endings
Convert to using DOS line endings. Change-Id: Ie2f148867d9b2b386d556583afb6716ec21399e9 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- CorebootPayloadPkg/CorebootPayloadPkg.fdf| 84 ++--- CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 412 +++--- CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 419 +++ 3 files changed, 455 insertions(+), 460 deletions(-) diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf index 85748a6..7b52f40 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf +++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf @@ -1,16 +1,16 @@ ## @file # Coreboot Payload Package # -# Provides drivers and definitions to create uefi payload for coreboot. +# Provides drivers and definitions to create uefi payload for coreboot. # -# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved. -# This program and the accompanying materials are licensed and made available under -# the terms and conditions of the BSD License that accompanies this distribution. +# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved. +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License that accompanies this distribution. # The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. # ## @@ -93,31 +93,31 @@ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf -INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf -INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf +INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf +INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf -INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf +INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf -INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf -INF CorebootModulePkg/CbSupportDxe/CbSupportDxe.inf +INF CorebootModulePkg/CbSupportDxe/CbSupportDxe.inf INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf # # PCI Support # -INF CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf -INF CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf -INF CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.inf +INF CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf +INF CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf +INF CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.inf # # ISA Support # -INF CorebootModulePkg/SerialDxe/SerialDxe.inf +INF CorebootModulePkg/SerialDxe/SerialDxe.inf # # Console Support @@ -133,13 +133,13 @@ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf -INF CorebootModulePkg/SataControllerDxe/SataControllerDxe.inf +INF CorebootModulePkg/SataControllerDxe/SataControllerDxe.inf INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf -INF FatPkg/EnhancedFatDxe/Fat.inf +INF FatPkg/EnhancedFatDxe/Fat.inf # # Usb Support @@ -154,40 +154,40 @@ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf # # Shell # -!if $(SHELL_TYPE) == BUILD_SHELL -INF ShellPkg/Application/Shell/Shell.inf -!endif - -!if $(SHELL_TYPE) == FULL_BIN +!if $(SHELL_TYPE) == BUILD_SHELL +INF ShellPkg/Application/Shell/Shell.inf +!endif + +!if $(SHELL_TYPE) == FULL_BIN !if $(ARCH) == IA32 INF RuleOverride = BINARY USE = IA32 EdkShellBinP
[edk2] [PATCH 5/6] CorebootPayloadPkg/PciBusNoEnumerationDxe: Skip disabled devices
Skip non-bridge devices which are not enabled either for memory or I/O
access.
Change-Id: I1a39c69a8556b6b9cefd1a2bb191f7e0744ddfb0
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
b/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
index 0b0247d..58b9385 100644
--- a/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
+++ b/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
@@ -227,6 +227,15 @@ Returns:
if (!EFI_ERROR (Status)) {
//
+// Skip non-bridge devices which are not enabled
+//
+if (((Pci.Hdr.Command & (EFI_PCI_COMMAND_IO_SPACE
+ | EFI_PCI_COMMAND_MEMORY_SPACE)) == 0)
+ && (!(IS_PCI_BRIDGE () || IS_CARDBUS_BRIDGE ( {
+ continue;
+}
+
+//
// Collect all the information about the PCI device discovered
//
Status = PciSearchDevice (
--
1.9.1
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[edk2] [PATCH 6/6] CorebootPayloadPkg/PlatformBdsLib: Pass more serial parameters
Pass the serial port baudrate, register stride, input clock rate and
ID from coreboot to CorebootPayloadPkg.
Change-Id: I37111d23216e4effa2909337af7e8a6de36b61f7
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
CorebootModulePkg/Include/Coreboot.h | 17 ++-
CorebootModulePkg/Include/Library/CbParseLib.h | 26 +++
CorebootModulePkg/Library/CbParseLib/CbParseLib.c | 54 ++
.../Library/PlatformBdsLib/BdsPlatform.c | 7 ++-
.../Library/PlatformBdsLib/PlatformBdsLib.inf | 6 +++
.../Library/PlatformHookLib/PlatformHookLib.c | 53 -
.../Library/PlatformHookLib/PlatformHookLib.inf| 12 +++--
7 files changed, 140 insertions(+), 35 deletions(-)
diff --git a/CorebootModulePkg/Include/Coreboot.h
b/CorebootModulePkg/Include/Coreboot.h
index f2f18be..b622e6f 100644
--- a/CorebootModulePkg/Include/Coreboot.h
+++ b/CorebootModulePkg/Include/Coreboot.h
@@ -80,7 +80,7 @@ struct imd_root {
UINT32 max_entries;
UINT32 num_entries;
UINT32 flags;
- UINT32 entry_align;
+ UINT32 entry_align;
UINT32 max_offset;
struct imd_entry entries[0];
};
@@ -165,6 +165,21 @@ struct cb_serial {
UINT32 type;
UINT32 baseaddr;
UINT32 baud;
+ UINT32 regwidth;
+
+ // Crystal or input frequency to the chip containing the UART.
+ // Provide the board specific details to allow the payload to
+ // initialize the chip containing the UART and make independent
+ // decisions as to which dividers to select and their values
+ // to eventually arrive at the desired console baud-rate.
+ UINT32 input_hertz;
+
+ // UART PCI address: bus, device, function
+ // 1 << 31 - Valid bit, PCI UART in use
+ // Bus << 20
+ // Device << 15
+ // Function << 12
+ UINT32 uart_pci_addr;
};
#define CB_TAG_CONSOLE 0x00010
diff --git a/CorebootModulePkg/Include/Library/CbParseLib.h
b/CorebootModulePkg/Include/Library/CbParseLib.h
index 170375b..5550373 100644
--- a/CorebootModulePkg/Include/Library/CbParseLib.h
+++ b/CorebootModulePkg/Include/Library/CbParseLib.h
@@ -30,7 +30,7 @@ CbParseMemoryInfo (
IN UINT64*pLowMemorySize,
IN UINT64*pHighMemorySize
);
-
+
/**
Acquire the coreboot memory table with the given table id
@@ -45,11 +45,11 @@ CbParseMemoryInfo (
**/
RETURN_STATUS
CbParseCbMemTable (
- IN UINT32 TableId,
+ IN UINT32 TableId,
IN VOID** pMemTable,
IN UINT32*pMemTableSize
);
-
+
/**
Acquire the acpi table from coreboot
@@ -66,7 +66,7 @@ CbParseAcpiTable (
IN VOID** pMemTable,
IN UINT32*pMemTableSize
);
-
+
/**
Acquire the smbios table from coreboot
@@ -83,7 +83,7 @@ CbParseSmbiosTable (
IN VOID** pMemTable,
IN UINT32*pMemTableSize
);
-
+
/**
Find the required fadt information
@@ -107,13 +107,16 @@ CbParseFadtInfo (
IN UINTN* pPmEvtReg,
IN UINTN* pPmGpeEnReg
);
-
+
/**
Find the serial port information
@param pRegBase Pointer to the base address of serial port
registers
@param pRegAccessType Pointer to the access type of serial port
registers
+ @param pRegWidth Pointer to the register width in bytes
@param pBaudrate Pointer to the serial port baudrate
+ @param pInputHertzPointer to the input clock frequency
+ @param pUartPciAddr Pointer to the UART PCI bus, dev and func address
@retval RETURN_SUCCESS Successfully find the serial port information.
@retval RETURN_NOT_FOUND Failed to find the serial port information .
@@ -121,9 +124,12 @@ CbParseFadtInfo (
**/
RETURN_STATUS
CbParseSerialInfo (
- IN UINT32* pRegBase,
- IN UINT32* pRegAccessType,
- IN UINT32* pBaudrate
+ OUT UINT32 *pRegBase,
+ OUT UINT32 *pRegAccessType,
+ OUT UINT32 *pRegWidth,
+ OUT UINT32 *pBaudrate,
+ OUT UINT32 *pInputHertz,
+ OUT UINT32 *pUartPciAddr
);
/**
@@ -141,7 +147,7 @@ CbParseGetCbHeader (
IN UINTN Level,
IN VOID** HeaderPtr
);
-
+
/**
Find the video frame buffer information
diff --git a/CorebootModulePkg/Library/CbParseLib/CbParseLib.c
b/CorebootModulePkg/Library/CbParseLib/CbParseLib.c
index 377abf3..ad183b8 100644
--- a/CorebootModulePkg/Library/CbParseLib/CbParseLib.c
+++ b/CorebootModulePkg/Library/CbParseLib/CbParseLib.c
@@ -33,7 +33,7 @@
@return the UNIT64 value after convertion.
**/
-UINT64
+UINT64
cb_unpack64 (
IN struct cbuint64 val
)
@@ -216,8 +216,8 @@ FindCbMemTable (
*pMemTableSize = Entries[Idx].size;
}
- DEBUG ((EFI_D_INFO, "Find CbMemTable Id 0x%x, base %p, size 0x%x\n",
-TableId, *pMemTable, Entries[Idx].size));
+ DEBUG ((EFI_D_INFO, "Find CbMemTable Id 0x%x, base %p, size 0x%x\n",
+TableId, *pMemTable, Entries[Idx].size));
return RETURN_SUCCESS;
[edk2] [PATCH 4/6] CorebootModulePkg/PciBusNoEnumerationDxe: Remove white space
Remove trailing white space from PciEnumeratorSupport.c.
Change-Id: Ia2f354151d46c09b140e2b42609d76fbbf8333f9
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
.../PciBusNoEnumerationDxe/PciEnumeratorSupport.c | 92 +++---
1 file changed, 46 insertions(+), 46 deletions(-)
diff --git a/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
b/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
index 27311fd..0b0247d 100644
--- a/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
+++ b/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
@@ -2,18 +2,18 @@
Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.
(C) Copyright 2015 Hewlett Packard Enterprise Development LP
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD
License
-which accompanies this distribution. The full text of the license may be
found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
PciEnumeratorSupport.c
-
+
Abstract:
PCI Bus Driver
@@ -24,17 +24,17 @@ Revision History
#include "PciBus.h"
-EFI_STATUS
+EFI_STATUS
InitializePPB (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
-EFI_STATUS
+EFI_STATUS
InitializeP2C (
- IN PCI_IO_DEVICE *PciIoDevice
+ IN PCI_IO_DEVICE *PciIoDevice
);
-PCI_IO_DEVICE*
+PCI_IO_DEVICE*
CreatePciIoDevice (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci,
@@ -72,12 +72,12 @@ PciSearchDevice (
);
-EFI_STATUS
+EFI_STATUS
DetermineDeviceAttribute (
IN PCI_IO_DEVICE *PciIoDevice
);
-EFI_STATUS
+EFI_STATUS
BarExisted (
IN PCI_IO_DEVICE *PciIoDevice,
IN UINTN Offset,
@@ -90,10 +90,10 @@ BarExisted (
EFI_DEVICE_PATH_PROTOCOL*
CreatePciDevicePath(
IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
- IN PCI_IO_DEVICE*PciIoDevice
+ IN PCI_IO_DEVICE*PciIoDevice
);
-PCI_IO_DEVICE*
+PCI_IO_DEVICE*
GatherDeviceInfo (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci,
@@ -102,7 +102,7 @@ GatherDeviceInfo (
UINT8 Func
);
-PCI_IO_DEVICE*
+PCI_IO_DEVICE*
GatherPPBInfo (
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,
IN PCI_TYPE00 *Pci,
@@ -255,7 +255,7 @@ Returns:
if (EFI_ERROR (Status)) {
return Status;
}
-
+
//
// If the PCI bridge is initialized then enumerate the next level bus
//
@@ -368,15 +368,15 @@ Returns:
if (!PciIoDevice) {
return EFI_OUT_OF_RESOURCES;
}
-
+
//
// Create a device path for this PCI device and store it into its private
data
//
CreatePciDevicePath(
Bridge->DevicePath,
-PciIoDevice
+PciIoDevice
);
-
+
//
// Detect this function has option rom
//
@@ -389,8 +389,8 @@ Returns:
}
ResetPowerManagementFeature (PciIoDevice);
-
- }
+
+ }
else {
PciRomGetRomResourceFromPciOptionRomTable (
,
@@ -399,7 +399,7 @@ Returns:
);
}
-
+
//
// Insert it into a global tree for future reference
//
@@ -509,7 +509,7 @@ Returns:
if (!PciIoDevice) {
return NULL;
}
-
+
if (gFullEnumeration) {
PciDisableCommandRegister (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
@@ -593,7 +593,7 @@ Returns:
--*/
{
PCI_IO_DEVICE *PciIoDevice;
-
+
PciIoDevice = CreatePciIoDevice (
PciRootBridgeIo,
Pci,
@@ -619,7 +619,7 @@ Returns:
// P2C only has one bar that is in 0x10
//
PciParseBar(PciIoDevice, 0x10, 0);
-
+
PciIoDevice->Decodes = EFI_BRIDGE_MEM32_DECODE_SUPPORTED |
EFI_BRIDGE_PMEM32_DECODE_SUPPORTED |
EFI_BRIDGE_IO32_DECODE_SUPPORTED;
@@ -742,7 +742,7 @@ DetermineDeviceAttribute (
/*++
Routine Description:
-
+
Determine the related attributes of all devices u
[edk2] [PATCH 1/6] CorebootModulePkg: Add BaseSerialPortLib16550
Copy MdeModulePkg/Library/BaseSerialPortLib16550 revision
89ecd4cf8078aa946083cdcbf9af81ff29f8d9f5.
Change-Id: Ie2fd0123bdd7aaba4335afdb1cb017f3690455c6
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
.../BaseSerialPortLib16550.c | 1094
.../BaseSerialPortLib16550.inf | 48 +
.../BaseSerialPortLib16550.uni | 22 +
3 files changed, 1164 insertions(+)
create mode 100644
CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
create mode 100644
CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
create mode 100644
CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.uni
diff --git
a/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
b/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
new file mode 100644
index 000..0ccac96
--- /dev/null
+++ b/CorebootModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
@@ -0,0 +1,1094 @@
+/** @file
+ 16550 UART Serial Port library functions
+
+ (C) Copyright 2014 Hewlett-Packard Development Company, L.P.
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
License
+ which accompanies this distribution. The full text of the license may be
found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+//
+// PCI Defintions.
+//
+#define PCI_BRIDGE_32_BIT_IO_SPACE 0x01
+
+//
+// 16550 UART register offsets and bitfields
+//
+#define R_UART_RXBUF 0
+#define R_UART_TXBUF 0
+#define R_UART_BAUD_LOW 0
+#define R_UART_BAUD_HIGH 1
+#define R_UART_FCR2
+#define B_UART_FCR_FIFOEBIT0
+#define B_UART_FCR_FIFO64 BIT5
+#define R_UART_LCR3
+#define B_UART_LCR_DLAB BIT7
+#define R_UART_MCR4
+#define B_UART_MCR_DTRC BIT0
+#define B_UART_MCR_RTS BIT1
+#define R_UART_LSR5
+#define B_UART_LSR_RXRDYBIT0
+#define B_UART_LSR_TXRDYBIT5
+#define B_UART_LSR_TEMT BIT6
+#define R_UART_MSR6
+#define B_UART_MSR_CTS BIT4
+#define B_UART_MSR_DSR BIT5
+#define B_UART_MSR_RI BIT6
+#define B_UART_MSR_DCD BIT7
+
+//
+// 4-byte structure for each PCI node in PcdSerialPciDeviceInfo
+//
+typedef struct {
+ UINT8 Device;
+ UINT8 Function;
+ UINT16 PowerManagementStatusAndControlRegister;
+} PCI_UART_DEVICE_INFO;
+
+/**
+ Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value
is read from
+ MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O
space. The
+ parameter Offset is added to the base address of the 16550 registers that is
specified
+ by PcdSerialRegisterBase.
+
+ @param BaseThe base address register of UART device.
+ @param Offset The offset of the 16550 register to read.
+
+ @return The value read from the 16550 register.
+
+**/
+UINT8
+SerialPortReadRegister (
+ UINTN Base,
+ UINTN Offset
+ )
+{
+ if (PcdGetBool (PcdSerialUseMmio)) {
+return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
+ } else {
+return IoRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));
+ }
+}
+
+/**
+ Write an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value
is written to
+ MMIO space. If PcdSerialUseMmio is FALSE, then the value is written to I/O
space. The
+ parameter Offset is added to the base address of the 16550 registers that is
specified
+ by PcdSerialRegisterBase.
+
+ @param BaseThe base address register of UART device.
+ @param Offset The offset of the 16550 register to write.
+ @param Value The value to write to the 16550 register specified by Offset.
+
+ @return The value written to the 16550 register.
+
+**/
+UINT8
+SerialPortWriteRegister (
+ UINTN Base,
+ UINTN Offset,
+ UINT8 Value
+ )
+{
+ if (PcdGetBool (PcdSerialUseMmio)) {
+return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride),
Value);
+ } else {
+return IoWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride),
Value);
+ }
+}
+
+/**
+ Update the value of an 16-bit PCI configuration register in a PCI device.
If the
+ PCI Configuration register specified by PciAddress is already programmed
with a
+ non-zero value, then return the current value. Otherwise update the PCI
configuration
+ register specified by PciAddress with the value specified by Value and
return the
+ value program
[edk2] [PATCH 7/7] CorebootPayloadPkg: Use serial drivers with PlatformHookLib
Use the serial drivers which update the serial PCDs from
PlatformHookLib.
Change-Id: Ie6a3526d56332ee1cf07edb24ff39634a981183f
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
CorebootPayloadPkg/CorebootPayloadPkg.fdf| 39
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 3 +-
CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 3 +-
3 files changed, 24 insertions(+), 21 deletions(-)
diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
index 2072602..bb8d1f6 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
@@ -1,16 +1,16 @@
## @file
# Coreboot Payload Package
#
-# Provides drivers and definitions to create uefi payload for coreboot.
+# Provides drivers and definitions to create uefi payload for coreboot.
#
-# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
-# This program and the accompanying materials are licensed and made available
under
-# the terms and conditions of the BSD License that accompanies this
distribution.
+# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+# This program and the accompanying materials are licensed and made available
under
+# the terms and conditions of the BSD License that accompanies this
distribution.
# The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
@@ -93,30 +93,31 @@ INF
MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
INF
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
-INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
-INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
+INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
-INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
+INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
-INF CorebootModulePkg/CbSupportDxe/CbSupportDxe.inf
+INF CorebootModulePkg/CbSupportDxe/CbSupportDxe.inf
INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
#
# PCI Support
#
-INF
CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf
-INF CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
+INF
CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf
+INF CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
+INF CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.inf
#
# ISA Support
#
-INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+INF CorebootModulePkg/SerialDxe/SerialDxe.inf
#
# Console Support
@@ -132,13 +133,13 @@ INF
MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
-INF CorebootModulePkg/SataControllerDxe/SataControllerDxe.inf
+INF CorebootModulePkg/SataControllerDxe/SataControllerDxe.inf
INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
-INF FatPkg/EnhancedFatDxe/Fat.inf
+INF FatPkg/EnhancedFatDxe/Fat.inf
#
# Usb Support
@@ -186,7 +187,7 @@ FILE FREEFORM=
PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) {
}
#
-# Framebuffer Gop
+# Framebuffer Gop
#
INF CorebootPayloadPkg/FbGop/FbGop.inf
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index e0c14f3..e1420fe 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -388,6 +388,7 @@
[edk2] [PATCH 6/7] CorebootModulePkg/SerialDxe: Use PlatformHookLib
Copy the driver from MdeModulePkg/Universal/SerialDxe. Add PlatformHookLib to the Library section of the .inf file to adjust the PCDs for the UART. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- CorebootModulePkg/SerialDxe/SerialDxe.inf | 55 +++ CorebootModulePkg/SerialDxe/SerialDxe.uni | 21 + CorebootModulePkg/SerialDxe/SerialDxeExtra.uni | 19 + CorebootModulePkg/SerialDxe/SerialIo.c | 528 + 4 files changed, 623 insertions(+) create mode 100644 CorebootModulePkg/SerialDxe/SerialDxe.inf create mode 100644 CorebootModulePkg/SerialDxe/SerialDxe.uni create mode 100644 CorebootModulePkg/SerialDxe/SerialDxeExtra.uni create mode 100644 CorebootModulePkg/SerialDxe/SerialIo.c diff --git a/CorebootModulePkg/SerialDxe/SerialDxe.inf b/CorebootModulePkg/SerialDxe/SerialDxe.inf new file mode 100644 index 000..8489e06 --- /dev/null +++ b/CorebootModulePkg/SerialDxe/SerialDxe.inf @@ -0,0 +1,55 @@ +## @file +# Serial driver that layers on top of a Serial Port Library instance. +# +# Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved. +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +## + +[Defines] + INF_VERSION= 0x00010005 + BASE_NAME = SerialDxe + MODULE_UNI_FILE= SerialDxe.uni + FILE_GUID = D3987D4B-971A-435F-8CAF-4967EB627241 + MODULE_TYPE= DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT= SerialDxeInitialize + +[Sources.common] + SerialIo.c + +[Packages] + MdePkg/MdePkg.dec + CorebootModulePkg/CorebootModulePkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiBootServicesTableLib + DebugLib + PcdLib + PlatformHookLib + SerialPortLib + +[Protocols] + gEfiSerialIoProtocolGuid ## PRODUCES + gEfiDevicePathProtocolGuid## PRODUCES + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits ## CONSUMES + +[Depex] + TRUE + +[UserExtensions.TianoCore."ExtraFiles"] + SerialDxeExtra.uni diff --git a/CorebootModulePkg/SerialDxe/SerialDxe.uni b/CorebootModulePkg/SerialDxe/SerialDxe.uni new file mode 100644 index 000..e2daf27 --- /dev/null +++ b/CorebootModulePkg/SerialDxe/SerialDxe.uni @@ -0,0 +1,21 @@ +// /** @file +// Serial driver that layers on top of a Serial Port Library instance. +// +// Serial driver that layers on top of a Serial Port Library instance. +// +// Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Serial driver that layers on top of a Serial Port Library instance" + +#string STR_MODULE_DESCRIPTION #language en-US "Serial driver that layers on top of a Serial Port Library instance." + diff --git a/CorebootModulePkg/SerialDxe/SerialDxeExtra.uni b/CorebootModulePkg/SerialDxe/SerialDxeExtra.uni new file mode 100644 index 000..3790487 --- /dev/null +++ b/CorebootModulePkg/SerialDxe/SerialDxeExtra.uni @@ -0,0 +1,19 @@ +// /** @file +// SerialDxe Localized Strings and Content +// +// Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"SerialDxe Driver" + + diff --git a/CorebootModulePkg/SerialDxe/SerialIo.c b/CorebootModulePkg/SerialDxe/SerialIo.c new file mode 100644 index 000..171eb46 --- /dev/null +++ b/Coreboot
[edk2] [PATCH 4/7] CorebootPayloadPkg: Allow MaxLogicalProcessorNumber to be changed
Add a define and use it with MaxLogicalProcessorNumber to enable this PCD to be changed via the command line. Quark needs to set this value to one during the builds. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 7 +++ CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 7 +++ 2 files changed, 14 insertions(+) diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc index 7c9a1eb..e0c14f3 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc @@ -34,6 +34,11 @@ DEFINE SOURCE_DEBUG_ENABLE = FALSE # + # CPU options + # + DEFINE MAX_LOGICAL_PROCESSORS = 64 + + # # Serial port set up # DEFINE BAUD_RATE= 115200 @@ -281,6 +286,8 @@ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE) gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS) + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS) + # # Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc index 884a4e2..540d591 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc @@ -34,6 +34,11 @@ DEFINE SOURCE_DEBUG_ENABLE = FALSE # + # CPU options + # + DEFINE MAX_LOGICAL_PROCESSORS = 64 + + # # Serial port set up # DEFINE BAUD_RATE= 115200 @@ -286,6 +291,8 @@ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE) gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS) + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS) + # # Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform -- 1.9.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 5/7] CorebootModulePkg/PciSioSerialDxe: Use PlatformHookLib
Copy the driver from MdeModulePkg/Bus/Pci/PciSioSerialDxe. Add
PlatformHookLib to the Library section of the .inf file to adjust the
PCDs for the UART.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
CorebootModulePkg/PciSioSerialDxe/ComponentName.c | 288 +
.../PciSioSerialDxe/PciSioSerialDxe.inf| 82 ++
.../PciSioSerialDxe/PciSioSerialDxe.uni| 21 +
.../PciSioSerialDxe/PciSioSerialDxeExtra.uni | 18 +
CorebootModulePkg/PciSioSerialDxe/Serial.c | 1248 ++
CorebootModulePkg/PciSioSerialDxe/Serial.h | 789
CorebootModulePkg/PciSioSerialDxe/SerialIo.c | 1320
7 files changed, 3766 insertions(+)
create mode 100644 CorebootModulePkg/PciSioSerialDxe/ComponentName.c
create mode 100644 CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.inf
create mode 100644 CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.uni
create mode 100644 CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxeExtra.uni
create mode 100644 CorebootModulePkg/PciSioSerialDxe/Serial.c
create mode 100644 CorebootModulePkg/PciSioSerialDxe/Serial.h
create mode 100644 CorebootModulePkg/PciSioSerialDxe/SerialIo.c
diff --git a/CorebootModulePkg/PciSioSerialDxe/ComponentName.c
b/CorebootModulePkg/PciSioSerialDxe/ComponentName.c
new file mode 100644
index 000..994dc84
--- /dev/null
+++ b/CorebootModulePkg/PciSioSerialDxe/ComponentName.c
@@ -0,0 +1,288 @@
+/** @file
+ UEFI Component Name and Name2 protocol for Isa serial driver.
+
+Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "Serial.h"
+
+//
+// EFI Component Name Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL
gPciSioSerialComponentName = {
+ SerialComponentNameGetDriverName,
+ SerialComponentNameGetControllerName,
+ "eng"
+};
+
+//
+// EFI Component Name 2 Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL
gPciSioSerialComponentName2 = {
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) SerialComponentNameGetDriverName,
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)
SerialComponentNameGetControllerName,
+ "en"
+};
+
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE
mSerialDriverNameTable[] = {
+ {
+"eng;en",
+L"PCI SIO Serial Driver"
+ },
+ {
+NULL,
+NULL
+ }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 mSioSerialPortName[] = L"SIO Serial Port
#%d";
+GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 mPciSerialPortName[] = L"PCI Serial Port
#%d";
+
+/**
+ Retrieves a Unicode string that is the user readable name of the driver.
+
+ This function retrieves the user readable name of a driver in the form of a
+ Unicode string. If the driver specified by This has a user readable name in
+ the language specified by Language, then a pointer to the driver name is
+ returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+ by This does not support the language specified by Language,
+ then EFI_UNSUPPORTED is returned.
+
+ @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL
or
+EFI_COMPONENT_NAME_PROTOCOL instance.
+
+ @param Language[in] A pointer to a Null-terminated ASCII string
+array indicating the language. This is the
+language of the driver name that the caller is
+requesting, and it must match one of the
+languages specified in SupportedLanguages. The
+number of languages supported by a driver is up
+to the driver writer. Language is specified
+in RFC 4646 or ISO 639-2 language code format.
+
+ @param DriverName[out] A pointer to the Unicode string to return.
+This Unicode string is the name of the
+driver specified by This in the language
+specified by Language.
+
+ @retval EFI_SUCCESS The Unicode string for the Driver specified by
+This and the language specified by Language was
+returned in DriverName.
+
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+
+ @retval EFI_INVALID_PARAMETER DriverName is
[edk2] [PATCH 3/7] CorebootPayloadPkg: Make serial I/O configurable
Allow the serial port configuration to be overriden from the command
line.
Make the debug serial PCDs patchable in module.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 73 ---
CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 74 +---
2 files changed, 131 insertions(+), 16 deletions(-)
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index 58cb063..7c9a1eb 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -34,6 +34,40 @@
DEFINE SOURCE_DEBUG_ENABLE = FALSE
#
+ # Serial port set up
+ #
+ DEFINE BAUD_RATE= 115200
+ DEFINE SERIAL_CLOCK_RATE= 1843200
+ DEFINE SERIAL_LINE_CONTROL = 3 # 8-bits, no parity
+ DEFINE SERIAL_HARDWARE_FLOW_CONTROL = FALSE
+ DEFINE SERIAL_DETECT_CABLE = FALSE
+ DEFINE SERIAL_FIFO_CONTROL = 7 # Enable FIFO
+ DEFINE SERIAL_EXTENDED_TX_FIFO_SIZE = 16
+ DEFINE UART_DEFAULT_BAUD_RATE = $(BAUD_RATE)
+ DEFINE UART_DEFAULT_DATA_BITS = 8
+ DEFINE UART_DEFAULT_PARITY = 1
+ DEFINE UART_DEFAULT_STOP_BITS = 1
+ DEFINE DEFAULT_TERMINAL_TYPE= 0
+
+ #
+ # typedef struct {
+ #UINT16 VendorId; ///< Vendor ID to match the PCI device. The
value 0x terminates the list of entries.
+ #UINT16 DeviceId; ///< Device ID to match the PCI device
+ #UINT32 ClockRate; ///< UART clock rate. Set to 0 for default
clock rate of 1843200 Hz
+ #UINT64 Offset;///< The byte offset into to the BAR
+ #UINT8 BarIndex; ///< Which BAR to get the UART base address
+ #UINT8 RegisterStride;///< UART register stride in bytes. Set to
0 for default register stride of 1 byte.
+ #UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set
to 0 for a default FIFO depth of 16 bytes.
+ #UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set
to 0 for a default FIFO depth of 16 bytes.
+ #UINT8 Reserved[2];
+ # } PCI_SERIAL_PARAMETER;
+ #
+ # Vendor Device Prog Interface 1, BAR #0, Offset 0, Stride = 1,
Clock 1843200 (0x1c2000)
+ #
+ # [Vendor] [Device]
[ClockRate---] [Offset---] [Bar] [Stride] [RxFifo]
[TxFifo] [Rsvd] [Vendor]
+ DEFINE PCI_SERIAL_PARAMETERS= {0x00,0x00, 0x00,0x00,
0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00,0x01, 0x0,0x0,
0x0,0x0, 0x0,0x0, 0xff,0xff}
+
+ #
# Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI]
#
DEFINE SHELL_TYPE = FULL_BIN
@@ -203,13 +237,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
[PcdsFixedAtBuild]
- gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x7
- gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x804F
-!if $(SOURCE_DEBUG_ENABLE)
- gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17
-!else
- gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
-!endif
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x1
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000
gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x1
@@ -221,8 +248,38 @@
!endif
[PcdsPatchableInModule.common]
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x7
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x804F
+!if $(SOURCE_DEBUG_ENABLE)
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+!endif
+
+ #
+ # The following parameters are set by Library/PlatformHookLib
+ #
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x03F8
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3f8
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|$(BAUD_RATE)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1
+
+ #
+ # Enable these parameters to be set on the command line
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|$(SERIAL_CLOCK_RATE)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|$(SERIAL_LINE_CONTROL)
+
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|$(SERIAL_HARDWARE_FLOW_CONTROL)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|$(SERIAL_DETECT_CABLE)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL)
+
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE)
+
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)
+ gEfiMdePkgToken
[edk2] [PATCH 1/7] CorebootPayloadPkg/PlatformHelperLib: Remove unreferenced function
Remove the PlatformFlashEraseWrite function which is not used within
CorebootPayloadPkg.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
.../Include/Library/PlatformHelperLib.h| 38 +-
.../Library/PlatformHelperLib/PlatformHelperDxe.c | 141 -
2 files changed, 1 insertion(+), 178 deletions(-)
diff --git a/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h
b/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h
index a6cc863..28dc096 100644
--- a/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h
+++ b/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h
@@ -1,7 +1,7 @@
/** @file
PlatformHelperLib function prototype definitions.
-Copyright (c) 2013 Intel Corporation.
+Copyright (c) 2013 - 2016 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
@@ -106,42 +106,6 @@ PlatformFlashLockPolicy (
IN CONST BOOLEANPreBootPolicy
);
-/**
- Erase and Write to platform flash.
-
- Routine accesses one flash block at a time, each access consists
- of an erase followed by a write of FLASH_BLOCK_SIZE. One or both
- of DoErase & DoWrite params must be TRUE.
-
- Limitations:-
-CpuWriteAddress must be aligned to FLASH_BLOCK_SIZE.
-DataSize must be a multiple of FLASH_BLOCK_SIZE.
-
- @param Smst If != NULL then InSmm and use to locate
- SpiProtocol.
- @param CpuWriteAddressAddress in CPU memory map of flash region.
- @param Data The buffer containing the data to be written.
- @param DataSize Amount of data to write.
- @param DoEraseEarse each block.
- @param DoWriteWrite to each block.
-
- @retval EFI_SUCCESSOperation successful.
- @retval EFI_NOT_READY Required resources not setup.
- @retval EFI_INVALID_PARAMETER Invalid parameter.
- @retval Others Unexpected error happened.
-
-**/
-EFI_STATUS
-EFIAPI
-PlatformFlashEraseWrite (
- IN VOID *Smst,
- IN UINTN CpuWriteAddress,
- IN UINT8 *Data,
- IN UINTN DataSize,
- IN BOOLEAN DoErase,
- IN BOOLEAN DoWrite
- );
-
/** Check if System booted with recovery Boot Stage1 image.
@retval TRUEIf system booted with recovery Boot Stage1 image.
diff --git a/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c
b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c
index 18dbd8b..441f760 100644
--- a/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c
+++ b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c
@@ -325,147 +325,6 @@ PlatformFlashLockPolicy (
}
}
-/**
- Erase and Write to platform flash.
-
- Routine accesses one flash block at a time, each access consists
- of an erase followed by a write of FLASH_BLOCK_SIZE. One or both
- of DoErase & DoWrite params must be TRUE.
-
- Limitations:-
-CpuWriteAddress must be aligned to FLASH_BLOCK_SIZE.
-DataSize must be a multiple of FLASH_BLOCK_SIZE.
-
- @param Smst If != NULL then InSmm and use to locate
- SpiProtocol.
- @param CpuWriteAddressAddress in CPU memory map of flash region.
- @param Data The buffer containing the data to be written.
- @param DataSize Amount of data to write.
- @param DoEraseEarse each block.
- @param DoWriteWrite to each block.
-
- @retval EFI_SUCCESSOperation successful.
- @retval EFI_NOT_READY Required resources not setup.
- @retval EFI_INVALID_PARAMETER Invalid parameter.
- @retval Others Unexpected error happened.
-
-**/
-EFI_STATUS
-EFIAPI
-PlatformFlashEraseWrite (
- IN VOID *Smst,
- IN UINTN CpuWriteAddress,
- IN UINT8 *Data,
- IN UINTN DataSize,
- IN BOOLEAN DoErase,
- IN BOOLEAN DoWrite
- )
-{
- EFI_STATUSStatus;
- UINT64CpuBaseAddress;
- SPI_INIT_INFO *SpiInfo;
- UINT8 *WriteBuf;
- UINTN Index;
- UINTN SpiWriteAddress;
- EFI_SPI_PROTOCOL *SpiProtocol;
-
- if (!DoErase && !DoWrite) {
-return EFI_INVALID_PARAMETER;
- }
- if (DoWrite && Data == NULL) {
-return EFI_INVALID_PARAMETER;
- }
- if ((CpuWriteAddress % FLASH_BLOCK_SIZE) != 0) {
-
[edk2] [PATCH 2/7] CorebootPayloadPkg: Make shell selectable
Add all of the shell options from ShellBinPkg including building the
shell from source.
Enable link time optimization for GCC debug builds to keep the size
under 0x3e.
Test: Use -DSHELL_TYPE=BUILD_SHELL command line options to build the
shell from source. Run the result on Galileo Gen2.
Change-Id: I1e12adb57960ac5e75e682073540a9322aa03081
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
CorebootPayloadPkg/CorebootPayloadPkg.fdf| 28 +++-
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 189 +++---
CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 193 ---
3 files changed, 287 insertions(+), 123 deletions(-)
diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
index 3cc5a4d..2072602 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
@@ -153,17 +153,33 @@ INF
MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
#
# Shell
#
-#!if $(ARCH) == IA32
-#INF RuleOverride = BINARY USE = IA32 ShellBinPkg/UefiShell/UefiShell.inf
-#!else
-#INF RuleOverride = BINARY USE = X64 ShellBinPkg/UefiShell/UefiShell.inf
-#!endif
-#
+!if $(SHELL_TYPE) == BUILD_SHELL
+INF ShellPkg/Application/Shell/Shell.inf
+!endif
+
+!if $(SHELL_TYPE) == FULL_BIN
!if $(ARCH) == IA32
INF RuleOverride = BINARY USE = IA32 EdkShellBinPkg/FullShell/FullShell.inf
!else
INF RuleOverride = BINARY USE = X64 EdkShellBinPkg/FullShell/FullShell.inf
!endif
+!endif
+
+!if $(SHELL_TYPE) == MIN_BIN
+!if $(ARCH) == IA32
+INF RuleOverride = BINARY USE = IA32 ShellBinPkg/MinUefiShell/MinUefiShell.inf
+!else
+INF RuleOverride = BINARY USE = X64 ShellBinPkg/MinUefiShell/MinUefiShell.inf
+!endif
+!endif
+
+!if $(SHELL_TYPE) == UEFI_BIN
+!if $(ARCH) == IA32
+INF RuleOverride = BINARY USE = IA32 ShellBinPkg/UefiShell/UefiShell.inf
+!else
+INF RuleOverride = BINARY USE = X64 ShellBinPkg/UefiShell/UefiShell.inf
+!endif
+!endif
FILE FREEFORM= PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) {
SECTION RAW = MdeModulePkg/Logo/Logo.bmp
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index 49afa73..58cb063 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -1,16 +1,16 @@
## @file
# Coreboot Payload Package
#
-# Provides drivers and definitions to create uefi payload for coreboot.
+# Provides drivers and definitions to create uefi payload for coreboot.
#
-# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
-# This program and the accompanying materials are licensed and made available
under
-# the terms and conditions of the BSD License that accompanies this
distribution.
+# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+# This program and the accompanying materials are licensed and made available
under
+# the terms and conditions of the BSD License that accompanies this
distribution.
# The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
@@ -23,16 +23,21 @@
PLATFORM_NAME = CorebootPayloadPkg
PLATFORM_GUID = F71608AB-D63D-4491-B744-A8C8CD96
PLATFORM_VERSION= 0.1
- DSC_SPECIFICATION = 0x00010005
+ DSC_SPECIFICATION = 0x00010005
SUPPORTED_ARCHITECTURES = IA32
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER= DEFAULT
OUTPUT_DIRECTORY= Build/CorebootPayloadPkgIA32
FLASH_DEFINITION=
CorebootPayloadPkg/CorebootPayloadPkg.fdf
-
+
DEFINE SECURE_BOOT_ENABLE = FALSE
DEFINE SOURCE_DEBUG_ENABLE = FALSE
-
+
+ #
+ # Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI]
+ #
+ DEFINE SHELL_TYPE = FULL_BIN
+
[BuildOptions]
GCC:*_UNIXGCC_*_CC_FLAGS = -DMDEPKG_NDEBUG
GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
@@ -65,7 +70,7 @@
#
# Basic
#
- BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf
SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
@@ -76,7 +81,7 @@
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
PeCoffGetEn
[edk2] [PATCH] CorebootPayloadPkg: Remove trailing white space
Remove trailing white space from existing .dsc and .fdf files.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
CorebootPayloadPkg/CorebootPayloadPkg.fdf| 35 ---
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 117 +++---
CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 119 +++
3 files changed, 132 insertions(+), 139 deletions(-)
diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
index bde5e7e..44df258 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
@@ -1,16 +1,16 @@
## @file
# Coreboot Payload Package
#
-# Provides drivers and definitions to create uefi payload for coreboot.
+# Provides drivers and definitions to create uefi payload for coreboot.
#
-# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
-# This program and the accompanying materials are licensed and made available
under
-# the terms and conditions of the BSD License that accompanies this
distribution.
+# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+# This program and the accompanying materials are licensed and made available
under
+# the terms and conditions of the BSD License that accompanies this
distribution.
# The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
IMPLIED.
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
@@ -93,25 +93,25 @@ INF
MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
INF
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
-INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
-INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
+INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
-INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
+INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
-INF CorebootModulePkg/CbSupportDxe/CbSupportDxe.inf
+INF CorebootModulePkg/CbSupportDxe/CbSupportDxe.inf
INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
#
# PCI Support
#
INF DuetPkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf
-INF DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
+INF DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
#
# ISA Support
@@ -132,13 +132,13 @@ INF
MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
-INF DuetPkg/SataControllerDxe/SataControllerDxe.inf
+INF DuetPkg/SataControllerDxe/SataControllerDxe.inf
INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
-INF FatPkg/EnhancedFatDxe/Fat.inf
+INF FatPkg/EnhancedFatDxe/Fat.inf
#
# Usb Support
@@ -170,7 +170,7 @@ FILE FREEFORM=
PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) {
}
#
-# Framebuffer Gop
+# Framebuffer Gop
#
INF CorebootPayloadPkg/FbGop/FbGop.inf
@@ -271,4 +271,3 @@ INF CorebootPayloadPkg/FbGop/FbGop.inf
FILE RAW = $(NAMED_GUID) {
RAW RAW|.raw
}
-
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index e725423..267da80 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -1,16 +1,16 @@
## @file
# Coreboot Payload Package
#
-# Provides drivers and definitions to create uefi payload for core
[edk2] [PATCH] QuarkPlatformPkg: Move baud rate setting to top of .dsc file
Move the baud rate setting to the top of the .dsc file. Use a single setting for each board. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- QuarkPlatformPkg/Quark.dsc| 25 - QuarkPlatformPkg/QuarkMin.dsc | 25 - 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/QuarkPlatformPkg/Quark.dsc b/QuarkPlatformPkg/Quark.dsc index c87bb17..2b8038e 100644 --- a/QuarkPlatformPkg/Quark.dsc +++ b/QuarkPlatformPkg/Quark.dsc @@ -46,6 +46,16 @@ DEFINE GALILEO = GEN2 # + # Specify the maximum baud rate for the board + # +!if $(GALILEO) == GEN1 + DEFINE BAUD_RATE = 460800 +!endif +!if $(GALILEO) == GEN2 + DEFINE BAUD_RATE = 921600 +!endif + + # # TPM 1.2 Hardware. Options are [NONE, LPC, ATMEL_I2C, INFINEON_I2C] # DEFINE TPM_12_HARDWARE = NONE @@ -342,12 +352,7 @@ !endif gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x18 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE000 -!if $(GALILEO) == GEN1 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|460800 -!endif -!if $(GALILEO) == GEN2 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|921600 -!endif + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(BAUD_RATE) gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 @@ -382,14 +387,8 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x9000B000 -!if $(GALILEO) == GEN1 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|460800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|$(BAUD_RATE) gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE -!endif -!if $(GALILEO) == GEN2 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|921600 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE -!endif gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE diff --git a/QuarkPlatformPkg/QuarkMin.dsc b/QuarkPlatformPkg/QuarkMin.dsc index f8a656e..7d89767 100644 --- a/QuarkPlatformPkg/QuarkMin.dsc +++ b/QuarkPlatformPkg/QuarkMin.dsc @@ -40,6 +40,16 @@ DEFINE PERFORMANCE_ENABLE = FALSE DEFINE LOGGING = FALSE + # + # Specify the maximum baud rate for the board + # +!if $(GALILEO) == GEN1 + DEFINE BAUD_RATE = 460800 +!endif +!if $(GALILEO) == GEN2 + DEFINE BAUD_RATE = 921600 +!endif + !if $(TARGET) == "DEBUG" DEFINE LOGGING = TRUE !endif @@ -311,12 +321,7 @@ !endif gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x18 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE000 -!if $(GALILEO) == GEN1 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|460800 -!endif -!if $(GALILEO) == GEN2 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|921600 -!endif + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(BAUD_RATE) gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 @@ -351,14 +356,8 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x9000B000 -!if $(GALILEO) == GEN1 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|460800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|$(BAUD_RATE) gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE -!endif -!if $(GALILEO) == GEN2 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|921600 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE -!endif gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE -- 1.9.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH] QuarkSocPkg/SDControllerDxe: Add EFIAPI to SetHighSpeedMode
Fix 64-bit build error detected with GCC4.8 due to inconsistent routine declaration and implementation. Add EFIAPI to fix the build error. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.c | 1 + 1 file changed, 1 insertion(+) diff --git a/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.c b/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.c index 18e85c8..2b5dbe6 100644 --- a/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.c +++ b/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDController.c @@ -244,6 +244,7 @@ GetErrorReason ( @return EFI_SUCCESS **/ EFI_STATUS +EFIAPI SetHighSpeedMode ( IN EFI_SD_HOST_IO_PROTOCOL*This, IN BOOLEANEnable -- 1.9.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 10/12] CorebootPayloadPkg: Allow MaxLogicalProcessorNumber to be changed
Add a define and use it with MaxLogicalProcessorNumber to enable this PCD to be changed via the command line. Quark needs to set this value to one during the builds. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 7 +++ CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 7 +++ 2 files changed, 14 insertions(+) diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc index 4bdd91b..cd66ebb 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc @@ -34,6 +34,11 @@ DEFINE SOURCE_DEBUG_ENABLE = FALSE # + # CPU options + # + DEFINE MAX_LOGICAL_PROCESSORS = 64 + + # # Serial port set up # DEFINE BAUD_RATE= 115200 @@ -281,6 +286,8 @@ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE) gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS) + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS) + # # Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc index 382b21a..f050b94 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc @@ -34,6 +34,11 @@ DEFINE SOURCE_DEBUG_ENABLE = FALSE # + # CPU options + # + DEFINE MAX_LOGICAL_PROCESSORS = 64 + + # # Serial port set up # DEFINE BAUD_RATE= 115200 @@ -284,6 +289,8 @@ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE) gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS) + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS) + # # Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform -- 1.9.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 11/12] CorebootPayloadPkg/PlatformHelperLib: Remove unreferenced function
Remove the PlatformFlashEraseWrite function which is not used within
CorebootPayloadPkg.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
.../Include/Library/PlatformHelperLib.h| 38 +-
.../Library/PlatformHelperLib/PlatformHelperDxe.c | 141 -
2 files changed, 1 insertion(+), 178 deletions(-)
diff --git a/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h
b/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h
index a6cc863..28dc096 100644
--- a/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h
+++ b/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h
@@ -1,7 +1,7 @@
/** @file
PlatformHelperLib function prototype definitions.
-Copyright (c) 2013 Intel Corporation.
+Copyright (c) 2013 - 2016 Intel Corporation.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
@@ -106,42 +106,6 @@ PlatformFlashLockPolicy (
IN CONST BOOLEANPreBootPolicy
);
-/**
- Erase and Write to platform flash.
-
- Routine accesses one flash block at a time, each access consists
- of an erase followed by a write of FLASH_BLOCK_SIZE. One or both
- of DoErase & DoWrite params must be TRUE.
-
- Limitations:-
-CpuWriteAddress must be aligned to FLASH_BLOCK_SIZE.
-DataSize must be a multiple of FLASH_BLOCK_SIZE.
-
- @param Smst If != NULL then InSmm and use to locate
- SpiProtocol.
- @param CpuWriteAddressAddress in CPU memory map of flash region.
- @param Data The buffer containing the data to be written.
- @param DataSize Amount of data to write.
- @param DoEraseEarse each block.
- @param DoWriteWrite to each block.
-
- @retval EFI_SUCCESSOperation successful.
- @retval EFI_NOT_READY Required resources not setup.
- @retval EFI_INVALID_PARAMETER Invalid parameter.
- @retval Others Unexpected error happened.
-
-**/
-EFI_STATUS
-EFIAPI
-PlatformFlashEraseWrite (
- IN VOID *Smst,
- IN UINTN CpuWriteAddress,
- IN UINT8 *Data,
- IN UINTN DataSize,
- IN BOOLEAN DoErase,
- IN BOOLEAN DoWrite
- );
-
/** Check if System booted with recovery Boot Stage1 image.
@retval TRUEIf system booted with recovery Boot Stage1 image.
diff --git a/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c
b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c
index 18dbd8b..441f760 100644
--- a/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c
+++ b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c
@@ -325,147 +325,6 @@ PlatformFlashLockPolicy (
}
}
-/**
- Erase and Write to platform flash.
-
- Routine accesses one flash block at a time, each access consists
- of an erase followed by a write of FLASH_BLOCK_SIZE. One or both
- of DoErase & DoWrite params must be TRUE.
-
- Limitations:-
-CpuWriteAddress must be aligned to FLASH_BLOCK_SIZE.
-DataSize must be a multiple of FLASH_BLOCK_SIZE.
-
- @param Smst If != NULL then InSmm and use to locate
- SpiProtocol.
- @param CpuWriteAddressAddress in CPU memory map of flash region.
- @param Data The buffer containing the data to be written.
- @param DataSize Amount of data to write.
- @param DoEraseEarse each block.
- @param DoWriteWrite to each block.
-
- @retval EFI_SUCCESSOperation successful.
- @retval EFI_NOT_READY Required resources not setup.
- @retval EFI_INVALID_PARAMETER Invalid parameter.
- @retval Others Unexpected error happened.
-
-**/
-EFI_STATUS
-EFIAPI
-PlatformFlashEraseWrite (
- IN VOID *Smst,
- IN UINTN CpuWriteAddress,
- IN UINT8 *Data,
- IN UINTN DataSize,
- IN BOOLEAN DoErase,
- IN BOOLEAN DoWrite
- )
-{
- EFI_STATUSStatus;
- UINT64CpuBaseAddress;
- SPI_INIT_INFO *SpiInfo;
- UINT8 *WriteBuf;
- UINTN Index;
- UINTN SpiWriteAddress;
- EFI_SPI_PROTOCOL *SpiProtocol;
-
- if (!DoErase && !DoWrite) {
-return EFI_INVALID_PARAMETER;
- }
- if (DoWrite && Data == NULL) {
-return EFI_INVALID_PARAMETER;
- }
- if ((CpuWriteAddress % FLASH_BLOCK_SIZE) != 0) {
-
[edk2] [PATCH 07/12] CorebootPayloadPkg: Make serial I/O configurable
Allow the serial port configuration to be overriden from the command
line.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 59 +++-
CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 58 ++-
2 files changed, 114 insertions(+), 3 deletions(-)
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index d5f4fb1..df6f9c1 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -34,6 +34,40 @@
DEFINE SOURCE_DEBUG_ENABLE = FALSE
#
+ # Serial port set up
+ #
+ DEFINE BAUD_RATE= 115200
+ DEFINE SERIAL_CLOCK_RATE= 1843200
+ DEFINE SERIAL_LINE_CONTROL = 3 # 8-bits, no parity
+ DEFINE SERIAL_HARDWARE_FLOW_CONTROL = FALSE
+ DEFINE SERIAL_DETECT_CABLE = FALSE
+ DEFINE SERIAL_FIFO_CONTROL = 7 # Enable FIFO
+ DEFINE SERIAL_EXTENDED_TX_FIFO_SIZE = 16
+ DEFINE UART_DEFAULT_BAUD_RATE = $(BAUD_RATE)
+ DEFINE UART_DEFAULT_DATA_BITS = 8
+ DEFINE UART_DEFAULT_PARITY = 1
+ DEFINE UART_DEFAULT_STOP_BITS = 1
+ DEFINE DEFAULT_TERMINAL_TYPE= 0
+
+ #
+ # typedef struct {
+ #UINT16 VendorId; ///< Vendor ID to match the PCI device. The
value 0x terminates the list of entries.
+ #UINT16 DeviceId; ///< Device ID to match the PCI device
+ #UINT32 ClockRate; ///< UART clock rate. Set to 0 for default
clock rate of 1843200 Hz
+ #UINT64 Offset;///< The byte offset into to the BAR
+ #UINT8 BarIndex; ///< Which BAR to get the UART base address
+ #UINT8 RegisterStride;///< UART register stride in bytes. Set to
0 for default register stride of 1 byte.
+ #UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set
to 0 for a default FIFO depth of 16 bytes.
+ #UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set
to 0 for a default FIFO depth of 16 bytes.
+ #UINT8 Reserved[2];
+ # } PCI_SERIAL_PARAMETER;
+ #
+ # Vendor Device Prog Interface 1, BAR #0, Offset 0, Stride = 1,
Clock 1843200 (0x1c2000)
+ #
+ # [Vendor] [Device]
[ClockRate---] [Offset---] [Bar] [Stride] [RxFifo]
[TxFifo] [Rsvd] [Vendor]
+ DEFINE PCI_SERIAL_PARAMETERS= {0x00,0x00, 0x00,0x00,
0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00,0x01, 0x0,0x0,
0x0,0x0, 0x0,0x0, 0xff,0xff}
+
+ #
# Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI]
#
DEFINE SHELL_TYPE = FULL_BIN
@@ -220,11 +254,32 @@
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17
!else
gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
-
!endif
+ #
+ # The following parameters are set by Library/PlatformHookLib
+ #
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x03F8
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3f8
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|$(BAUD_RATE)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1
+
+ #
+ # Enable these parameters to be set on the command line
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|$(SERIAL_CLOCK_RATE)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|$(SERIAL_LINE_CONTROL)
+
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|$(SERIAL_HARDWARE_FLOW_CONTROL)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|$(SERIAL_DETECT_CABLE)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL)
+
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE)
+
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|$(UART_DEFAULT_STOP_BITS)
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE)
+
gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS)
#
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index db6c97d..67b70f0 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -34,6 +34,40 @@
DEFINE SOURCE_DEBUG_ENABLE = FALSE
#
+ # Serial port set up
+ #
+ DEFINE BAUD_RATE= 115200
+ DEFINE SERIAL_CLOCK_RATE
[edk2] [PATCH 08/12] CorebootPayloadPkg: Use serial drivers with PlatformHookLib
Use the serial drivers which update the serial PCDs from PlatformHookLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- CorebootPayloadPkg/CorebootPayloadPkg.fdf| 3 ++- CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 11 ++- CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 9 + 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf index 804eeed..a386d50 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf +++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf @@ -112,11 +112,12 @@ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf # INF CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf INF CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf +INF CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.inf # # ISA Support # -INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf +INF CorebootModulePkg/SerialDxe/SerialDxe.inf # # Console Support diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc index df6f9c1..4bdd91b 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc @@ -158,7 +158,7 @@ SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf PlatformHookLib|CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf PlatformBdsLib|CorebootPayloadPkg/Library/PlatformBdsLib/PlatformBdsLib.inf - + # # Misc # @@ -381,7 +381,8 @@ # CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf - + CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.inf + # # SCSI/ATA/IDE/DISK Support # @@ -404,12 +405,12 @@ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf - + # # ISA Support # - MdeModulePkg/Universal/SerialDxe/SerialDxe.inf - + CorebootModulePkg/SerialDxe/SerialDxe.inf + # # Console Support # diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc index 67b70f0..382b21a 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc @@ -384,7 +384,8 @@ # CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf - + CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.inf + # # SCSI/ATA/IDE/DISK Support # @@ -407,12 +408,12 @@ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf - + # # ISA Support # - MdeModulePkg/Universal/SerialDxe/SerialDxe.inf - + CorebootModulePkg/SerialDxe/SerialDxe.inf + # # Console Support # -- 1.9.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 06/12] CorebootPayloadPkg: Make debug serial PCDs patchable
Make the debug serial PCDs patchable in module. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 16 +--- CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 16 +--- 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc index 88790e9..d5f4fb1 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc @@ -203,13 +203,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE [PcdsFixedAtBuild] - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x7 - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x804F -!if $(SOURCE_DEBUG_ENABLE) - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 -!else - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F -!endif gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x1 gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000 gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x1 @@ -221,6 +214,15 @@ !endif [PcdsPatchableInModule.common] + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x7 + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x804F +!if $(SOURCE_DEBUG_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F + +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x03F8 diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc index ef9f349..db6c97d 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc @@ -204,13 +204,6 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE [PcdsFixedAtBuild] - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x7 - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x804F -!if $(SOURCE_DEBUG_ENABLE) - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 -!else - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F -!endif gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x1 gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000 gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x1 @@ -223,6 +216,15 @@ !endif [PcdsPatchableInModule.common] + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x7 + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x804F +!if $(SOURCE_DEBUG_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x03F8 -- 1.9.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 05/12] CorebootPayloadPkg: Make shell selectable
Add all of the shell options from ShellBinPkg including building the
shell from source.
Test: Use -DSHELL_TYPE=BUILD_SHELL command line options to build the
shell from source. Run the result on Galileo Gen2.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
CorebootPayloadPkg/CorebootPayloadPkg.fdf| 24 +---
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc| 78 ++--
CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 78 ++--
3 files changed, 162 insertions(+), 18 deletions(-)
diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
index e28f732..804eeed 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
@@ -153,16 +153,20 @@ INF
MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
#
# Shell
#
-#!if $(ARCH) == IA32
-#INF RuleOverride = BINARY USE = IA32 ShellBinPkg/UefiShell/UefiShell.inf
-#!else
-#INF RuleOverride = BINARY USE = X64 ShellBinPkg/UefiShell/UefiShell.inf
-#!endif
-#
-!if $(ARCH) == IA32
-INF RuleOverride = BINARY USE = IA32 EdkShellBinPkg/FullShell/FullShell.inf
-!else
-INF RuleOverride = BINARY USE = X64 EdkShellBinPkg/FullShell/FullShell.inf
+!if $(SHELL_TYPE) == BUILD_SHELL
+INF ShellPkg/Application/Shell/Shell.inf
+!endif
+
+!if $(SHELL_TYPE) == FULL_BIN
+INF RuleOverride = BINARY USE = $(ARCH) EdkShellBinPkg/FullShell/FullShell.inf
+!endif
+
+!if $(SHELL_TYPE) == MIN_BIN
+INF RuleOverride = BINARY USE = $(ARCH)
ShellBinPkg/MinUefiShell/MinUefiShell.inf
+!endif
+
+!if $(SHELL_TYPE) == UEFI_BIN
+INF RuleOverride = BINARY USE = $(ARCH) ShellBinPkg/UefiShell/UefiShell.inf
!endif
FILE FREEFORM= PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) {
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index 42c2d20..88790e9 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -32,7 +32,12 @@
DEFINE SECURE_BOOT_ENABLE = FALSE
DEFINE SOURCE_DEBUG_ENABLE = FALSE
-
+
+ #
+ # Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI]
+ #
+ DEFINE SHELL_TYPE = FULL_BIN
+
[BuildOptions]
GCC:*_UNIXGCC_*_CC_FLAGS = -DMDEPKG_NDEBUG
GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
@@ -361,6 +366,71 @@
# Framebuffer Gop
#
CorebootPayloadPkg/FbGop/FbGop.inf
-
-
-
+
+ #--
+ # Build the shell
+ #--
+
+!if $(SHELL_TYPE) == BUILD_SHELL
+
+[PcdsFixedAtBuild]
+ ## This flag is used to control initialization of the shell library
+ # This should be FALSE for compiling the shell application itself only.
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+
+ #
+ # Shell Lib
+ #
+[LibraryClasses]
+
BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+
+[Components.IA32]
+ ShellPkg/Application/Shell/Shell.inf {
+
+#--
+# Basic commands
+#--
+
+
+
NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+
NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+
NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+
NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+
NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+
NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+
+#--
+# Networking commands
+#--
+
+
+
NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+
+#--
+# Performance command
+#--
+
+
+ NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf
+
+#--
+# Support libraries
+#--
+
+
+ DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+
HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+
ShellCommandLib|ShellPkg/L
[edk2] [PATCH 04/12] CorebootPayloadPkg/PciBusNoEnumerationDxe: Skip disabled devices
Skip non-bridge devices which are not enabled either for memory or I/O
access.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
b/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
index ca300cf..3802424 100644
--- a/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
+++ b/CorebootModulePkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
@@ -227,6 +227,15 @@ Returns:
if (!EFI_ERROR (Status)) {
//
+// Skip non-bridge devices which are not enabled
+//
+if (((Pci.Hdr.Command & (EFI_PCI_COMMAND_IO_SPACE
+ | EFI_PCI_COMMAND_MEMORY_SPACE)) == 0)
+ && (!(IS_PCI_BRIDGE () || IS_CARDBUS_BRIDGE ( {
+ continue;
+}
+
+//
// Collect all the information about the PCI device discovered
//
Status = PciSearchDevice (
--
1.9.1
___
edk2-devel mailing list
edk2-devel@lists.01.org
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[edk2] [PATCH 02/12] CorebootModulePkg/PciSioSerialDxe: Use PlatformHookLib
Copy the driver from MdeModulePkg/Bus/Pci/PciSioSerialDxe. Add
PlatformHookLib to the Library section of the .inf file to adjust the
PCDs for the UART.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
CorebootModulePkg/PciSioSerialDxe/ComponentName.c | 288 +
.../PciSioSerialDxe/PciSioSerialDxe.inf| 82 ++
.../PciSioSerialDxe/PciSioSerialDxe.uni| 21 +
.../PciSioSerialDxe/PciSioSerialDxeExtra.uni | 18 +
CorebootModulePkg/PciSioSerialDxe/Serial.c | 1248 ++
CorebootModulePkg/PciSioSerialDxe/Serial.h | 789
CorebootModulePkg/PciSioSerialDxe/SerialIo.c | 1320
7 files changed, 3766 insertions(+)
create mode 100644 CorebootModulePkg/PciSioSerialDxe/ComponentName.c
create mode 100644 CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.inf
create mode 100644 CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxe.uni
create mode 100644 CorebootModulePkg/PciSioSerialDxe/PciSioSerialDxeExtra.uni
create mode 100644 CorebootModulePkg/PciSioSerialDxe/Serial.c
create mode 100644 CorebootModulePkg/PciSioSerialDxe/Serial.h
create mode 100644 CorebootModulePkg/PciSioSerialDxe/SerialIo.c
diff --git a/CorebootModulePkg/PciSioSerialDxe/ComponentName.c
b/CorebootModulePkg/PciSioSerialDxe/ComponentName.c
new file mode 100644
index 000..994dc84
--- /dev/null
+++ b/CorebootModulePkg/PciSioSerialDxe/ComponentName.c
@@ -0,0 +1,288 @@
+/** @file
+ UEFI Component Name and Name2 protocol for Isa serial driver.
+
+Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD
License
+which accompanies this distribution. The full text of the license may be
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "Serial.h"
+
+//
+// EFI Component Name Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL
gPciSioSerialComponentName = {
+ SerialComponentNameGetDriverName,
+ SerialComponentNameGetControllerName,
+ "eng"
+};
+
+//
+// EFI Component Name 2 Protocol
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL
gPciSioSerialComponentName2 = {
+ (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) SerialComponentNameGetDriverName,
+ (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)
SerialComponentNameGetControllerName,
+ "en"
+};
+
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE
mSerialDriverNameTable[] = {
+ {
+"eng;en",
+L"PCI SIO Serial Driver"
+ },
+ {
+NULL,
+NULL
+ }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 mSioSerialPortName[] = L"SIO Serial Port
#%d";
+GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 mPciSerialPortName[] = L"PCI Serial Port
#%d";
+
+/**
+ Retrieves a Unicode string that is the user readable name of the driver.
+
+ This function retrieves the user readable name of a driver in the form of a
+ Unicode string. If the driver specified by This has a user readable name in
+ the language specified by Language, then a pointer to the driver name is
+ returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+ by This does not support the language specified by Language,
+ then EFI_UNSUPPORTED is returned.
+
+ @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL
or
+EFI_COMPONENT_NAME_PROTOCOL instance.
+
+ @param Language[in] A pointer to a Null-terminated ASCII string
+array indicating the language. This is the
+language of the driver name that the caller is
+requesting, and it must match one of the
+languages specified in SupportedLanguages. The
+number of languages supported by a driver is up
+to the driver writer. Language is specified
+in RFC 4646 or ISO 639-2 language code format.
+
+ @param DriverName[out] A pointer to the Unicode string to return.
+This Unicode string is the name of the
+driver specified by This in the language
+specified by Language.
+
+ @retval EFI_SUCCESS The Unicode string for the Driver specified by
+This and the language specified by Language was
+returned in DriverName.
+
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+
+ @retval EFI_INVALID_PARAMETER DriverName is
[edk2] [PATCH v2 8/9] QuarkPkg: Move baud rate setting to top of .dsc file
Move the baud rate setting to the top of the .dsc file. Use a single setting for each board. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- QuarkPlatformPkg/Quark.dsc| 25 - QuarkPlatformPkg/QuarkMin.dsc | 25 - 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/QuarkPlatformPkg/Quark.dsc b/QuarkPlatformPkg/Quark.dsc index c87bb17..2b8038e 100644 --- a/QuarkPlatformPkg/Quark.dsc +++ b/QuarkPlatformPkg/Quark.dsc @@ -46,6 +46,16 @@ DEFINE GALILEO = GEN2 # + # Specify the maximum baud rate for the board + # +!if $(GALILEO) == GEN1 + DEFINE BAUD_RATE = 460800 +!endif +!if $(GALILEO) == GEN2 + DEFINE BAUD_RATE = 921600 +!endif + + # # TPM 1.2 Hardware. Options are [NONE, LPC, ATMEL_I2C, INFINEON_I2C] # DEFINE TPM_12_HARDWARE = NONE @@ -342,12 +352,7 @@ !endif gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x18 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE000 -!if $(GALILEO) == GEN1 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|460800 -!endif -!if $(GALILEO) == GEN2 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|921600 -!endif + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(BAUD_RATE) gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 @@ -382,14 +387,8 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x9000B000 -!if $(GALILEO) == GEN1 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|460800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|$(BAUD_RATE) gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE -!endif -!if $(GALILEO) == GEN2 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|921600 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE -!endif gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE diff --git a/QuarkPlatformPkg/QuarkMin.dsc b/QuarkPlatformPkg/QuarkMin.dsc index f8a656e..7d89767 100644 --- a/QuarkPlatformPkg/QuarkMin.dsc +++ b/QuarkPlatformPkg/QuarkMin.dsc @@ -40,6 +40,16 @@ DEFINE PERFORMANCE_ENABLE = FALSE DEFINE LOGGING = FALSE + # + # Specify the maximum baud rate for the board + # +!if $(GALILEO) == GEN1 + DEFINE BAUD_RATE = 460800 +!endif +!if $(GALILEO) == GEN2 + DEFINE BAUD_RATE = 921600 +!endif + !if $(TARGET) == "DEBUG" DEFINE LOGGING = TRUE !endif @@ -311,12 +321,7 @@ !endif gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x18 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE000 -!if $(GALILEO) == GEN1 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|460800 -!endif -!if $(GALILEO) == GEN2 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|921600 -!endif + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(BAUD_RATE) gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 @@ -351,14 +356,8 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x9000B000 -!if $(GALILEO) == GEN1 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|460800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|$(BAUD_RATE) gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE -!endif -!if $(GALILEO) == GEN2 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|921600 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE -!endif gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE -- 1.9.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 8/9] QuarkPkg: Move baud rate setting to top of .dsc file
Move the baud rate setting to the top of the .dsc file. Use a single setting for each board. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- QuarkPlatformPkg/Quark.dsc| 25 - QuarkPlatformPkg/QuarkMin.dsc | 25 - 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/QuarkPlatformPkg/Quark.dsc b/QuarkPlatformPkg/Quark.dsc index c87bb17..2b8038e 100644 --- a/QuarkPlatformPkg/Quark.dsc +++ b/QuarkPlatformPkg/Quark.dsc @@ -46,6 +46,16 @@ DEFINE GALILEO = GEN2 # + # Specify the maximum baud rate for the board + # +!if $(GALILEO) == GEN1 + DEFINE BAUD_RATE = 460800 +!endif +!if $(GALILEO) == GEN2 + DEFINE BAUD_RATE = 921600 +!endif + + # # TPM 1.2 Hardware. Options are [NONE, LPC, ATMEL_I2C, INFINEON_I2C] # DEFINE TPM_12_HARDWARE = NONE @@ -342,12 +352,7 @@ !endif gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x18 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE000 -!if $(GALILEO) == GEN1 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|460800 -!endif -!if $(GALILEO) == GEN2 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|921600 -!endif + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(BAUD_RATE) gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 @@ -382,14 +387,8 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x9000B000 -!if $(GALILEO) == GEN1 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|460800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|$(BAUD_RATE) gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE -!endif -!if $(GALILEO) == GEN2 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|921600 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE -!endif gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE diff --git a/QuarkPlatformPkg/QuarkMin.dsc b/QuarkPlatformPkg/QuarkMin.dsc index f8a656e..7d89767 100644 --- a/QuarkPlatformPkg/QuarkMin.dsc +++ b/QuarkPlatformPkg/QuarkMin.dsc @@ -40,6 +40,16 @@ DEFINE PERFORMANCE_ENABLE = FALSE DEFINE LOGGING = FALSE + # + # Specify the maximum baud rate for the board + # +!if $(GALILEO) == GEN1 + DEFINE BAUD_RATE = 460800 +!endif +!if $(GALILEO) == GEN2 + DEFINE BAUD_RATE = 921600 +!endif + !if $(TARGET) == "DEBUG" DEFINE LOGGING = TRUE !endif @@ -311,12 +321,7 @@ !endif gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x18 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE000 -!if $(GALILEO) == GEN1 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|460800 -!endif -!if $(GALILEO) == GEN2 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|921600 -!endif + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(BAUD_RATE) gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 @@ -351,14 +356,8 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x9000B000 -!if $(GALILEO) == GEN1 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|460800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|$(BAUD_RATE) gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE -!endif -!if $(GALILEO) == GEN2 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|921600 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE -!endif gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE -- 1.9.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 8/9] QuarkPkg: Move baud rate setting to top of .dsc file
Move the baud rate setting to the top of the .dsc file. Use a single setting for each board. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.le...@intel.com> --- QuarkPlatformPkg/Quark.dsc | 28 +++- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/QuarkPlatformPkg/Quark.dsc b/QuarkPlatformPkg/Quark.dsc index c87bb17..c8952d8 100644 --- a/QuarkPlatformPkg/Quark.dsc +++ b/QuarkPlatformPkg/Quark.dsc @@ -46,6 +46,19 @@ DEFINE GALILEO = GEN2 # + # Specify the maximum baud rate for the board + # + DEFINE GEN1_BAUD_RATE = 460800 + DEFINE GEN2_BAUD_RATE = 921600 + +!if $(GALILEO) == GEN1 + BAUD_RATE = $(GEN1_BAUD_RATE) +!endif +!if $(GALILEO) == GEN2 + BAUD_RATE = $(GEN2_BAUD_RATE) +!endif + + # # TPM 1.2 Hardware. Options are [NONE, LPC, ATMEL_I2C, INFINEON_I2C] # DEFINE TPM_12_HARDWARE = NONE @@ -342,12 +355,7 @@ !endif gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x18 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE000 -!if $(GALILEO) == GEN1 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|460800 -!endif -!if $(GALILEO) == GEN2 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|921600 -!endif + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(BAUD_RATE) gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 @@ -382,14 +390,8 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x9000B000 -!if $(GALILEO) == GEN1 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|460800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|$(BAUD_RATE) gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE -!endif -!if $(GALILEO) == GEN2 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|921600 - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE -!endif gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07 gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE -- 1.9.1 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH 7/9] QuarkPlatformPkg/PlatformBootManagerLib: No non-countdown msgs
Disable the countdown messages which are displayed every second when the
timeout is specified as infinite (0x).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
a/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
b/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
index 19ff3d0..fff1c80 100644
--- a/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
+++ b/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
@@ -333,5 +333,7 @@ PlatformBootManagerWaitCallback (
UINT16 TimeoutRemain
)
{
- Print (L"\r%-2d seconds remained...", TimeoutRemain);
+ if (TimeoutRemain != 0x) {
+Print (L"\r%-2d seconds remained...", TimeoutRemain);
+ }
}
--
1.9.1
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[edk2] [PATCH 6/9] MdeModulePkg/BdsDxe: Eliminate non-countdown messages
Eliminate the message every one second when the timeout is specified
as infinite (0x).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
MdeModulePkg/Universal/BdsDxe/BdsEntry.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/MdeModulePkg/Universal/BdsDxe/BdsEntry.c
b/MdeModulePkg/Universal/BdsDxe/BdsEntry.c
index 3734ff9..dbe2cd6 100644
--- a/MdeModulePkg/Universal/BdsDxe/BdsEntry.c
+++ b/MdeModulePkg/Universal/BdsDxe/BdsEntry.c
@@ -233,7 +233,9 @@ BdsWait (
TimeoutRemain = PcdGet16 (PcdPlatformBootTimeOut);
while (TimeoutRemain != 0) {
-DEBUG ((EFI_D_INFO, "[Bds]BdsWait(%d)..Zzzz...\n", (UINTN) TimeoutRemain));
+if (TimeoutRemain != 0x) {
+ DEBUG ((EFI_D_INFO, "[Bds]BdsWait(%d)..Zzzz...\n", (UINTN)
TimeoutRemain));
+}
PlatformBootManagerWaitCallback (TimeoutRemain);
BdsReadKeys (); // BUGBUG: Only reading can signal HotkeyTriggered
--
1.9.1
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[edk2] [PATCH 5/9] MdeModulePkg/PciSioSerialDxe: Set RTS and DTR by default
Usually the debug serial connection only uses two wires. However when
the controller at the other end is honoring hardware flow control
signals, it is necessary for the PciSioSerialDxe to properly generate
the necessary signals. Turn on DTR and RTS during reset. Allow the
higher level application control these signals after the fact with the
SetControl interface.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c
b/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c
index f1870f3..07ee424 100644
--- a/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c
+++ b/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c
@@ -574,7 +574,7 @@ SerialReset (
//
// Go set the current control bits
//
- Control = 0;
+ Control = EFI_SERIAL_REQUEST_TO_SEND | EFI_SERIAL_DATA_TERMINAL_READY;
if (SerialDevice->HardwareFlowControl) {
Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
}
--
1.9.1
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[edk2] [PATCH 4/9] DuetPkg/PciBusNoEnumerationDxe: Skip disabled devices
Skip non-bridge devices which are not enabled either for memory or I/O
access.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
DuetPkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/DuetPkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
b/DuetPkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
index ca300cf..3802424 100644
--- a/DuetPkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
+++ b/DuetPkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
@@ -227,6 +227,15 @@ Returns:
if (!EFI_ERROR (Status)) {
//
+// Skip non-bridge devices which are not enabled
+//
+if (((Pci.Hdr.Command & (EFI_PCI_COMMAND_IO_SPACE
+ | EFI_PCI_COMMAND_MEMORY_SPACE)) == 0)
+ && (!(IS_PCI_BRIDGE () || IS_CARDBUS_BRIDGE ( {
+ continue;
+}
+
+//
// Collect all the information about the PCI device discovered
//
Status = PciSearchDevice (
--
1.9.1
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[edk2] [PATCH 3/9] CorebootPayloadPkg/PlatformBdsLib: Fix spelling error
Change vender to vendor
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c | 2 +-
CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.h | 4 ++--
CorebootPayloadPkg/Library/PlatformBdsLib/PlatformData.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c
b/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c
index fec14a3..a5027e5 100644
--- a/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c
+++ b/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.c
@@ -123,7 +123,7 @@ Returns:
//
// Register COM1
//
- DevicePath = AppendDevicePathNode ((EFI_DEVICE_PATH_PROTOCOL *)NULL,
(EFI_DEVICE_PATH_PROTOCOL *));
+ DevicePath = AppendDevicePathNode ((EFI_DEVICE_PATH_PROTOCOL *)NULL,
(EFI_DEVICE_PATH_PROTOCOL *));
DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL
*));
DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL
*));
diff --git a/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.h
b/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.h
index 641e1cb..b8a241c 100644
--- a/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.h
+++ b/CorebootPayloadPkg/Library/PlatformBdsLib/BdsPlatform.h
@@ -38,7 +38,7 @@ extern EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges[];
extern ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode;
extern UART_DEVICE_PATH gUartDeviceNode;
extern VENDOR_DEVICE_PATH gTerminalTypeDeviceNode;
-extern VENDOR_DEVICE_PATH gUartDeviceVenderNode;
+extern VENDOR_DEVICE_PATH gUartDeviceVendorNode;
//
//
@@ -83,7 +83,7 @@ extern VENDOR_DEVICE_PATH gUartDeviceVenderNode;
#define gPnp16550ComPort \
PNPID_DEVICE_PATH_NODE(0x0501)
-#define gUartVender \
+#define gUartVendor \
{ \
{ \
HARDWARE_DEVICE_PATH, \
diff --git a/CorebootPayloadPkg/Library/PlatformBdsLib/PlatformData.c
b/CorebootPayloadPkg/Library/PlatformBdsLib/PlatformData.c
index 4739c3c..c86e0e9 100644
--- a/CorebootPayloadPkg/Library/PlatformBdsLib/PlatformData.c
+++ b/CorebootPayloadPkg/Library/PlatformBdsLib/PlatformData.c
@@ -23,7 +23,7 @@ UINT16 gPlatformBootTimeOutDefault = 5;
ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode = gPnp16550ComPort;
UART_DEVICE_PATH gUartDeviceNode= gUart;
VENDOR_DEVICE_PATH gTerminalTypeDeviceNode= gPcAnsiTerminal;
-VENDOR_DEVICE_PATH gUartDeviceVenderNode = gUartVender;
+VENDOR_DEVICE_PATH gUartDeviceVendorNode = gUartVendor;
//
// Predefined platform root bridge
//
--
1.9.1
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[edk2] [PATCH 1/9] edksetup.sh: Create the Conf directory if necessary
Edit the shell script to determine if the Conf directory is present. If
not then create the Conf directory.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
edksetup.sh | 4
1 file changed, 4 insertions(+)
diff --git a/edksetup.sh b/edksetup.sh
index 57368b5..d89ef9d 100755
--- a/edksetup.sh
+++ b/edksetup.sh
@@ -72,6 +72,10 @@ function SetWorkspace()
function SetupEnv()
{
+ if [ ! -d "$WORKSPACE/Conf" ]
+ then
+mkdir $WORKSPACE/Conf
+ fi
if [ -n "$EDK_TOOLS_PATH" ]
then
. $EDK_TOOLS_PATH/BuildEnv $*
--
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[edk2] [PATCH v3] DuetPkg-PciBusNoEnumerationDxe: Fix stack overflow
When a PCI bridge is not enabled, the secondary bus may still be zero.
This causes an infinite recursive call to enumerate bus 0 which results
in a stack overflow. The easy fix is to skip the recursive bus
enumeration for devices which are not enabled either for memory or I/O
accesses.
TEST=Build and run CorebootPayloadPkg on Quark/Galileo Gen2
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
DuetPkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/DuetPkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
b/DuetPkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
index 80b2b6b..7f8393a 100644
--- a/DuetPkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
+++ b/DuetPkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
@@ -243,7 +243,9 @@ Returns:
//
//
-if (!EFI_ERROR (Status) && (IS_PCI_BRIDGE () || IS_CARDBUS_BRIDGE
())) {
+if (!EFI_ERROR (Status) && (Pci.Hdr.Command & (EFI_PCI_COMMAND_IO_SPACE
+| EFI_PCI_COMMAND_MEMORY_SPACE))
+ && (IS_PCI_BRIDGE () || IS_CARDBUS_BRIDGE ())) {
//
// If it is PPB, we need to get the secondary bus to continue the
enumeration
--
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[edk2] [PATCH v2] DuetPkg-PciBusNoEnumerationDxe: Fix stack overflow
When a PCI bridge is not enabled, the secondary bus may still be zero.
This causes an infinite recursive call to enumerate bus 0 which results
in a stack overflow. The easy fix is to have PciDevicePresent return
EFI_NOT_FOUND for devices which are not enabled either for memory or I/O
accesses.
TEST=Build and run CorebootPayloadPkg on Quark/Galileo Gen2
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
DuetPkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/DuetPkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
b/DuetPkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
index 80b2b6b..648d17c 100644
--- a/DuetPkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
+++ b/DuetPkg/PciBusNoEnumerationDxe/PciEnumeratorSupport.c
@@ -166,7 +166,14 @@ Returns:
Pci
);
-return EFI_SUCCESS;
+//
+// Only return success if the device is enabled
+//
+if (Pci->Hdr.Command & (EFI_PCI_COMMAND_IO_SPACE
+ | EFI_PCI_COMMAND_MEMORY_SPACE)) {
+
+ return EFI_SUCCESS;
+}
}
return EFI_NOT_FOUND;
--
1.9.1
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